JPS5515583A - Bit slice type arithmetic circuit - Google Patents

Bit slice type arithmetic circuit

Info

Publication number
JPS5515583A
JPS5515583A JP8957778A JP8957778A JPS5515583A JP S5515583 A JPS5515583 A JP S5515583A JP 8957778 A JP8957778 A JP 8957778A JP 8957778 A JP8957778 A JP 8957778A JP S5515583 A JPS5515583 A JP S5515583A
Authority
JP
Japan
Prior art keywords
carry
output
circuits
arithmetic
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8957778A
Other languages
Japanese (ja)
Other versions
JPS6129018B2 (en
Inventor
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8957778A priority Critical patent/JPS5515583A/en
Publication of JPS5515583A publication Critical patent/JPS5515583A/en
Publication of JPS6129018B2 publication Critical patent/JPS6129018B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To reduce apparent look-ahead carry circuits in number by making it possible to generate a carry generation output and carry propagating output by building a carry look-ahead circuit with a carry control input in each arithmetic circuit.
CONSTITUTION: Input-stage logic circuits 51 to 54 generate outputs Xi and Yi (i=0W3) by two input data A=A0WA3 and B=B0WB3 and arithmetic control signals S0 to S4. In case of arithmetic of S4=1, internal carry generating circuits 55 to 58 carry digits from lower bits to upper bits and in case of logical operation of S4= 0, the content of output Yi is outputted, as it is, to arithmetic result Fi. Carry signal 50 supplied to circuits 55 to 58 is formed on the basis of a lower arithmetic circuit. When control input M is zero, the output of gate 66 is 1 while that of gate 68 is 0, so that carry generation output G and carry propagation output P will be determined only by input data A and B. In case of M=1, the output of gate 66 indicates that three lower arithmetic circuits are under the carry propagation conditon, thereby making it possible to reduce apparent look-ahead circuits.
COPYRIGHT: (C)1980,JPO&Japio
JP8957778A 1978-07-21 1978-07-21 Bit slice type arithmetic circuit Granted JPS5515583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8957778A JPS5515583A (en) 1978-07-21 1978-07-21 Bit slice type arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8957778A JPS5515583A (en) 1978-07-21 1978-07-21 Bit slice type arithmetic circuit

Publications (2)

Publication Number Publication Date
JPS5515583A true JPS5515583A (en) 1980-02-02
JPS6129018B2 JPS6129018B2 (en) 1986-07-03

Family

ID=13974646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8957778A Granted JPS5515583A (en) 1978-07-21 1978-07-21 Bit slice type arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS5515583A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848142A (en) * 1981-09-17 1983-03-22 Toshiba Corp High-speed adding circuit
EP0242600A2 (en) * 1986-03-20 1987-10-28 Kabushiki Kaisha Toshiba Carry look-ahead calculating method and circuits therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848142A (en) * 1981-09-17 1983-03-22 Toshiba Corp High-speed adding circuit
EP0242600A2 (en) * 1986-03-20 1987-10-28 Kabushiki Kaisha Toshiba Carry look-ahead calculating method and circuits therefor

Also Published As

Publication number Publication date
JPS6129018B2 (en) 1986-07-03

Similar Documents

Publication Publication Date Title
JPS5650439A (en) Binary multiplier cell circuit
JPS54109354A (en) Digital filter
JPS5515583A (en) Bit slice type arithmetic circuit
JPS55105732A (en) Multiplier
JPS554697A (en) Arithmetic and logic unit using basic cell
JPS5477533A (en) Signal generating device
JPS56152046A (en) Arithmetic and logic circuit
JPS5696328A (en) Logical arithmetic operating device
JPS5668841A (en) Gate control system
JPS55134455A (en) Parity forming circuit
JPS5572261A (en) Logic unit
JPS52140241A (en) Binary #-digit addition circuit
JPS5417644A (en) Electronic minicomputer
JPS5518706A (en) Parallel adder circuit
JPS6476221A (en) Logical operating circuit
JPS54137251A (en) Code conversion system
JPS5474324A (en) Generating circuit for border of multi-division screen
JPS5595138A (en) Input data discrimination system of data input unit
JPS5685127A (en) Digital signal processor
JPS54125378A (en) Input-output unit for sequence controller
JPS6486271A (en) Accumulator
JPS5679529A (en) Logic circuit
JPS5771045A (en) Digital mulitplier
JPS56138325A (en) Flip-flop circuit of set and reset type
JPS52124835A (en) Level conversion circuit