JPS54137251A - Code conversion system - Google Patents

Code conversion system

Info

Publication number
JPS54137251A
JPS54137251A JP4507678A JP4507678A JPS54137251A JP S54137251 A JPS54137251 A JP S54137251A JP 4507678 A JP4507678 A JP 4507678A JP 4507678 A JP4507678 A JP 4507678A JP S54137251 A JPS54137251 A JP S54137251A
Authority
JP
Japan
Prior art keywords
data
control signal
address bit
code conversion
roma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4507678A
Other languages
Japanese (ja)
Inventor
Katsuki Takaku
Toshiki Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4507678A priority Critical patent/JPS54137251A/en
Publication of JPS54137251A publication Critical patent/JPS54137251A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the circuit constitution with a reduced number of the elements and then to enhance the reliability and the packing density by putting the control signal into the address bit of the highest-rank of ROM and then selecting the data output based on the state of the control signal.
CONSTITUTION: ROMA features the address bit of 2n+1; input data C1WCn are supplied to address bits A1WAn; and control signal S is introduced into high- rank address bit An+1 from CPU. Signal S features logic 1 or 0 mode, and output data E1WEn same as data C1WCn or data E1WEn obtained through code conversion of C1WCn are delivered from ROMA according to the mode of 1 or 0. Thus, the selector can be omitted to simplify the circuit constitution.
COPYRIGHT: (C)1979,JPO&Japio
JP4507678A 1978-04-17 1978-04-17 Code conversion system Pending JPS54137251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4507678A JPS54137251A (en) 1978-04-17 1978-04-17 Code conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4507678A JPS54137251A (en) 1978-04-17 1978-04-17 Code conversion system

Publications (1)

Publication Number Publication Date
JPS54137251A true JPS54137251A (en) 1979-10-24

Family

ID=12709236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4507678A Pending JPS54137251A (en) 1978-04-17 1978-04-17 Code conversion system

Country Status (1)

Country Link
JP (1) JPS54137251A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5798039A (en) * 1980-12-12 1982-06-18 Nec Corp Decoding circuit
JPS61134998A (en) * 1984-12-04 1986-06-23 Nec Corp Read-only memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5798039A (en) * 1980-12-12 1982-06-18 Nec Corp Decoding circuit
JPS61134998A (en) * 1984-12-04 1986-06-23 Nec Corp Read-only memory

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