JPS56152046A - Arithmetic and logic circuit - Google Patents

Arithmetic and logic circuit

Info

Publication number
JPS56152046A
JPS56152046A JP5507080A JP5507080A JPS56152046A JP S56152046 A JPS56152046 A JP S56152046A JP 5507080 A JP5507080 A JP 5507080A JP 5507080 A JP5507080 A JP 5507080A JP S56152046 A JPS56152046 A JP S56152046A
Authority
JP
Japan
Prior art keywords
carry
signal
generation
output
negation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5507080A
Other languages
Japanese (ja)
Other versions
JPS6042491B2 (en
Inventor
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55055070A priority Critical patent/JPS6042491B2/en
Publication of JPS56152046A publication Critical patent/JPS56152046A/en
Publication of JPS6042491B2 publication Critical patent/JPS6042491B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To eliminate an increase in delay due to wired OR by generating a carry- generation negation signal and carry-propagation negation signal at an input part, by performing wired AND by a carry look ahead circuit, and by selecting a data output result set up at an output part. CONSTITUTION:(n)-Bit binary data inputs A0-A3 and B0-B3, and arithmetic control inputs S0-S3 are inputted to input part 51-54 to generate a negation signal for the generation of a carry, carry generation signal, and negation signal for carry propagation as to every bit. Those negation signals for carry generation and propagation are applied to group carry signal generation part 55, which generate an (n)-bit group carry generation signal and group carry propagation signal to output the 1st or 2nd data from data output generation part 56 according to whether a carry from the low-order group is generated or not. Those 1st and 2nd output results are applied to data output selection parts 61-64 to select the output of output generation part 55, thereby preventing an increase in delay due to wired OR.
JP55055070A 1980-04-25 1980-04-25 Arithmetic logic circuit Expired JPS6042491B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55055070A JPS6042491B2 (en) 1980-04-25 1980-04-25 Arithmetic logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55055070A JPS6042491B2 (en) 1980-04-25 1980-04-25 Arithmetic logic circuit

Publications (2)

Publication Number Publication Date
JPS56152046A true JPS56152046A (en) 1981-11-25
JPS6042491B2 JPS6042491B2 (en) 1985-09-24

Family

ID=12988428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55055070A Expired JPS6042491B2 (en) 1980-04-25 1980-04-25 Arithmetic logic circuit

Country Status (1)

Country Link
JP (1) JPS6042491B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225437A (en) * 1982-06-24 1983-12-27 Panafacom Ltd Carry look-ahead adder
JPS59186043A (en) * 1983-03-31 1984-10-22 ジ−メンス・アクチエンゲゼルシヤフト Parallel connection circuit
JPS6069735A (en) * 1983-09-26 1985-04-20 Nec Corp Adder
JPS61296427A (en) * 1985-06-25 1986-12-27 Nec Corp Arithmetic logical unit and its driving method
JPS62500474A (en) * 1985-01-31 1987-02-26 バロ−ス・コ−ポレ−シヨン High speed BCD/binary adder
EP0242600A2 (en) * 1986-03-20 1987-10-28 Kabushiki Kaisha Toshiba Carry look-ahead calculating method and circuits therefor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225437A (en) * 1982-06-24 1983-12-27 Panafacom Ltd Carry look-ahead adder
JPS59186043A (en) * 1983-03-31 1984-10-22 ジ−メンス・アクチエンゲゼルシヤフト Parallel connection circuit
JPS6069735A (en) * 1983-09-26 1985-04-20 Nec Corp Adder
JPS62500474A (en) * 1985-01-31 1987-02-26 バロ−ス・コ−ポレ−シヨン High speed BCD/binary adder
JPH0577095B2 (en) * 1985-01-31 1993-10-26 Unisys Corp
JPS61296427A (en) * 1985-06-25 1986-12-27 Nec Corp Arithmetic logical unit and its driving method
EP0242600A2 (en) * 1986-03-20 1987-10-28 Kabushiki Kaisha Toshiba Carry look-ahead calculating method and circuits therefor

Also Published As

Publication number Publication date
JPS6042491B2 (en) 1985-09-24

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