JPS6069735A - Adder - Google Patents

Abstract

PURPOSE:To shorten an addition arithmetic time greatly by calculating both sums when an intergroup carry signal from a low-order group arrives and when not previously and respectively, and selecting them according to the decision of the intergroup carry signal. CONSTITUTION:Addends A4n-1-A4n-4 and augends B4n-1-B4n-4 which are divided by four bits are supplied to the 1st and the 2nd CLA adders consisting of G-P generating circuits 100-n-1 and 100-n-2 and adding circuits 200-n-1 and 200- n-2. Then, addition when there is no intergroup carry signal and addition when there is the intergroup carry signal are carried out, and outputs are supplied to selecting circuits 400-n-0-400-n-4. An input value supplied to the 2nd or the 1st CLA adder is selected according to whether the intergroup carry signal Xn from a low-order group has a logical value ''1'' or ''0'' to output signals S4n-1-S4n-4 of respective digits of the calculation result and an intergroup carry signal to the high-order group.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to adders and, more particularly, to circuit implementation of multi-digit high speed parallel adders.

Traditionally, faster? The target adder has one-digit advance look-ahead (c
carry 1ook ahe, ad Hereinafter referred to as CLA] A carry signal (carry
) The most common and widely used method is to predetermine t in advance and add the result to each bit by t.

However, if the word length is about 4 digits, the scale of the logic circuit required to generate the carry signal is not that complicated, but as the number of digits increases, the complexity increases and the time required to generate it also decreases. This has the disadvantage that it occupies a large area on the chip.

To improve this, there are cases in which a CLA addition adder bottom is constructed by dividing each small number of bits (for example, 4 bits) into groups, or, for example, there is a carry between groups for every 4 bits, and each bit in the upper group is The generation of the carry signal starts after the supply of the carry signal t of the lower group.

FIG. 1 shows a block diagram of a conventional CLA adder. The CLA adder shown in FIG. 1 is a binary adder with both addend A and summand B under 4m digits μ.

The digit positions of the digits that make up the following several tones are indicated by the +j fix of the symbol that indicates the total number of digits. For example, the n-th digit of the addend A is indicated by Ant. Since the calculation involves 4m digits, m groups are created by dividing each bit into groups as described above, and each is calculated by the CLA adders 1-1 to 1-m, and when necessary, a group development up signal is sent to the upper group. supply.

This will be explained using the CLA adder '1cLA adder l-1 of each group as an example. The CLA adder 1-1 includes a carry generation function signal and carry propagation function signal generation circuit (hereinafter referred to as a G-P generation circuit) 10-1, and a carry signal generation circuit 20-1.
1 and an adder circuit 30-1.

(the last four digits of the addend) A3. A2. AI and AO
and the last four digits of the summand) Ba, B2. Bl and BO are supplied to the G-P generation circuit 10-1, which generates four carry generation function signals G and four carry propagation function signals P, which are respectively sent to the carry signal generation circuit 20-1. supply

The logical formula for generating the G and P signals is as follows (2).The carry signal generating circuit 20-1 generates the carry signal c2 in response to the supply of the G and P signals and the group development raise signal from the lower group.
The most significant carry signal generated is supplied to the upper group and the others are supplied to the adder circuit 30-1.The generation logic formula is as follows: Cn+x = On m Pn +On・-----■
The adder circuit 30-1 performs this addition in response to the above-mentioned carry signal C, the group development raise signal from the lower group, and the P@ number from the G-P generator circuit 10-1. Digit addition result Sn f Output Sn = Cn-1-Pn In this way, carry signal generation port Vl&2O-yL and addition circuit 30-1 are CLA adder 1-1? However, the other CLA adders 1-2 to 1-m become operational only after a group development raising signal is supplied from a lower group.

FIG. 2 is a time chart showing the entire calculation time. tl
represents the time required to generate the P signal G@, t2 represents the time required to generate a carry signal for each bit, and ta represents the total time required for addition. Here, as described above, the upper groups of group 2 and above are generated after the carry signal generation of the lower groups is completed.

However, the time indicated by the dotted line in FIG. 2 becomes the time for waiting for processing of the lower group, which is completely wasted time and has the disadvantage that the calculation time becomes longer.

The purpose of the present invention is to perform multi-digit addition 7 by dividing the addend and summand into a plurality of groups, each consisting of a plurality of bits, with or without a group development signal from the lower order for each group. The purpose is to provide a high-speed adder by calculating both of them in a CLA adder and selecting either one of the calculation results in response to a group cultivation raising signal from a lower group.

The adder of the present invention is an adder that performs all additions of binary numbers of multiple digits. For each group of at least two or more digits, a first carry look-ahead addition means that calculates in advance the case where there is no carry from the lower group, and a second carry look-ahead addition means that calculates in advance for a certain case; and a supply of the calculation results of the first carry look-ahead addition means and the calculation results of the second carry look-ahead addition means; If there is no carry signal supplied from the above, the calculation result of the first carry look-ahead addition means is selected as the calculation result of each digit of the group and the carry signal to the upper group, and the carry signal is supplied. In this case, the calculation result of the second carry look-ahead addition means is selected and outputted as the calculation result of each digit of the group and a carry signal to the upper group.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows a block diagram of one group (nth) divided into four bits each in the first embodiment of the present invention. The adder in FIG. 3 includes a first CLA adder consisting of a GP generation circuit 100-n-1, a carry signal and addition circuit 200-n-1, and a GP generation circuit 100-n-1. 2 and a carry signal and addition circuit 200-n-2.
CLA adder and five selection circuits 400-11-0~
400-n-4.

Addends A4n-1 to A4n-4 and summands B4n-1 to B1
n-4 is supplied, the first CLA adder performs the addition in the absence of the group development raise signal.
The A adder performs addition when there is a group development increase signal, and each adder selects circuits 400-n-Q~4.
Supply to 00-n-4. In other words, the carry signal generation circuit 2 Q -n-1 of the first CLA adder and the addition circuit 30
- n-1 is supplied with a fixed group development raising signal of logic "0'" in advance, and the carry signal generation circuit 20-n-2 of the second CLA adder and the adder circuit 30-
A fixed group development raising signal of logic "1" is supplied to n-2 in advance.

The selection circuits 400-n-0 to 400-n-4 are the first CL
The A adder and the second CLA adder each supply a four-bit logical value of the addition result of the same digit and a group development raising signal. Selection circuit 400-n-0 to 400
Which input value or output value -n-4 is supplied as is determined by the group development raising signal Xn from the lower group. That is, the supplied group development signal X
When the logic [direct] of n is "1" (corresponding to the case where there is a group development raising signal from a lower group), the valley selection circuit selects all input values supplied from the second CLA adder and supplies The group development raising signal Xn that is to be
In the case (corresponding to the case where there is no group cultivation raising signal from the lower group), each selection circuit selects all input values supplied from the first CLA adder, and outputs the calculation result q! Output signals 54n-1 to 84n-4 of r digits and group development raising signal Xn-H2 to the upper group are generated.

FIG. 4 shows an example of the complete configuration of an adder having a large number of digits (4 m digits), each of m groups shown in FIG. 3 being cascaded. Each group is supplied with all the addends and summands divided into 4-digit units, and based on this, calculations are made in advance for both the case with and without the group development signal, and the groups from the lower groups are calculated in advance. In response to the determination of the cultivation raising signals (X2 to Xm), output signals 84111-1 to SOk are selected.

FIG. 5 shows a time chart i of calculation time of the first embodiment shown in FIG. As mentioned above, tl is the P signal.

The time required to generate the G signal, tz represents the time required to generate a carry signal for each bit, and ta represents the time required for addition. t4 is the time when the selection circuit selects all output signals in response to the group development signal supplied from the lower group.

As is clear from FIG. 5, the total calculation time T of the first embodiment shown in FIG. 4 is expressed by the following equation.

'I''w tl+12+t3+(tn-1) t4 On the other hand, in the conventional CLA adder, as is clear from FIG. 2, the total operation time TO is expressed by the following equation.

To=tx+mtz-4-ta Here, t4 is the transmission time of the two-manpower selection circuit t) Time required to generate a carry signal It is 1.

tz)t4 Therefore TO-T-ΔT=(m-1)(tz-t4)>.

As can be seen from the above equation, compared to the conventional CI and A adders,
The calculation time of the embodiment is improved by IT, and the effect becomes more significant as the number of digits increases.

FIG. 6 shows a block diagram of a second embodiment of the invention. Compared to the first embodiment, the second embodiment has only one GP generation circuit, and can contribute to a reduction in hardware compared to the first embodiment. The operation and other effects are the same as those in the first embodiment, so explanations will be omitted.

In the present invention, is the addition both with and without a group development signal from a lower group in advance? By determining the selection of the output signal in response to the determination of the group development raise signal from the lower group, what is the addition calculation time in the case of a large number of digits? This has the effect of significantly shortening the time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional carry look-ahead adder, FIG. 2 is a time chart of its operation time, FIG. 3 is a block diagram of an l group showing the first embodiment of the present invention, and FIG. 4 is a block diagram of a conventional carry look-ahead adder. 3 is a connection diagram for a plurality of groups, FIG. 5 is a time chart of calculation time in the embodiment of FIG. 4, and FIG. 6 is a block diagram showing a second embodiment of the present invention. 1-1.1-m...Creation look-ahead adder (CLA)
Adder, 2-1. 2-m, 200-n-1,200
-n-2... Carry signal and addition circuit, 10-
1°10-m, Zoo -1,100-n-1,100
-n-2...Carry generation function signal and carry propagation function signal generation circuit (G-P generation circuit), 20-1゜20-m, 2O-n-1, 2O-n-2 -=Carry signal generation circuit, 30-1. 30-m, 3O-n-1,3
Q-n-2...-"addition circuit, 400-n-0 to 40
0-n-4...Selection circuit. Agent Patent Attorney Uchihara 2'''511, -7 1, 11 Jin.

Claims (2)

[Claims] (1) In an adder that performs addition of multiple digit binary numbers,
The plurality of digits are divided into a plurality of groups each consisting of at least two digits. A first carry look-ahead addition means that calculates in advance when there is no carry from the lower group; and a second carry look-ahead addition means that calculates in advance when there is a carry from the lower group. If there is no carry signal supplied from the lower group due to the supply of the calculation result of the first carry lookahead addition means and the calculation result of the second carry lookahead addition means, the first digit The calculation result of the advance look-ahead addition means is selected as the calculation result of each digit of the group and the carry signal to the upper group, and if there is the carry signal, the calculation result of the second carry look-ahead addition means is An adder comprising a selection output means for selecting and outputting a calculation result of each digit of a group and a carry signal to an upper group. (2) The first carry lookahead addition means and the second carry lookahead addition means provided in each group are characterized in that they include the only common carry generation function signal and carry propagation function signal generation means. A Q adder according to claim (1).