GB2189630A - Multiplier - Google Patents

Abstract

A known method of fast multiplication in binary systems is the modified Booth algorithm, in which the multiplier is encoded into three bit data groups or triplets, nine such triplets being derived from a 16 bit multiplier, thirteen such triplets being derived from a 24 bit multiplier. The value of such a triplet determines what if any multiple of the multiplicand is added to the partial product. Sets of multiplexers are fed from the multiplicand under the control of the Booth encoded digits. In the present arrangement, the multiplexers are in three groups, MUX1-MUX3, MUX4-MUX6 and MUX7-MUX9, with the groups operating in parallel and simultaneously. Within each group the outputs are summed by adders ADD1A, ADD1B, ADD1C respectively, and the outputs of these adders are themselves summed in a final stage of adders ADD2, ADD3, ADD4, ACA. This gives a faster operating multiplication circuit than hitherto known arrangements. <IMAGE>

Description

SPECIFICATION Multiplier The present invention relates to binary multiplication circuits.

One of the disadvantages of conventional methods of multiplication of binary numbers is the large number of steps needed to do the operation. This in turn usually means that the operation takes a relatively long time. To minimise this disadvantage, uniform shift algorithms have been proposed which require no sign correction for two's complement numbers, and where the decoding of multiplier bits can begin from either direction. One case in which these conditions apply is in certain forms of digital signal processing. The most important advantage of such algorithms is that they reduce the number of partial product terms to be summed, and hence speed up the operation.

The basis of these algorithms is to examine at each step (Q+ 1) bits of an N-bit multiplier and to add or subtract a properly selected multiple of the multiplicand to form a partial product. The final product is obtained after N/Q such partial products have been formed and added together.

Theoretically any value of 0 can be used, but in practice the case where Q=2 is the most important as it is convenient from the aspect of hardware implementations. This is because the factor by which the multiplicand may be multiplied before being added to or subtracted from the other partial products is 0, 1 or 2. For binary numbers this involves adding zero in the multiplicand or its inverse shifted left by one position. Where the inverse is added, an extra bit must be inserted at the position for the least significant bit to correctly perform subtraction by two's complement addition. This is the modified Booth algorithm (see O.L. MacSorley, High Speed Arithmetic in Binary Computer, Proc. IRE 49, pp 67-91, January (1961)).

The modified Booth algorithm uses sets of three bits, or triplets, and the first of these triplets includes the least significant two bits, plus a notional zero at the least significant bit end. In addition, if necessary to make up the triplets, one or two zeros are added at the most significant bit end. Furthermore! the triplets overlap. Thus if the multiplier is 01010, it is recoded to [0]01010[0], the two added zeroes being indicated in square brackets. This would involve the following triplets, starting from the least significant bit end: 100,101,001.These are then used to select products of the multiplicand in accordance with the following table: Modified Booth Recoding Table Next Bit Present Bit Previous Bit Recoded Bit Action on multiplicand O 0 0 O ZERO O 0 1 +1 ADD O 1 0 +1 ADD O 1 1 +2 ADD X2 1 1 0 0 ~ -2 SUB X2 1 0 1 -1 SUB 1 1 0 -1 SUB 1 1 1 0 ZERO The control signals ADD, SUB, ZERO, ADD X2 and SUB X2 are generated from the multiplier using Booth encoding logic to determine which operation should be performed on the multiplicand at each stage.Where we have SUB to subtract we in fact add the two's complement, and where we have X2 we also perform a single left shift on the two's complement before adding.

Thus we consider multiplying 13 (binary 01101) by 10 (binary 01010), assuming five bit operands. The two's complement of 01101 is 10011. Thus we have the following operations: 01101 [two's complement 10011 ] 01010 X The multiplier is recoded as 0010100, which gives three triplets, as mentioned above, 100, 101 and 001.

Thus we have the following operations: 01101 (2's complement = 10011) 01010 x r recode multiplier: (duplicate MSB)

(a) 111100110 partial products (b) 1110011 (c) 01101 + result 010000010 [ = 130 ] The multiplier is extended to 0010100 which gives three triplets as mentioned above, 100, 101 and 001. Using the recoding table these provide the partial products (a) (b) and (c) respectively.

Partial product (a) is the -2 product, since the triplet is 100, with all digits to the left of the most significant bit represented as l's, since this partial product is a complement. The next partial product (b) is the~1 product, since the triplet is 101, and this is shifted two, positions with respect to (a). Finally, partial product (c) is +1, since the triplet is 001, and this is shifted two positions with respect to (b). The sum of these three partial products, which are handled as simple binary numbers, 1, will be seen to represent 130 in decimal notation.

Fig. 1 of the accompanying drawings shows a multiplexer consisting of five CMOS switches which is used to select the appropriate operation at the nth bit position of the multiplicand input.

In the present case 0=2 so that we have the five possible conditions set out in the table, i.e.

+2, +1, O, ~1, ~2.

Figure 2 indicates the bit positions on which each Booth encoding multiplexer operates, the example relating to a 16 digit multiplier. Thus it will be seen that nine rows of multiplexers are needed to encode a 16 bit number.

A simple extension of this figure shows that a 24 bit x 24 bit multiplier needs a total of 13 rows of multiplexers.

Fig. 3 shows in a highly schematic manner a standard Booth multiplier, where the product is formed by summating the outputs from the nine multiplexers in sequence. Although this will seem at first glance to involve a great deal of circuitry this is not in fact a serious consideration in view of the relative cheapness of integrated circuit units. The connections between various elements of the arrangement are not shown in detail since they would be clear to one skilled in the art. The add rows are rows of full adders which produce a sum and carry input to the next row of adders.

The first adder row ADD1 combines the outputs from the first three multiplexers, MUXI, MUX2, MUX3. Thereafter each adder row combines the sum and carry outputs from the previous adder row with the output from one multiplexer, e.g. ADD2 combines MUX4 output with the output from ADD1. There is no carry propagation along the adder rows. The carry outputs from each row of full adders are connected to an input of the next adder row at the next most significant bit positions (e.g. carry out from bit 6, ADD row 2 is input to bit 7 ADD row 3).

It is necessary at each stage to duplicate the Most Significant Bit MSB (sign-extend) so that the subtract twice SUBX2 (shift and subtract) operation gives a valid result.

Subtraction, as already indicated, uses two's complement addition; this involves adding the inverse of the number to be subtracted and adding a further 1 at the Least Significant Bit. In this arrangement there is not a free input for this 1 to be added, so two extra adders are included, marked by diagonal lines at the ends of the ADD blocks. These are used to add in the extra 1 for the subtract SUB and subtract twice SUBX2 operations. The sums and carries from the final adder stage are combined in a carry propagated adder to form the final result.

An object of the present invention is to provide a multiplier based on the modified Booth algorithm, but in which speed of operation is improved.

According to the invention there is provided an electronic digital multiplication circuit operating in accordance with a modified Booth algorithm, in which multiplexers used to derive the partial products under the control of Booth-encoded digits derived from the multiplier digits are arranged in a plurality of parallel groups of multiplexers, in which the outputs of the multiplexers are summated by adders individual to the respective groups of multiplexers, and in which the outputs of said group adders are themselves summated by a second stage of adders to derive the product of the multiplier and of the multiplicand.

Such an arrangement permits parallel summation of Booth encoded terms, and has fewer gate delays from input to output than existing Booth multipliers.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Fig. 4 shows schematically a parallel architecture modified Booth encoded multiplier circuit embodying the invention for sixteen bit multiplication.

Fig. 5 shows how the interconnections are made between multiplexers and adders at a single bit position where the outputs of all nine multiplexers are being combined to form three sum and three carry bits.

Fig. 6 shows the carry save addition arrangements used to combine the six bits, three sum and three carry, derived by an arrangement as shown in Fig. 5, using three rows of full adders, two per bit position in the first row, shown at the bottom of Fig. 4.

Fig. 7 is a schematic representation, similar to Fig. 4, of an implementation of a twenty four bit Booth multiplier, with an insert representing one bit place of adders (in Fig. 6).

We now refer to Fig. 4, which shows in the same manner as Fig. 3, a multiplier embodying the invention for handling sixteen bit multipliers, the Booth encoding being effected in the manner shown in Fig. 2. The nine multiplexers MUX1 to MUX9 are divided into three parallel groups each of three multiplexers, and the outputs from each group are combined in a single full adder row. Thus the outputs from MUX1, MUX2, MUX3 are combined in full adder row ADDIA, the outputs from MUX4, MUX5, MUX6 are combined in ADDIB and the outputs from MUX7, MUX8, MUX9 are combined in ADD1C. As shown by the diagonally lined areas extra adders are used to include the extra two's complement bits, although some of them are not included until the carry save adders ADD2, ADD3, ADD4, referred to later.

When subtraction (SUB or SUBX2) is to occur, a two's complement bit must be inserted at the multiplexer's least significant bit position. If SUBX2 is selected, the multiplexer will always select a '1' at this bit position so that the two's complement bit will propagate upon addition to the next most significant bit, as required. Thus a single "twos complement" bit is sufficient for both subtract operations. This bit can be incorporated either in the add 1 row, or in the carry save adder tree, to be described, which is at the bottom of the multiplier diagram. In the case of 16 bit multiplication an extra two adders, indicated by a diagonal line are included in row add 1c to handle the twos complement bit from MUX8. This would otherwise represent a seventh input bit to the carry save adder tree at this bit position.All other two's complement bits can be added into the carry save adder tree without complication.

The "multiplier" input to the multiplier is applied to the Booth encoder blocks, where its digits are formed into the nine triplets in the manner shown in Fig. 2. These encoded triplets then control the multiplexers as indicated by the arrowed connections leaving the encoder blocks in Fig. 4. The multiplicand is applied to the multiplexers, so that the various products derived therefrom, i.e. +2, +1, 0, 1, - 1, -2, as required are developed and passed to the adders.

The three groups A, B and C, evaluate in parallel and each produces a sum and carry output, see Fig. 5. Hence at most there are six bits to combine at each bit position, i.e. three sum bits and three carry bits, to produce the final result. This is achieved, see Fig. 6, with three rows FA1, FA2, and FA3, and finally FA4, of full adders. These correspond to the carry save adder rows ADD2, ADD3, ADD4, shown in Fig. 4. The carry and sum digits shown issuing forth from this adder tree form the inputs to the various bit positions of the last stage, Fig. 4, which is an Accelerated Carry Adder stage ACA.

Note here that carry propagation does not occur until the final stage ACA.

The carry propagation along the length of the multiplier result makes a significant contribution to the overall speed of the multiplier. It is therefore necessary to employ an accelerated carry circuit, although it is expensive in silicon area when implemented as an integrated circuit. Severall carry accelerate schemes are known, including carry select, carry lookahead, and Manchester carry chain. All would operate satisfactorily in the current arrangement and the final choice is dictated by which circuit will operate the fastest in the silicon technology chosen for implementation.

Both the sequential multiplier, Fig. 3, and the novel parallel multiplier, Fig. 4, have the same number of gate delays in the Booth encoder, multiplexer and carry propagate adder stages.

However, the parallel arrangement reduces the number of full adder delays from, in the case of 16 bit multipliers, seven to four. It is, however, necessary to sign extend the MSB of ADD1A and ADD 1 B up to the MSB of the result rather than simply by one bit.

Thus the novel parallel arrangement of a modified Booth multiplier provides a considerable speed improvement on existing designs. Note that for larger multipliers than sixteen bit, the speed saving would be even greater.

We now consider Fig. 5 in more detail. Here we see the three multiplexers at each stage of the addition feeding into respective full adders, each of which produces its carry digit and its sum digit. From this figure it is felt that the manner of interconnection is clear to one skilled in the art.

Fig. 7 shows how the parallel scheme is implemented for 24 bit X 24 bit multiplication. The thirteen multiplexers correspond to the thirteen Booth encoded terms referred to above. The multiplexers are grouped into four groups of three to provide inputs to the adder rows ADD 1 A, ADD1B, ADD1C and ADD1D. The final multiplexer, MUX13, provides an input directly to the carry save adder tree. Analysis shows that at most nine bits must be combined at any one bit position in the carry save adder tree. The insert shows how this can be achieved with four rows of adders; the first row containing three and the second row two adders per bit position. The diagonal arrows indicate the propagation of carry bits. The parallel arrangement reduces the number of full adder delays from twenty one for the known sequential arrangement (Fig. 3) to five for 24 bit multiplications.

We have mentioned that one application of such multipliers is to digital signal processing arrangements where a great number of multiplication operations are effected. Thus the multiplier could be used in the so-called node chip for an adaptive antenna arrangement. The node chip is described in some detail in our Application No. (C.R. Ward et al 10-2-1); this chip is a processor chip with separate provision for multiplication.

Such a multiplier is, however, of much more general application, and is usable wherever high speed multiplication is needed.

Claims (4)

1. An electronic digital multiplication circuit operating in accordance with a modified Booth algorithm, in which multiplexers used to derive the partial products under the control of Boothencoded digits derived from the multiplier digits are arranged in a plurality of parallel groups of multiplexers, in which the outputs of the multiplexers are summated by adders individual to the respective groups of multiplexers, and in which the outputs of said group adders are themselves summated by a second stage of adders to derive the product of the multiplier and of the multiplicand.

2. An electronic digital multiplication circuit operating in accordance with a modified Booth algorithm, in which multiplexers used to derive the partial products under the control of Boothencoded digits derived from the multiplier digits are arranged in a plurality of parallel groups of multiplexers, each such group including three multiplexers, in which for each said group the outputs from the multiplexers are combined in a single row of adders, in which extra adders may be included in each said row of adders to deal with extra two's complement bits where necessary as required by the modified Booth algorithm, in which said groups of multiplexers operate in parallel fashion with each said group producing a sum output and a carry output, inwhich a second stage of adders is provided, which second set of adders summates the output from said rows of adders, and in which said second set of adders feeds an accelerated carry adder which produces the final product of the multiplier and the multiplicand.

3. A circuit as claimed in claim 2, in which the multipliers to be handled each has sixteen binary bits, so that nine Booth encoded sets each of three binary bits are derived from the multiplier, and in which there are three groups of multiplexers, each consisting of three multiplexers.

4. An electronic multiplication circuit, substantially as described with reference to Figs. 4, 5 and 6, or Fig. 7 of the accompanying drawings.

4. A circuit as claimed in claim 2, in which the multiplexers to be handled each has twentyfour binary bits, so that thirteen Booth encoded sets each of three binary bits are derived from the multiplier, and in which there are four groups of multiplexers each consisting of three multiplexers, plus a thirteenth multiplexer.