JPS57147754A - Digital parallel adder - Google Patents

Digital parallel adder

Info

Publication number
JPS57147754A
JPS57147754A JP3227781A JP3227781A JPS57147754A JP S57147754 A JPS57147754 A JP S57147754A JP 3227781 A JP3227781 A JP 3227781A JP 3227781 A JP3227781 A JP 3227781A JP S57147754 A JPS57147754 A JP S57147754A
Authority
JP
Japan
Prior art keywords
adder
carrying
decided
output
partial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3227781A
Other languages
Japanese (ja)
Other versions
JPS6230451B2 (en
Inventor
Takehiro Moriya
Yukio Akazawa
Atsushi Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3227781A priority Critical patent/JPS57147754A/en
Publication of JPS57147754A publication Critical patent/JPS57147754A/en
Publication of JPS6230451B2 publication Critical patent/JPS6230451B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To contrive the increase in carrying speed, by optimizing the constitution of each partial adder, so that delays in a partial adder and those of signals successively propagated from a lower-rank adder may coincide with each other. CONSTITUTION:Carrying logical operation circuits 11, 12, 15, 16, 19, and 20 output a carry composed of an augend A, an addend B, and a carrying input CIN. Adders 13, 17, and 21 output a sum, S=A+B+C, from the augend A, the addend B, and the carrying input C. While the carry CIN changes over a selecting circuit 14, candidates C0<1> and C0<0> to be carried are obtained, and thus, a real carry C0 is decided effectively. While a candidate to be carried is successively decided as C1<1> C2<1> or C1<0> C2<0> in the second partial adding, the output of the lower-rank partial adder is decided in parallel as CIN C0, and those results are decided simultaneously as the output of COUT. When such arrangement is made, carrying signals can effectively be sent to the upper-rank adder two-demensinally, and therefore, high-speed operations can be made with a small circuit scale.
JP3227781A 1981-03-06 1981-03-06 Digital parallel adder Granted JPS57147754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3227781A JPS57147754A (en) 1981-03-06 1981-03-06 Digital parallel adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3227781A JPS57147754A (en) 1981-03-06 1981-03-06 Digital parallel adder

Publications (2)

Publication Number Publication Date
JPS57147754A true JPS57147754A (en) 1982-09-11
JPS6230451B2 JPS6230451B2 (en) 1987-07-02

Family

ID=12354478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3227781A Granted JPS57147754A (en) 1981-03-06 1981-03-06 Digital parallel adder

Country Status (1)

Country Link
JP (1) JPS57147754A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154542A (en) * 1983-02-23 1984-09-03 Hitachi Ltd Multiplying device
JPS6069735A (en) * 1983-09-26 1985-04-20 Nec Corp Adder
JPS60233730A (en) * 1984-04-24 1985-11-20 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Full addition circuit
JPS61110237A (en) * 1984-11-01 1986-05-28 レイセオン　カンパニ− Multi-bit digital adder
EP0334768A2 (en) * 1988-03-25 1989-09-27 Fujitsu Limited Logic circuit having carry select adders
WO1991000568A1 (en) * 1989-06-23 1991-01-10 Vlsi Technology, Inc. Conditional-sum carry structure compiler
US5047976A (en) * 1988-03-25 1991-09-10 Fujitsu Limited Logic circuit having carry select adders
JPH0561643A (en) * 1991-09-03 1993-03-12 Mitsubishi Electric Corp Carry look-ahead adder

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154542A (en) * 1983-02-23 1984-09-03 Hitachi Ltd Multiplying device
JPH0578049B2 (en) * 1983-02-23 1993-10-28 Hitachi Ltd
JPS6069735A (en) * 1983-09-26 1985-04-20 Nec Corp Adder
JPS60233730A (en) * 1984-04-24 1985-11-20 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Full addition circuit
JPH0518136B2 (en) * 1984-04-24 1993-03-11 Fuiritsupusu Furuuiranpenfuaburiken Nv
JPS61110237A (en) * 1984-11-01 1986-05-28 レイセオン　カンパニ− Multi-bit digital adder
EP0334768A2 (en) * 1988-03-25 1989-09-27 Fujitsu Limited Logic circuit having carry select adders
JPH01244531A (en) * 1988-03-25 1989-09-28 Fujitsu Ltd Logic circuit
US5047976A (en) * 1988-03-25 1991-09-10 Fujitsu Limited Logic circuit having carry select adders
WO1991000568A1 (en) * 1989-06-23 1991-01-10 Vlsi Technology, Inc. Conditional-sum carry structure compiler
US5126965A (en) * 1989-06-23 1992-06-30 Vlsi Technology, Inc. Conditional-sum carry structure compiler
JPH0561643A (en) * 1991-09-03 1993-03-12 Mitsubishi Electric Corp Carry look-ahead adder

Also Published As

Publication number Publication date
JPS6230451B2 (en) 1987-07-02

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