JPH0326857B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a multiplier used in applications that require high-speed signal processing, such as image processing. [Technical background of the invention and its problems] Various methods have been proposed as multiplier multiplication methods, but this method uses exactly the same principle as multiplication performed manually and has been realized using hardware. It is a parallel multiplier. As shown in Fig. 3, this consists of the same AND gate 11 that generates a partial product for each bit of the multiplier y and the multiplicand x, the partial products x, y, the sum output S' of the previous stage of the same digit, and A full adder 12 that adds the carry signal C' from the lower digit and obtains the addition output S and the carry signal C is one unit circuit (basic cell) 13, and this basic cell is used as the fourth
They are arranged in an array as shown in the figure.
Figure 4 shows a 4 x 4 bit multiplier, x _1
.about.x4 is a multiplicand, _y1 to _y4 are multipliers, ₁₃₁ to ₁₃₆ are basic cells, 14 is a 4-bit adder, and _S1 to _S8 are multiplication outputs. This method enables high-speed calculations because partial product generation and addition are performed in parallel. However, in the above configuration, if an n×n bit multiplier is to be formed, 2 ⁿ basic cells are required, which increases the amount of hardware. By the way, since the propagation time of a signal is generally determined by the number of stages of cells it passes through, this method uses n×n
In the bit multiplier, the basic cell is passed n times (here, only the cell array is used, and the final stage adder 1
4 is not included). Therefore, if further speeding up is desired, the number of stages through which the basic cells pass can be reduced, which also leads to a reduction in the amount of hardware. Wallace's tree is a method for reducing the number of stages that cells pass through. According to this method, the number of stages through which cells pass can be significantly reduced, and even higher speeds are expected. However, when considering LSI implementation, Wallace's tree method described above is difficult to organize the pattern shape into a rectangle and produces a large invalid area, making it unsuitable from the point of view of effective chip utilization. In addition, the required wiring is complicated,
It also has drawbacks such as non-negligible wiring delays. [Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its purpose is to enable high-speed operation, have a regular pattern suitable for LSI implementation, and achieve high integration. The objective is to provide a multiplier that can. [Summary of the Invention] In other words, in order to achieve the above object, the present invention combines the Booth algorithm and two systems of addition of the same digits in order to reduce the number of stages of passing cells. in,
By using the Booth algorithm, the number of cells passing through can be reduced to 1/2, and by using multiple paths to add the same digit, it can be reduced to about 1/2.
We aim to increase speed by reducing the total number of stages of cells that pass through to about 1/4. Also,
Since it is basically a parallel multiplier, it also maintains the regularity of the pattern. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In general, Booth's algorithm is the most commonly used method for generating partial products. This algorithm has the advantage that two's complement multiplication can be performed without correction. Now, as an example, 2 bits
I'll give you Booth and explain. When displaying in two's complement,
The multiplier Y is Y=-y _o・2 ^n-1 + _o-1 〓 ^j=1 y _i 2 ^i-1 ...(1) (y _o is the sign bit, y _o-1 ~ _{y 1} is the numerical part ). The above equation (1) can be rewritten as follows. Therefore, the multiplier P=X・Y is becomes. In (3) above, (y _2i +y _2i+1 −2y _2i+2 )
takes values of ``0'', ``±1'', and ``±2'' depending on the values of successive 3 bits (y _2i , y _2i+1 , 2y _2i+2 ), so
Depending on the partial product, it will take either 0, ±X, or ±2X. As is clear from the previous equation (3),
If Booth's algorithm is used, the number of partial products can be n/2, which is half of the number n of a normal parallel multiplier. On the other hand, as a method of reducing the number of stages of addition of partial products, as shown in FIG. 5, there is a method in which addition of the same digit is performed in two paths (for example, an even number stage and an odd number stage), and both are added at the final stage. According to this method, since n×n bit multiplication can be calculated in n/2+2 stages, a large effect is not obtained when the word length is short, but it becomes more effective as the word length becomes longer. In FIG. 5, the symbols appended with a indicate odd-numbered stages, and the symbols appended with b indicate even-numbered stages. For example, the sum output S from the basic cell 15a is
It skips over the next stage basic cell 15b and supplies it to 16a, and similarly skips one carry C and supplies it to 18a. On the other hand, for even-numbered stages, for example, 15
The sum output S from b is supplied to the basic cell 16b, and the carry C is supplied to the basic cell 18b. In this way, addition is performed separately in the even-numbered stages and odd-numbered stages, and finally the two are added together (in the figure, cell 1
9 to 22), two extra stages are required, but this effect diminishes as the word length increases. In this invention, in order to achieve high speed while maintaining pattern regularity, the above-mentioned two methods are used together to form a multiplier. FIG. 1 shows its configuration, and shows an 8×8 bit multiplier. This multiplier is constituted by basic cells 23 as shown in FIG. That is,
A sum input S _io , a carry input C _io and a multiplicand X are supplied, and their sum output S _put and carry output C _cut
The output of the exclusive NOR gate 25 is supplied to the multiplicand X input terminal of the full adder 24 which obtains . One input terminal of this exclusive NOR gate 25 is supplied with the inverted signal (-2X, -X) NEGA, and the other input terminal is supplied with the output of the NOR gate 26. At the input end of this NOR gate 26 are AND gates 27 ₁ ,
27 ₂ outputs are provided respectively. The multiplicand X is supplied to one input terminal of the AND gate ₂₇₁ , and the X selection signal SSELX is supplied to the other input terminal. Further, a signal 2X obtained by doubling the multiplicand X is supplied to one input terminal of the AND gate ₂₇₂ , and a select signal SEL2X of this 2X is supplied to the other input terminal. Such basic cells 23 are arranged in a matrix as shown in FIG. Basic cells arranged in a matrix 23 ₉ , 23 ₁₈ , 23 ₂₇ , 23 ₃₆
and 23 ₈ , 23 ₁₇ , 23 ₂₆ , 23 ₃₅ have multiplicands
_{X 0 is the multiplicand _ _ _ _ _}
However, the basic cells 23 ₇ , 23 ₁₆ , 23 ₂₅ , 23 ₃₄ and 23 ₆ , 23 ₁₅ , 23 ₂₄ , 23 ₃₃ have the _multiplicand
However, hereinafter, basic cells 23 ₁ to 23 ₆ , 2
3 ₁₀ ~ 223 ₁₅ , 23 ₁₉ ~ 23 ₂₄ and 23 ₂₈ ~ 2
₃₃₃ are supplied with multiplicands X ₃ to X ₇ , respectively.
Here, the multiplicand input from the right side of each basic cell corresponds to 2X in FIG. 2, and the multiplicand input from the left side corresponds to X. In addition, the basic cell 23 ₁ ,
23 ₁₀ , 23 ₁₉ and 23 ₂₈ have multiplicands X and 2X
The multiplicand X ₇ is supplied as 23 ₉ , 23 ₁₈ , 2
The ground potential V _SS is supplied as 2X of 3 ₂₇ and 23 ₃₆ . On the other hand, each of the multipliers Y ₀ to _{Y 7} has 3 bits equal to 1
The signals are supplied as a set to decoders 28 ₁ to 28 ₄ . That is, the decoder 28 ₁ receives the multipliers Y ₀ , Y ₁ and the ground potential VSS, and the decoder 28 ₂ receives the multipliers Y ₁ , Y ₂ , Y _{3 .}
However, the decoder 28 ₃ is supplied with multipliers Y ₃ , Y ₄ , and Y ₅ , and the decoder 28 ₄ is supplied with multipliers Y ₅ , Y ₆ , and Y _{7 ,} respectively. The control signals (X select signal SELX, 2X select signal SEL2X, and inverted signal NEGA) output from the decoder ₂₈₁ are as follows:
It is supplied to basic cells 23 ₁ to 23 ₉ and decoder 28
The control signals output from each basic cell ₂
3 ₁₀ to 23 ₁₈ , the control signals output from the decoder 28 ₃ are supplied to the basic cells 23 ₁₉ to 23 ₂₇ , respectively, and the control signals output from the decoder 28 ₄ are supplied to the basic cells 23 ₂₈ to 23 ₃₆ , respectively. Further, the basic cells 23 ₂ to 23 ₁₀ , 23 ₁₂ to 23 ₁₉ , 23
The ground potential V _SS is supplied to ₂₁ , 23 ₂₂ , 23 ₂₈ , 23 ₃₀ and 23 ₃₁ as a sum input S _io and a carry input C _io , respectively. The basic cell ₂₃₁ functions as a code bit and is supplied with a ground potential V _SS and a power supply potential V _DD . Similarly, basic cell 2
The ground potential V _SS and the power supply potential V _DD are also supplied to 3 ₁₁ , 23 ₂₀ , and 23 ₂₉ . The above basic cells 23 ₁ to 23
The sum output of ₅ is supplied to basic cells 23 ₂₃ to 23 ₂₇ . The ground potential V _SS is supplied to the carry inputs of these basic cells 23 ₂₃ to 23 ₂₇ . The sum output obtained from the basic cells 23 ₆ to 23 ₉ is sent to a multi-input high-speed adder 29 for generating a carry signal.
is supplied to The sum outputs of the basic cells 23 ₁₀ to 23 ₁₄ are supplied to the basic cells 23 ₃₂ to 23 ₃₆ , respectively, and the outputs of the basic cells 23 ₁₅ to 23 ₁₈ are supplied to the multi-input high-speed adder 29, respectively. Further, the carry output and sum output of the basic cell 23 ₁₉ are supplied to adders 30 ₁ and 30 ₂ , respectively, and the carry output and sum output of the basic cell 23 ₂₀ are supplied to adders 30 ₂ and 30 ₃ , respectively. The carry output and sum output of ₂₁ are added to adders 30 ₃ and 30 ₄ respectively.
The carry output and sum output of basic cell 23 ₂₂ are supplied to adders 30 ₄ and 30 ₅ , and the carry output and sum output of basic cell 23 ₂₃ are supplied to adders 30 ₅ and 30 ₆ , respectively. The carry outputs of the basic cells _23-24 are supplied to the adders _30-6 , the sum outputs are supplied to the multi-input high-speed adder 29, and the carry outputs and sum outputs of the basic cells _23-27 are respectively supplied to the multi-input high-speed adder 29. 29. The sum output of the basic cells 23 ₂₈ is supplied to the adder 30 ₇ , and the sum output of the basic cells 23 ₂₉ to 23 ₃₄ is supplied to the adders 30 ₁ to 3.
0 ₆ and the carry outputs are supplied to adders 30 ₇ to 30 ₁₂ , respectively. Further, the carry output of the basic cell 23 ₃₅ is supplied to the adder 30 ₁₃ , the sum output is supplied to the multi-input high speed adder 29, and the sum output and carry output of the basic cell 23 ₃₆ are supplied to the multi-input high speed adder 29, respectively. Ru. The sum outputs of the adders 30 ₁ to 30 ₆ are supplied to the adders 30 ₈ to 30 ₁₃ , and the carry outputs are supplied to the adders 30 ₇ to 30 ₁₂ , respectively. The sum output and carry output of the adders 30 ₇ to 30 ₁₃ are, for example, CLA (Carry
Look Ahead), etc., and is supplied to a high-speed adder 31 for determining the final sum. Further, the carry output of the multi-input high-speed adder 29 is transmitted to the adder 30.
₁₃ and the high-speed adder 31, respectively.
Then, the multiplication output Z ₀ ~ from the multi-input high-speed adder 29
Z ₇ and multiplication outputs Z ₈ to _{Z 14} are obtained from the high-speed adder 31, respectively. Next, the operation in the above configuration will be explained. The multiplicands X ₀ to X ₇ are supplied to each basic cell 23 ₁ to 23 ₃₆ , and the multipliers Y ₀ to _{Y 7} are supplied to the decoder 2.
8 ₁ to 28 ₄ , these decoders 28
₁ to ₂₈₄ decode the 3-bit multiplier data, and the corresponding control signals (X select signal SELX, 2X select signal SEL2X, inverted signal NEGA) are supplied to each basic cell ₂₃₁ to ₂₃₃₆ . 0, ±X, ±2X are selected. As a result, partial products of the multiplicands X ₀ to X ₇ and the multipliers Y ₀ to _{Y 7} are generated. These partial products are added for each odd-numbered stage and even-numbered stage, and are added to the basic cells 23 ₆ to 23
₉ , 23 ₁₅ ~ 23 ₁₈ , 23 ₂₄ ~ 23 ₂₇ , 23 ₃₅ , 2
At least one of the sum output and the carry output of ₃₃₆ is selectively supplied to a multi-input high speed adder 29.
At least one of the sum output and carry output of the basic cells 23 ₁₉ to 23 ₂₄ and 23 ₂₈ to 23 ₃₅ is selectively supplied to adders 30 ₁ to 30 ₁₃ , respectively;
The sums of the partial products of the odd and even stages are finally added. Then, the sum output and carry output of these adders 30 ₇ to 30 ₁₃ are added by a high-speed adder 31. Here, when the input of the high-speed adder 31 (the output of the adders 30 ₇ to 30 ₁₃ ) is determined, the carry signal from the lower adder must also be determined. Therefore, on the lower side, instead of increasing the number of cell stages and narrowing down the sum output and carry output to two, there are multiple inputs that generate a carry signal from the sum output and carry output output from the two systems of cells. A high-speed adder 29 is used to determine the carry to the higher order while passing through all the basic cells. According to such a configuration, the number of stages of passing cells can be reduced as shown in the table below, thereby increasing the speed. Furthermore, since it is a parallel type, regularity in pattern configuration can be maintained, making it suitable for LSI implementation.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a multiplier that is capable of high-speed operation, has a regular pattern suitable for LSI implementation, and can be highly integrated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiplier according to an embodiment of the present invention, FIG. 2 is a block diagram of the basic cell in FIG. 1, FIG. 3 is a basic block diagram of a conventional parallel multiplier, and FIG. This figure is a block diagram of a parallel multiplier constructed using the basic cell shown in FIG. 3, and FIG. 5 is a diagram for explaining a method of reducing the number of stages of addition of partial products. X ₀ ~ X ₇ ... Multiplicand, Y ₀ ~ _{Y 7} ... Multiplier, 23 ₁
~23 ₃₆ ...Basic cell, _2281-284 ...Decoder, ₂₉ ...Multi-input high-speed adder, _301-30
13 ... Adder, 31... High speed adder, Z ₀ ~ Z ₁₄ ...
...Multiply output, SELX...X select signal, SEL2
X...2X select signal, NEGA...inverted signal,
24...Full adder, 25...Exclusive NOR gate,
26...Noah gate, 27 ₁ , 27 ₂ ...And gate, S _io ...Sum input, C _io ...Carry input, S _put
... Sum output, C _put ... Carry output.

Claims (1)

[Claims] 1. A generating means for generating a selection signal from a multiplier of at least 3 bits; a basic cell for selecting a multiplicand and adding partial products according to the selection signal output from the generating means; A matrix-like calculation means in which cells are arranged in a matrix and the same digits of the obtained partial products are added separately in even and odd stages, and a plurality of partial products outputted from this matrix-like calculation means. A multiplier comprising: an adding means for adding and outputting sums; and a multiplier. 2. The basic cell includes a first AND gate to which a multiplicand and a selection signal of this multiplicand are supplied, and a second AND gate to which a signal obtained by doubling the multiplicand and a selection signal of this doubled signal, a NOR gate to which the outputs of the first and second AND gates are supplied, and an exclusive NOR gate to which the outputs and inverted signals of the NOR gate are supplied;
2. The multiplier according to claim 1, further comprising a full adder for obtaining a sum output and a carry output to which the output of the exclusive NOR gate, the sum signal, and the carry signal are supplied.