JPS60112141A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To obtain a multiplier circuit which can meet a multiplier input of short word length at high speed and a multiplier input of long word length at a low speed by providing the multiplier circuit in accordance with the multiplier input word length and the mutiplicand input word length which are supplied. CONSTITUTION:Eight bit multiplicands x0-x7 are divided into multiplicand groups X1(x0-x3) and X2(x4-x7) of every four bits and supplied to a selector 30. Eight bit multipliers y0-y7 are divided into multiplier groups Y1(y0-y3) and Y2(y4-y7), and supplied to a selector 31. A partial product X1.Y2 is formed by the 1st select signal, by the 2nd select signal a partial product X2.Y1 is formed and an action of four-bit shifting in the right direction is executed, by the 3rd select signal, a partial product X1.Y2 is formed, and by the 4th select signal a partial product X2.Y2 is formed and an action of four-bit shifting in the right direction is executed. As a result, multiplier outputs z0-z15 of 16 bits can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a multiplication circuit applied to processing digital video signals, digital audio signals, and the like.

[Background technology and its problems] For example, a multiplication circuit used for digital video signals is
Although a very high speed is required, the data word length is usually about 8 bits, and the input word length of the multiplier circuit does not need to be a long word length. However, for example, multiplier circuits used for digital audio signals do not require high speed, but multiplier circuits used for video signals do not require high speed, but the word length of the data is 16 to 24 pits, so the input word length of the multiplier circuit is must be long word length.

Conventionally, multiplier circuits have been constructed using parallel multiplier circuits, serial multiplier circuits, ALUs, circuits based on division multiplexing, and ROM.

However, except for methods that are theoretically versatile in terms of word length and speed, such as circuits based on time-division multiplexing using ALUs, multiplication circuits for video signals are used only for video signals, and are used only for audio signals. The multiplier circuit used for this was used only for audio signals, and had the disadvantage of not being versatile. Conventionally, multiplication circuits for video signals and audio signals require high speed, so
The parallel multiplier circuit shown in the figure was used.

In FIG. 1, 1 and 2 indicate registers, and register 1
4-bit multiplicand X (X = XO+, Xl +
X2+X3) is supplied, and register 2 is supplied with a 4-bit multiplier Y (Y-Yo+YI+Y2+y3). Multiplicand X output to register '1. -X3 and the multiplier y output to register 2. ~y3 is supplied to the parallel multiplication arithmetic circuit 3 shown surrounded by a broken line.

The parallel multiplication arithmetic circuit 3 includes an AND gate 9 shown in FIG.
and unit circuits 4A to 4D configured by the full adder 10
, 5A to 5D, 6A to 6D, and 7A to 7D are arranged in a two-dimensional array, and each unit circuit has a bit input terminal 11.12, an addition input terminal 13, an addition output terminal 14,
It has a carry input terminal 15 and a carry output terminal 16.

The multiplicand X (X-xQ, X1r X21 X3) is supplied to the parallel multiplication operation circuit 3 from register 1.
The least significant bit X in . are unit circuits 4A, 5A, 6A
, 7A, and beep)x□ is the unit circuit 4B.

5B, 6B, 7B, bit X2 is supplied to unit circuits 4C, 5C, 6C, 7C, most significant bit
is the unit circuit 4 I), 5D, 6D, 7D
supplied to

The multiplier Y (Y-yO+ 3'l + y2 + V3) supplied from the register 2 to the parallel multiplication arithmetic circuit 3
The lowest human in y. Unit circuit 4A, 4B, 4C
, 4D, and the pin l-y□ is supplied to the unit circuits 5A, 5B.
, 5C25D, and bit y is supplied to the unit circuit 6A.

6f3,6. The most significant bit y3 is supplied to unit circuits 7A, 7B, '7C, and 7D.

Unit circuits 4A, 5A, and 6A at the right end of each row arranged in the horizontal direction
, 7A Ω carry outputs are unit circuits 4B, 5, respectively.
The carry outputs of unit circuits 4B, 5B, 6B, and 7B are supplied to unit circuits 4C, 5C, 6C, and 7C, respectively. The respective carry outputs of unit circuit 7C are supplied to unit circuits 4D, 5D, 6D, and 7D, respectively, the carry output of unit circuit 4D is used as the addition input of unit circuit 5D, and the carry output of unit circuit 5D is supplied to unit circuit 6D. The carry of unit circuit 6D is applied to the addition input of unit circuit 7D.

The addition output output from each unit circuit is used as the addition input of each unit circuit arranged in the vertical direction, and is applied to the lower end unit circuits 4A, 5A, 6A, 7A, 7B in each vertical column.
, 7C, γD and the carry of the unit circuit γD are supplied to a register 8, which produces an 8-bit multiplication output S. +s
l, s2. s3. ...s7 is taken out from register 8.

The above-mentioned parallel multiplication circuit realizes the operation shown in FIG. In other words, the multiplicand X'(X=x(,.

XI + X2 + X3) and multiplier Y (” =yo+ y
t + yz + ys'j"IsI, unit circuit 4
In A to 4D, the partial product X of the multiplicand X and the LSB Vo of the multiplier
” yo is determined, unit circuits 5A to 5D determine the partial product Xa y of multiplicand X and multiplier bit y1, and unit circuits 68 to 6D determine the partial product X−y2 of multiplicand X and multiplier bit y2. and the multiplicand 'X in unit circuits 7A to 7D
The partial products X-y3 of and bit y3 of the multiplier are determined, and these partial products are shifted one bit at a time and added.

The operating limit of this parallel multiplication circuit is the multiplicand L
The carry output to the unit circuit 4A into which the SB xo and the LSB yo of the multiplier are input is determined by the time it takes for the carry to influence the unit circuit 7D and determine its value. Finally, this operating limit is generally approximately proportional to the number of bits B, where B is the number of bits of the multiplicand and multiplier. Further, the gate scale can be considered as the number of full adders required, which is 82, which is the square of the number of bits B. follow-
Therefore, when the multiplicand input word length and multiplier input word length are 12 bits, 144 full adders are required, and when the multiplicand input word length and multiplier input word length are 24 bits, 576 full adders are required. However, there was a problem in that the gate size became large.

``Object of the Invention'' It is an object of the present invention to provide a multiplication circuit that can handle both high-speed, short-word multiplication inputs and slow-speed, long-word multiplication inputs by improving the waste of gates.

Another object of the present invention is to provide a multiplication circuit that can also operate as a multiplier.

"Summary of the Invention" This invention includes a parallel multiplier circuit that multiplies a multiplicand input and a multiplier input, and an input signal that is input as a multiplicand input according to the word length of the multiplicand of the parallel multiplier circuit. A selector that selects one of the multiplier inputs according to the multiplier word length of the parallel multiplication circuit, a selector that divides the input signal input as the multiplier input into multiple groups and selects one of the groups, and a selector that selects one of the groups, The multiplication circuit includes a shift circuit that supplies one input power as the other input of the arithmetic circuit.

"Example" An embodiment of the invention will be described with reference to the drawings.

In FIG. 4, 20 and 21 indicate selectors, and a multiplicand X of M bits. , xl, x2. x3. ...xt
-1 is supplied to the selector 20, an N-bit multiplier y. ,
yyo+y2+y3...Yn-1 is supplied to the selector 21.

Reference numeral 22 indicates a parallel multiplication arithmetic circuit, and the parallel multiplication arithmetic circuit 22 is configured similarly to the parallel multiplication arithmetic circuit 3 shown in FIG. The length is L bits.

The multiplicand Xo-Xm-□ supplied to the selector 20 is divided into P multiplicand groups 7'Xt-Xp each having bits equal to the multiplicand input word length of the parallel multiplication arithmetic circuit 22,
One of the multiplicand groups is selected by a select signal synchronized with the clock supplied to the selector 20 and supplied to the parallel multiplication arithmetic circuit 22 . Multiplier y supplied to selector 21. -yn-1 is equal to the multiplier input word length of the parallel multiplication arithmetic circuit 22.Q multiplier groups Y of L bits each
One of the multiplier groups is selected by a select signal synchronized with the clock supplied to the selector 21 and supplied to the parallel multiplication arithmetic circuit 22 .

The parallel multiplication arithmetic circuit 22 multiplies the multiplicand group selected by the selector 20 and the multiplier group selected by the selector 21, and the husband's partial products are supplied to the addition circuit 23.

The adder circuit 23 is composed of a plurality of full adders, and O data 24 is supplied to a predetermined number of lower bits of the adder circuit 23, and the output of the parallel multiplication arithmetic circuit 22 is supplied as its upper bits. . On the other hand, the output of the selector 27 is supplied to the adder circuit 23, and the partial product determined by the parallel multiplication arithmetic circuit 22 and the output of the selector 27 are added together by the adder circuit 23.

The output of the adder circuit 23 is supplied to a register 25, and the output of the register 25 is supplied to a shift circuit 26 and a selector 2γ. The shift circuit 26 shifts the bits of the partial product output to the register 25. Shift circuit 2
6 is supplied to the selector 21.

The selector 27 selects the output to be supplied to the adder circuit 24, and the selector 21 has the output of the shift circuit 26,
The output of the register 25 and all O data supplied from the terminal 28 are supplied, and these three outputs are selected by a select signal synchronized with the clock supplied to the selector 27 and output.

For the partial products determined by the parallel multiplication arithmetic circuit 22 and supplied to the addition circuit 23, the output of the selector 27 selects O data for the first partial product determined;
It is determined whether or not to perform a bit shift on the partial product data that will be found thereafter, depending on the requested partial product, and if a bit shift is to be performed, the shift circuit 26
The output of the register 25 is selected, and if no bit shifting is performed, the output of the register 25 is selected.

In this way, the partial products of the multiplicand group and the multiplier group, which are requested by the parallel multiplication arithmetic circuit 22 and sequentially output, are shifted by the shift circuit 26 as necessary and accumulated, thereby performing the multiplication. An output is output from register 25.

FIG. 5 shows an implementation in which the multiplicand input word length and multiplier input word length of the parallel multiplication arithmetic circuit are 4 bits, and the supplied multiplicand input word length and multiplier input word length are 8 bits. Give an example.

In FIG. 5, 30 and 31 indicate selectors. 8-bit multiplicand x01 xl + X2 + X3'''
X7 is a multiplicand group of 4 bits each, X, , X, ,
(X, = xo, x, .

X2+ X3+ X2= X4+ x5* X6+ x
7) and supplied to the selector 30. 8-bit multiplier y. ,yl.

Y2 + Y3 +-・yl is multiplier group y of 4 bits each, +Y2 (Yl-Yo+ Y++ Y2T Y3
Yz=y4+3'5+3'6+yl) and supplied to the selector 31. A select signal synchronized with the clock is supplied to the selectors 30 and 31, and the multiplicand groups XI, X2 and the multiplier groups Y1, Y2 are selected by the select signal. When the first select signal is supplied to the selectors 30 and 31, multiplicand group X1 and multiplier group is selected, and when the third select signal is supplied to the selectors 30 and 31, the multiplicand group X1 and the multiplier group Y2 are selected, and when the fourth select signal is supplied to the selectors 30 and 31, the multiplicand group X2 and the multiplier group Group Y2 is selected, and the selected multiplicand group and multiplier group are supplied to the parallel multiplication arithmetic circuit 32.

The parallel multiplication arithmetic circuit 32 is constructed similarly to the parallel multiplication arithmetic circuit shown in FIG. 1, and has a multiplicand input word length and a multiplier input word length of 4 bits.

The multiplicand group and multiplier group selected by the selectors 30 and 31 are supplied to the parallel multiplication arithmetic circuit 32, whereby partial products X1. Y1 Partial product X2・YI of multiplicand group X2 and multiplier group Y1, Partial product of multiplicand group X1 and multiplier group Y2, fft
is determined by the parallel multiplication arithmetic circuit 32.

The 8-bit partial products input to the parallel multiplication arithmetic circuit 32 are full adders 33, 34, 35, 36.

The data supplied to 37.38.39' and 40 and converted to 0 data by being grounded is sent to the full adder 41.42.
, 43, 44, 45, 46, 47°48.

50 indicates a selector, and the selector 50 contains data in which all 16-bit data is set to 0 by being grounded, and the output of the 16-bit register 51, and 0 by grounding the second-order 4 bits. By making the lower 12 bits the upper 12 bits of the register 51, the output of the register 51 is shifted to the right by 4 bits, and one of these three pieces of data is synchronized with the clock supplied to the selector 50. It is selected by a select signal and supplied to full adders 33-48.

The full adders 33 to 48 add the 16-bit data in which the upper 8 bits I. are the output of the parallel multiplication arithmetic circuit 32 and the lower 8 bits are O, and the output data selected by the selector 50. , this addition output is in register 5
1.

When the first select signal is supplied, the parallel multiplication arithmetic circuit 32 outputs the partial product X1·Y□ of the multiplicand group XI and the multiplier group Y1, and this output is sent to the full adder 3
3 to 40, and full adders 41 to 48 are grounded to supply zero data. On the other hand, selector 50
selects data with all 16 bits set to 0,
It is supplied to full adders 33-48. Therefore, the data of the partial product x1·Yl is output to the full adders 33 to 40,
00 data is output to the full adders 41 to 48, and the outputs of these full adders 33 to 48 are supplied to the register 51.

A 16-bit output is taken out to the register 51, and this 16-bit data is supplied as is to the selector 50, and the upper 4 bits are grounded to become 0 data, and the lower 12 bits are output from the upper register 51. By setting it to 12 bits, the output of the register 51 is shifted to the right by 4 bits and is supplied to the selector 50.

When the second select signal is supplied to the selectors 30 and 31, the parallel multiplication operation circuit 32
The partial product X2・Yl of and multiplier group Y1 is output,
This output is supplied to full adders 33-40, and 0 data is supplied to full adders 41-48. At the same time, data obtained by shifting the partial product X1.Yl by 4 bits to the right is selected by the selector 50 and supplied to the full adders 33-48. The outputs of full adders 33 to 48 are in register 5.
1, and the output of the register 51 is supplied to the it selector 50 thereof, and is also shifted to the right by 4 bits and supplied to the selector 50.

When the third select signal is supplied to the selectors 30 and 31, the parallel multiplication operation circuit 32
The partial product X1・Y2 of and multiplier group Y2 is output,
This output is supplied to full adders 33-40, and O data is supplied to full adders 41-48. At the same time, the output of the register 51 is selected by the selector 50 and supplied to the full adders 33-48. Therefore full adder 33
48, the accumulated outputs of partial products X2.Yl, X1.Y2, and partial products X1.Yl shifted by 4 bits to the right are obtained. The outputs of the true adders 33 to 48 are supplied to a register 51, and the output of the register 51 is supplied as is to a selector 50, and is also shifted to the right by 4 bits and supplied to the selector 50.

When the fourth select signal is supplied to the selectors 30 and 31, the parallel multiplication operation circuit 32
The partial product X2・Y2 of and multiplier group Y2 is output,
This output is supplied to full adders 33-40, and 0 data is supplied to full adders 41-48. Along with this,
The output of register 51 shifted to the right by 4 bits is selected by selector 50 and supplied to full adders 33-48. The outputs of the full adders 33 to 48 are supplied to the register 51, and the multiplication outputs 2°, z, z2.
...zI5 is taken out.

In this multiplication circuit, when the multiplicand input word length and the multiplier input word length are 4 bits, for example, the parallel multiplication operation circuit 3
2 shows the 16-bit calculation output. in this case,
The selector 50 is configured to always select data of 0.

Also, when the multiplicand input word length and multiplier input word length are 8 bits and 4 bits, or when the multiplicand input word length and multiplier input word length are 4 bits and 8 bits, the selector 30. The selector 50 shifts the bits of the partial products selected and sequentially stored in the parallel multiplication calculation circuit 32 and accumulates them, so that the multiplication output is stored in the register 51.

The operation of the embodiment of the present invention described above will be summarized with reference to FIG. The partial product X1 is selected by the first select signal.
・Yl is formed, and the partial product
The operation of forming ♀・Y, 1 and shifting 4 bits to the right is performed, and the third select signal forms the digital partial product X1・Y2, and the fourth select signal generates the digital partial product X2・Y.
The operation of forming 2 and shifting 4 bits to the right is performed. Then, a 16-bit multiplication output zo~2□5 is obtained.

FIG. 7 shows another embodiment of the present invention which also operates as a product-sum circuit.

As shown in FIG. 8, in the product-sum circuit, the multiplicand X and the multiplier Y are supplied to a multiplication circuit 52, the multiplication output of the multiplication circuit 52 and an external output P are supplied to an addition circuit 53, and the addition output is taken out from the register 54, and is used, for example, when constructing a digital filter.

In FIG. 7, a parallel multiplication arithmetic circuit 22 and an addition circuit 2
3, and the selector 55 is supplied with the output of the parallel multiplication arithmetic circuit 22 whose lower bit is set to 0, and the input P from the outside. After forming the multiplication output of the multiplicand X and the multiplier Y in the same manner as in the above embodiment,
When the input P from the outside is selected by the selector 55, the sum of the multiplication output and the input P from the outside is formed.

Further, the present invention can be used as a multiplication circuit with an accumulation circuit shown in FIG.

As shown in FIG. 9, the multiplier circuit with an accumulation circuit has a multiplier circuit 52, an adder circuit 53 to which the multiplication output is supplied, and a register 54 to which the output of the adder circuit 53 is supplied. This configuration is such that the other is fed back to the adding circuit 53.

Therefore, by storing the multiplication output based on the present invention, a multiplication circuit with an accumulation circuit can be constructed.

"Application Example" The present invention can be applied not only to natural binary codes but also to multiplication of 2's complementary codes. In this case, the adder circuit is configured as an ALU, and the ALU performs subtraction at the clock when the highest group among the groups of multiplier Y is selected, and the ALU performs addition at other clocks. Ru.

"Effects of the Invention" According to the present invention, the multiplication of a word length of M bits) is divided into the multiplication of XL bits of a short word length. Without completing the multiplication, efficient gate operations can be performed. Further, it is possible to realize a multiplication circuit that can handle both high-speed multiplication input with short word length and low-speed multiplication input with long word length.

[Brief explanation of the drawing]

Figures 1, 2, and 3 are connection diagrams of a conventional parallel multiplier circuit and a part thereof, and a route diagram used to explain its operation.
FIG. 4 is a block diagram of an embodiment of this invention, FIG. 5 is a more detailed block diagram of an embodiment of this invention, FIG. 6 is a route map used to explain the operation of an embodiment of this invention, and FIG. 7 and 8 are block diagrams of other embodiments of the present invention and block diagrams used for explaining the same, and FIG. 9 is a block diagram used for explaining still another embodiment of the present invention. 20.21.27, 30.31.50.55...Selector, 22.32...Parallel multiplication arithmetic circuit, 26...Shift circuit. Agent Tadashi Sugiura Figure 3 x-■ Figure 6 Figure 8 Figure 9

Claims (1)

[Claims] a parallel multiplier circuit that multiplies a multiplicand input and a multiplier input; and a selector that divides an input signal input as a multiplicand input into a plurality of groups according to the word length of the multiplicand of the parallel multiplier circuit, and selects one of the groups. , a selector that divides an input signal input as a multiplier input into a plurality of groups according to the multiplier word length of the parallel multiplier circuit, and selects one of the groups, and a multiplier output of the parallel multiplier circuit that selects one of the inputs. and a shift circuit that supplies the other input to the arithmetic circuit.