JPS6289135A - Digital fixed point multiplier - Google Patents

Abstract

PURPOSE:To decrease the scale of the hardware of a multiplying circuit by using a multiplicand higher order register, a multiplicand lower order register, an input selector, a multiplying circuit, an output selector and an adding means, and executing one multiplication by dividing it into two times. CONSTITUTION:The multiplier register 8 of the 8-bit constitution of MSB 9 - LSB 10 is provided, and the multiplier register 8 is connected to an 8 bit X8 bit multiplying circuit 11. The multiplicand register is composed of two registers, and one side is the multiplicand higher order register 1 of the 8 bit constitution of MSB 5 - LSB 6, and other side is a multiplicand lower order register 4 of the 8 bit constitution of MSB 5 - LSB 6. The lower order register 4 is constituted so that the higher order 1 bit of MSB outputs always '0'. The higher order register 1 and the lower order register 4 are connected to the input selector 7 to select the register, and the input selector 7 is connected to a multiplying circuit 11. To the multiplying circuit 11, the output register 12 of the 16 bit constitution of MSB 13 - LSB 14 is connected, and the output register 12 is connected to an output selector 15.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to digital circuits, and more particularly to digital fixed-point multipliers.

[Conventional technology]

Conventionally, this type of digital fixed-point multiplier has been constructed of a digital multiplication circuit having input/output of the required number of bits. FIG. 2 shows a block diagram of this conventional circuit.

This digital fixed-point multiplier uses the most significant bit (M
SB) A multiplier register 31 consisting of 8 bits from 31 to least significant bit (LSB) 32, and 1 from MSB 34 to LSB 35.
Multiplicand register 33 with 5-bit configuration and 8-bit x 15
Bit multiplication circuit 36, MSB 38 to LSB 39 (
7) A product register 37 having a 23-bit configuration.

In such a digital fixed-point multiplier, y=aXx
Let us consider the case of performing the multiplication (1). An 8-bit fixed-point multiplier a is input to the multiplier register 3o, and a 15-bit fixed-point multiplicand X is input to the multiplicand register 33. The multiplication circuit 36 calculates the numerical value in the multiplier register 30 and the numerical value in the multiplicand register 33, and calculates the product of 8+15 bits of the fixed point number into the product register 37.
Output to.

[Problem that the invention seeks to solve]

In the above-mentioned conventional digital fixed-point multiplier, when performing multiplication of an n-bit multiplier and an m-bit multiplicand, generally a multiplication circuit with n-bit and m-bit inputs and n+m-bit output is required. Therefore, there is a drawback that the scale of the hardware becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital fixed-point multiplier that overcomes these drawbacks.

[Means for solving problems]

The digital fixed-point multiplier of the present invention includes a multiplier register that stores a multiplier, a multiplicand upper register that stores the upper bits of the multiplicand, a lower multiplicand register that stores the lower bits of the multiplicand, and the multiplicand upper register and the multiplicand. an input selector for selecting a lower register; a multiplication circuit for multiplying the multiplier by the lower or upper bit of the multiplicand; an output selector for selecting an output of the multiplication result to the addition means described later; and an addition means for obtaining a multiplication result equivalent to the product of the multiplier and the multiplicand from the multiplication result of the multiplication performed twice on the bits.

〔Example〕

Next, examples of the present invention will be described.

FIG. 1 is a block diagram of a digital fixed-point multiplier that is an embodiment of the present invention. This digital fixed-point multiplier is equipped with a multiplier register 8 consisting of 8 bits from MSB9 to LSB10.
It is connected to a bit×8 bit multiplication circuit 11. On the other hand, the multiplicand register is composed of two registers, one of which is the upper multiplicand register 1 consisting of 8 bits from MSB2 to LSB3, and the other is the 8-bit register from MSB5 to LSB6.
This is a multiplicand lower register 4 having a bit configuration.

Note that the lower register 4 is configured so that the upper 1 bit of the MSB always outputs "0".

The upper register 1 and the lower register 4 are connected to an input selector 7 that selects these registers, and the input selector 7 is connected to a multiplication circuit 11. The multiplication circuit 11 is connected to an output register 12 having a 16-bit configuration of MSB13 to LSB14, and this output register 12 is connected to an output selector 15.The output selector 15 has two sets of 16-bit output lines 16.
The upper 9 bits of the output line 16 are connected to the lower 9 bits of the 16-bit adder circuit 18, and the lower 7 bits of the output line 16 are MSB20 to LSB2.
The lower 7 bits of the product register 19 with 23 bits of 1/
connected to the On the other hand, the output line 17 is connected to an adder circuit 18, and the adder circuit 18 is connected to the upper 16 bits of the product register 19.

In the digital fixed-point multiplier with the above configuration, y=ax
Consider the case of performing multiplication of x (2). Here, the multiplier a is an 8-bit fixed point number,
The multiplicand X is a 15-bit fixed-point numeric value in two's complement format. The multiplicand X is divided into upper 8 bits and lower 7 bits, and each is expressed as Xh+XI2. Furthermore, if a binary number is expressed by adding b to the end of the number, the multiplicand X is expressed as follows.

x=xhX100QQOOOOb+x! ! (3)(
Substituting equation 3) into equation (2), y=axx = a × (xh xtooooooob + xl
) = a X xhXlooooooob + a X
x, 2 (4).

To execute this multiplication, first, the multiplier a is input into the multiplier register 8, the upper 8 bits xh of the multiplicand X are input into the upper multiplicand register 1, and the lower 7 bits xl are input into the lower multiplicand register 4. The input selector 7 first selects the multiplicand lower register 4 as the multiplicand input of the multiplication circuit 11, and performs multiplication of a×XI in the second term on the right side of equation (4). XI is a fixed decimal point
Since the lower 7 bits are extracted from , all must be treated as positive numbers. Therefore, the sign bit O, which is a positive sign, is inserted in the lower register 4 as described above.

The multiplication result of aXXp in the multiplication circuit 1 is sent from the output register 12 by the output selector 15, and the lower 7 bits are sent to the lower bit part of the product register I9 via the output line 16.
The upper bits are also sent to the adder circuit 18 via the output line 16.
is input to the lower bit part of. When the multiplication of the lower multiplicand is completed, the input selector 7 next selects the upper multiplicand register 1 as the multiplicand input of the multiplication circuit 11, and multiplies by aXxh in the first term on the right side of equation (4). The multiplication result is input from the output register 12 to the adder circuit 18 via the output line 17 by the output selector 15. At this time, the multiplication result of aXXh is multiplied by 10000000b and is sent to the adder circuit 18.
is input. In the adder circuit 18, it is added to the upper 9 bits of aXx6 that have already been input by the previous multiplication,
The addition result is input to the upper bit part of the product register 19. Therefore, the product register 19 contains a x xhxlOOOOOOOOb + a
is obtained, and a multiplication result equivalent to an 8-bit x 15-bit multiplication circuit is obtained.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and it goes without saying that various modifications and changes can be made within the scope of the present invention.

〔Effect of the invention〕

As explained above, the present invention uses the multiplicand upper register, the multiplicand lower register, the input selector 1 multiplication circuit, the output selector, and the addition means, and performs one multiplication twice, thereby reducing the hardware of the multiplication circuit. It becomes possible to reduce the scale to about 1/2.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional circuit. 1... Multiplicand upper register 2.5.9... MSB (Most significant bit) 3.6.1O
-LSB (least significant bit) 4... Multiplicand lower register 7... Input selector 8.30... Multiplier register 11... 8 bits x 8 pinto multiplier circuit 12...・
... Output register 15 ... Output selector 16.17 ... Output line 18 ... Addition circuit 19.37 ... Product register 33 ... Multiplicand register

Claims (2)

[Claims] (1) Input for selecting a multiplier register that stores a multiplier, a multiplicand upper register that stores the upper bits of the multiplicand, a lower multiplicand register that stores the lower bits of the multiplicand, and the multiplicand upper register and multiplicand lower register. a selector, a multiplication circuit that multiplies the multiplier by the lower or upper bits of the multiplicand, an output selector that selects the output of the multiplication result to the addition means described later, and the lower and upper bits of the multiplicand. A digital fixed-point multiplier comprising: an addition means for obtaining a multiplication result equivalent to the product of the multiplier and the multiplicand from the multiplication result of the multiplication performed. (2) The digital fixed-point multiplier according to claim 1, wherein the adding means comprises an adding circuit and a register.