JP3106767B2 - Multiplication method and multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication method and a multiplication circuit used for, for example, digital signal processing.

[0002]

2. Description of the Related Art Conventionally, there has been a method in which a multiplier is coded according to a Booth algorithm, a partial product is generated from a multiplicand using the code signal, and the partial product is added using a Wallace Tree or the like to perform multiplication. .

There is also a method of using a ROM when multiplying the multiplier P and the multiplicand Q. According to this method, if the bit length of data is M bits, the required capacity of the ROM is ^{22 M} words. There is a method of halving the number of words by utilizing the interchangeability of multiplication, but the number of words becomes very large as M increases. Therefore, by dividing the multiplier factor P and the multiplicand Q for each N bits each, to generate a partial product using the ROM address 2N bits, the data number 2 ^2N,
There has also been a method of performing multiplication by shifting and adding them.

[0004]

However, the multiplier P
In the method of coding only the data according to the Booth algorithm, if the bit length of the data becomes longer, the number of the partial products increases, so that there is a problem that the circuit scale of the portion to which the partial products are added tends to be large.

In the latter method using a ROM, when the input data is a number expressed in 2's complement, the operation on the most significant N bits and the operation on the other N bits are performed by using the sign code. Since the meaning is different depending on whether or not the operation is performed, there is a problem that different types of ROMs need to be prepared.

The present invention eliminates the above problems and encodes the multiplier and the multiplicand using a higher-order Booth algorithm, so that multiplication can be performed without increasing the circuit scale even if the data bit length is increased. It is an object to provide a possible multiplication method.

[0007]

SUMMARY OF THE INVENTION According to the present invention, there are provided a multiplier, a multiplicand.
Both code signals according to the higher order Booth algorithm
Means for generating a partial product using the code signal.
Means that includes means for adding said partial products, said code
The means for converting to a signal is a code that encodes the multiplier and the multiplicand.
Each code signal consists of absolute value and sign part
And the means for generating the partial product comprises:
From the absolute value of the code signal of the absolute value and the multiplicand
The means for generating a partial product and adding the partial product includes a multiplier and a multiplier.
When the sign representing the sign of the code signal of the multiplicand is the same sign
Adds the partial product of the absolute value part,
Is performed .

Also, a code encoding a multiplier and a multiplicand
When the MSB of the absolute value part of the signal is "1" (maximum value
), The partial product is generated by a shift operation.
It is characterized by .

[0009]

According to the present invention, both the multiplier P and the multiplicand Q are coded by using a higher-order Booth algorithm, so that multiplication is performed without increasing the circuit size even if the bit length increases. A multiplication circuit can be configured.

When a partial product is generated, coding is performed using a higher-order Booth algorithm.
There is no problem that the operation on the N bits including the most significant bit and the operation on the other parts generated by the method using the ROM are different from each other, and the operation can be performed using the same circuit.

Further, by taking one bit representing a code from the code signal and performing a process related thereto by means for adding a partial product, the code signal can be represented by an M-bit signal line, The size of the circuit for calculating the partial product can be reduced.

Further, MS of the M bits of the code signal
B is used only in ^one case of 2 ^M−1 , and by realizing the process related to the power of 2 by the shift operation, the scale of the circuit for calculating the partial product can be suppressed.

[0013]

Next, the multiplication method according to the present invention will be described with reference to the case of 8 bits.

An 8-bit two's complement multiplier P,
When the multiplicand Q is represented by a power of two, it becomes (Equation 1).

[0015]

(Equation 1)

However, p _i , q _j (0 ≦ i, j ≦ 7) takes a value of 1 or 0. If P and Q are expressed using the fourth-order Booth method (corresponding to M = 4), the following equation (2) is obtained.

[0017]

(Equation 2)

However, -8 ≦ X _i and Y _j ≦ 8. −8 ≦
In order to represent the number of X _i , Y _j ≦ 8, if it is represented by a sign bit + an absolute value, it can be represented by M + 1 = 5 bits. By using X ₁ , X ₀ , Y ₁ , and Y ₀ , P × Q can be expressed by (Equation 3).

[0019]

(Equation 3)

That is, X ₁ Y ₁ , X ₀ Y ₁ , X ₁ Y ₀ , X ₀ Y ₀
, And shift and add. The above four partial products can be obtained as follows.

[0021] X _i, and outputs the absolute value the values of X _i Y _j from its combination as an input signal of 8 bits together portions of 4 bits each indicating the Y _j. This combination is 0
Except for the case, there are 64 (= 8 × 8) patterns. When either X _i or Y _j is 0, the partial product is “0”.

The number of combinations required to generate a partial product is
It can be reduced as follows. That is, of the 4-bit portion indicating the absolute value, the MSB is 1 only when the absolute value is 8.
Becomes Therefore, before generating the partial product, attention is paid to the MSB of the 4-bit portion representing the absolute value of each of X _i and Y _j . If this MSB is not 1, the 3-bit portion excluding the MSB is partially Input to the product generation circuit to generate a partial product.

On the other hand, when the MSB is 1, the MSB
Is set to "001" (that is, 1 bit).
/ 8) and input to the partial product generation circuit.

The partial product generated as a result of the above operation is represented by 0 bits (corresponding to 1) when both MSBs are 0, and 3 bits (corresponding to 8 times) when one of the MSBs is 1. If both MSBs are 1, then a 6-bit (corresponding to 64 times) left shift (lower order by 0) can obtain a correct partial product. In this case, to generate a partial product, The number of required combinations can be 7 × 7 = 49.

[0025] Examples of the above operation, 4-bit MSB representing the absolute value of X _i is 1 (absolute value of X _i = 8), 4-bit MSB representing the absolute value of Y _j is 1 If not, the partial product generation circuit performs an operation of “001” × “absolute value of Y _j ”. The result of this operation is
One-eighth of the original operation result. Since one of the MSB is 1, the left shift 3 bits for this calculation result is performed, it is possible to obtain a partial product, "the absolute value of X _i" × "the absolute value of Y _j".

Similarly, when both MSBs are 1, that is, when “absolute value of X _i ” × “absolute value of Y _j ” = 64, the input of the partial product generation circuit is “001”. , Its output becomes “1”. Since this output is shifted left by 6 bits, "1,000,000" = 64 is obtained. Also, the four sign bits are input to the partial product addition means,
Controls addition and subtraction of partial products.

The addition and subtraction of the partial product is performed according to (Equation 3). The partial product X _i Y _j is negative when the exclusive OR of the two sign bits is 1, so in that case, subtraction is performed, and when the exclusive OR is 0, the addition is performed. .

The processing relating to the power of 2 in (Equation 3) is performed by shifting left. That is, X ₁ Y ₁ is 8 bits, X ₁ Y ₀ , X ₀ Y ₁
Is 4 bits, and X ₀ Y ₀ is shifted left by 0 bits to perform addition and subtraction. As a result of the above addition and subtraction of the partial products, a product of P × Q can be obtained.

Next, an embodiment of an 8-bit × 8-bit multiplication circuit using the multiplication method of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration diagram of the circuit of this embodiment. The multiplier 1 and the multiplicand 2 are input to booth coding means 3 and 4, respectively. Code signals 5, 6 obtained by converting multiplier 1 into code signals
Of the four 5-bit signals of code signals 7 and 8 obtained by encoding the multiplicand 2 and the 4-bit portion representing the absolute value, the 4-bit portion is input to the partial product generation means 9 and the partial products 14 to 17 is output, and the output partial products 14-1
7 is input to the partial product addition means 18. Further, code bits 10 to 13 representing the codes of the code signals 5 to 8 are also input to the partial product adding means 18 to control addition and subtraction of the partial products 14 to 17. This addition / subtraction is performed by the partial product addition means 18, and the product 19 of the multiplier 1 and the multiplicand 2 is output.

Next, the partial product generating means 9 will be described.
FIG. 2 shows the circuit configuration. 4-bit absolute value signals 101 to 104, which are portions indicating the absolute values of the code signals 5 to 8
Are (101, 103), (101, 104), (10
2, 103) and (102, 104) as "001" generation circuits (105, 106), (107,
108), (109, 110) and (111, 112). The “001” generation circuits 105 to 112 are all the same circuit, and the MS of the input 4-bit absolute value signal is
When B is 1, "001" is output, and when MSB is 0, 3 bits excluding the MSB are output.

Outputs of the "001" generating circuits 105 to 112 are input to partial product generating circuits 113 to 116. Also, among the 4-bit absolute value signals 101 to 104, MS
B is (101, 103), (101, 104), (10
2, 103) and (102, 104) are input to the shifters 117 to 120, respectively.

The four partial product generation circuits 113 to 116 are exactly the same circuit, and receive two 3-bit (decimal 0) bits.
7) is output. The output products are input to shifters 117 to 120, respectively.

All the shifters have the same circuit, and the shifter 117 will be described here. Partial product generation circuit 1
13 and the MSB of the absolute value signal 101 and the absolute value signal 1
When the MSBs of 03 are input, the output of the partial product generation circuit 112 is shifted (through) by 0 bit when both MSBs are 0, and when one of the MSBs is 1, the partial product generation circuit 112 is shifted.
Is shifted left by 3 bits (zeroed) and output. When both MSBs are 1, the output of the partial product generation circuit 112 is shifted left by 6 bits (zeroed) and output as a partial product.

Next, the partial product adding means 18 will be described. FIG. 3 shows the configuration diagram. The partial product addition means 18 includes an addition input generation unit 200 and a 4-input addition circuit 201. The addition input generation section 200 includes addition input generation circuits 202 to
205, four partial circuits 14 to 17 and code bits 10 to 1 sent from the partial product generating means 9.
3, subtraction signals 210 to 213 and addition inputs 220 to 22
3 is generated.

Here, the configuration of the addition input generation circuit 202 will be described. The other addition input generation circuits 203 to 205 are different from each other only in the input signal, and thus the description is omitted.

FIG. 4 shows the configuration of the addition input generation circuit 202. The addition input generation circuit 202 includes the exclusive OR circuit 30.
It comprises 0, a bit inversion circuit 301 and a selector 302. The sign bit 11 and the sign bit 13 are input to the exclusive OR circuit 300, and the exclusive OR output thereof becomes a subtraction signal 210. When the sign bit 11 and the sign bit 13 are different values, that is, when the value of the partial product 14 is negative, it becomes “1”.

The partial product 14 generated by the partial product generation circuit 9
Is input to the bit inversion circuit 301 and the selector 302. In the bit inversion circuit 301, each bit of the partial product 14 is inverted and input to the selector 302. The selector 302 switches between the partial product 14 and the output of the bit inversion circuit 301 with the subtraction signal 210 and outputs the result as the addition input 220. Switching is performed such that when the subtraction signal 210 is “1”, the output of the bit inversion circuit 301 is output, and when the subtraction signal 210 is “0”, the partial product 14 is output.

The output from the addition input generation unit 200, the subtraction signals 210 to 213 and the addition inputs 220 to 223 are input to a four-input addition circuit 201. In the four-input adding circuit 201, these eight signals are the subtracted signal 210 and the added input 2
20, subtraction signal 211, addition input 221, subtraction signal 21
2 and addition input 222, subtraction signal 213 and addition input 223
Are treated as four sets.

Each of these sets is represented by (Equation 3) X ₁ Y ₁ ,
The values of X ₁ Y ₀ , X ₀ Y ₁ , and X ₀ Y ₀ are shown. The 4-input addition circuit 201 performs the addition of (Equation 3) to obtain the product 19 of P × Q. Here, the processing of 2 ⁸ and 2 ⁴ can be easily realized by shifting X ₁ Y ₁ to the left by 8 bits and shifting X ₀ Y ₁ and X ₁ Y ₀ to the left by 4 bits and adding them. or,
If the values of X ₁ Y ₁ , X ₁ Y ₀ , X ₀ Y ₁ , X ₀ Y ₀ are negative,
That is, when the subtraction signals 210 to 213 are “1”, the corresponding addition inputs 220 of the subtraction signals 210 to 213
By adding 1 to the LSB digit of 〜223 and sign-extending the digit higher than the MSB digit by 1, the subtraction can be performed by two's complement operation.

Next, a second embodiment of the multiplying circuit will be described. In the second embodiment, the absolute value signal 10 is used because the partial input generator 225 of the partial product generator 9 and the addition input generator 225 of the partial product adder 18 in the first embodiment are composed of four identical circuits.
The partial product generation / addition input generation unit is configured by one circuit by inputting 1 to 104 in a time-division manner. FIG. 5 shows the configuration in this case.

In FIG. 5, a multiplier 1 and a multiplicand 2 are input to booth coding means 3 and 4, respectively, and code signals 5 to 5 are input.
8 is generated. The code signals 5 to 8 are taken into the data latches 500 to 503, respectively, and are held for four cycles. The outputs of the data latches 500 to 503 and the code inputs 504 to 507 are input to the partial product generating / adding means 508, and the signal processed by the partial product generating / adding means 508 is output as the product 19.

Here, a description will be given of a partial product generating / adding means 508 which is different from the first embodiment. FIG. 6 shows the configuration of the partial product generating / adding means 508. Code input 504
And 505 are the code inputs 506 and 507 to the selector 600
Are input to the selector 601 respectively. Selector 60
At 0, the control signal 604 output from the control circuit 603
When the control signal 604 is "0", the code input 5
04 when the control signal 604 is “1”.
05 is output. Similarly, the selector 601 outputs a code input 506 when the control signal 605 is “0” and a code input 507 when the control signal 605 is “1” according to the control signal 605 output from the control circuit 603.
Here, the control signal 604 and the control signal 605 are changed one cycle at a time (0, 0), (1, 0), (0, 1), (1,
When switching as in 1), corresponding to (Equation 3),
A signal is selected by a combination of (X ₁ Y ₁ ), (X ₀ Y ₁ ), (X ₁ Y ₀ ), and (X ₀ Y ₀ ).

Each of the signals selected by the selectors 600 and 601 is divided into a part indicating its absolute value and a sign bit. That is, the output of the selector 600 is separated into an absolute value signal 606 and a sign bit 607, and the output of the selector 601 is separated into an absolute value signal 608 and a sign bit 609. The absolute value signal 606 and the absolute value signal 608 are each “001”.
The signals are input to the generation circuits 610 and 611. The “001” generating circuits 610 and 611 are the “001” generating circuits 105 to
Since the circuit is completely the same as 112, the description of the operation is omitted. The outputs of the “001” generation circuits 610 and 611 are input to the partial product generation circuit 612. Partial product generation circuit 612
Is the same circuit as the partial product generation circuits 113 to 116, outputs a product of 3 bits × 3 bits, and inputs the product to the shifter 613. The shifters 613 are the shifters 117 to 12.
0, the output of the partial product generation circuit 612, the MSB of the absolute value signal 606, and the MSB of the absolute value signal 608.
Output the partial product 614 from. The operation of this circuit is exactly the same as that of the shifters 117 to 120, and the description is omitted.

The partial product 614 is input to the shifter 615. The shifter 615 shifts the partial product 614 to the left by an amount specified by the shift amount control signal 616 generated by the control circuit 603. The shift amount control signal 616 gives a shift amount of 8, 4, 4, 0 bits per cycle.
As a result, processing relating to the power of 2 of (Equation 3) is performed.

The output of the shifter 615 is added to an addition / subtraction circuit 617.
Is input to The output of the addition / subtraction circuit 617 is taken into the register 618 every cycle, and the taken signal is
This is the other input of the addition / subtraction circuit 617, whereby the addition / subtraction circuit 617 operates as a cumulative adder. In the addition / subtraction circuit 617, the sign bit 607 and the sign bit 609
Signal 62 generated by the exclusive OR circuit 619 from the
When 0 is “1”, the output of the shifter 615 is subtracted from the signal taken into the register 618, and the subtracted signal 620
Is "0", the signal taken into the register 618 and the output of the shifter 615 are added. The cumulative addition is initialized by receiving a reset signal 621 generated by the control circuit 603. A signal obtained by performing cumulative addition for four cycles from the initialization is output as a product 19. The timing of this series of operations is shown in (Table 1).

[0047]

[Table 1]

In Table 1, the symbol ＾ means a power. For example, 2 ＾ 4 is 2 to the fourth power or 16
Means

[0049]

As described above, both the multiplier and the multiplicand are coded according to the higher-order Booth algorithm, the multiplier and the multiplicand are divided into a plurality of parts by using the code signal, and each divided part is multiplied. Since the product is obtained by adding the partial products obtained as described above, multiplication can be performed without increasing the circuit scale even if the bit length of the data becomes long.

When a partial product is generated, the coding is performed by using a higher-order Booth algorithm. Therefore, it is possible to generate the partial product using the same circuit. As a result, the circuit design time can be reduced.

Furthermore, one bit representing a code is taken out of the code signal, and processing relating to the bit is performed by means for adding a partial product, so that the scale of a circuit for calculating the partial product can be suppressed.

Further, MS of the M bits of the code signal
In the case of using B, there is only one type of 2M-1, and by performing the process related to the power of 2 by the shift operation, it is possible to suppress the scale of the circuit that calculates the partial product.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a multiplication circuit according to the present invention;

FIG. 2 is a configuration diagram of a partial product generation unit in the embodiment.

FIG. 3 is a configuration diagram of a partial product addition unit in the embodiment.

FIG. 4 is a configuration diagram of an addition input generation circuit in the embodiment.

FIG. 5 is a configuration diagram of another embodiment of the multiplication circuit of the present invention.

FIG. 6 is a configuration diagram of a partial product generation / addition unit in the embodiment.

[Explanation of symbols]

 1 multiplier 2 multiplicand 3, 4 Booth coding means 9 partial product generating means 18 partial product adding means 19 product 105-112 “001” generating circuit 113-116 partial product generating circuit 117-120 shifter 200 addition input generating unit 2014 input Addition circuit 202-205 Addition input generation circuit 508 Partial product generation / addition means 600, 601 Selector 610, 611 "001" generation circuit 612 Partial product generation circuit 613 Shifter 615 Shifter 617 Addition / subtraction circuit 618 Register

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/52 310 G06F 17/10

Claims (3)

(57) [Claims] 1. A means for converting both a multiplier and a multiplicand into a code signal in accordance with a higher-order Booth algorithm;
Means for generating a partial product using a signal, and adding the partial product
Means for encoding the multiplier and the multiplicand.
Each of the code signals obtained is a part representing the absolute value and the sign.
And the means for generating the partial product includes an absolute value of the code signal of the multiplier.
From the absolute value of the code signal of the value and the multiplicand to the absolute value part
The means for generating a product and adding the partial products comprises a code signal for the multiplier and the multiplicand.
If the part representing the sign of the signal is the same sign, the absolute value part
Partial product adding, multiplying circuits you and performing processing in the case of different signs for subtraction. 2. The method according to claim 1, wherein the means for generating the partial product includes a multiplier and a multiplicand.
MSB of the absolute value part of the code signal encoding the number
Is "1" (maximum value), the partial product
The multiplication circuit according to claim 1, wherein the generation is performed by a shift operation . 3. A method for encoding a multiplier and a multiplicand.
The code signal is composed of an absolute value and a part representing a sign.
Both the number and the multiplicand follow the higher order Booth algorithm.
A step of encoding signals of I, the absolute of the absolute value and the multiplicand code signal code signal of the multiplier
The step of generating a partial product of the absolute value part from the value and the part representing the sign of the code signal of the multiplier and the multiplicand are the same sign
In the case of, the partial product of the absolute value part is added, and
The step of performing a subtraction process if
Multiplication method .