JP2568608B2 - Multiplication circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit used for a central processing unit of a digital computer and performing signed multiplication.

2. Description of the Related Art Conventional multiplication circuits include, for example, "Improved approach to the use of blues multiplication algorithm" IBM Technical Disclosure Bulletin ("Impro
ved approach to the use of Booth's multiplication
algorithm ", IBM Technical Disclosure Bulletin) Vo
l.27 No.11 1985.

FIG. 7 shows a block diagram of this conventional multiplication circuit, where 1 is a multiplicand register for inputting and holding a multiplicand,
2 is a multiplier register that inputs a multiplier at the start of multiplication and holds a multiplier shifted by 3 bits in the least significant bit direction (hereinafter referred to as right) during arithmetic processing. 3b is an accumulator during arithmetic processing. The upper product register, in which the higher order of the partial product is held and the higher order of the product as the operation result is stored when the operation is completed,
Is a lower product register that holds the lower order of the accumulated partial product during operation processing and stores the lower order of the product when the operation is completed.
Is an arithmetic circuit for performing an operation between two inputs of A and B, 6
Is a multiplier shifter that shifts the value held in the multiplier register 2 to the right by 3 bits and stores the result in the multiplier register 2 again, 7 is a carry flag that holds the overflow of the multiplier shifter 6, and 8b is an accumulated partial product 3b arithmetically shifts the output of the arithmetic circuit 5b, which is the upper bit, to the right (the sign bit is copied from the most significant bit) and stores it in the upper product register 3b. 9b is the upper bit. Lower-order accumulation in which the overflow of the partial product shifter 8b is shifted in from the upper bit and the lower bit of the accumulated partial product held in the lower-order product register 4 is shifted to the right by 3 bits, and the result is again stored in the lower-order product register 4. A partial product shifter, 10b is an arithmetic control circuit for controlling the arithmetic executed by the arithmetic circuit 5b by the lower 3 bits of the multiplier register 2 and the carry flag 7, and 12 is a double multiplicand register for inputting and holding a double value of the multiplicand 13 is a triple multiplicand register for inputting and holding a triple value of the multiplicand, 14 is a quadruple multiplicand register for inputting and holding a quadruple value of the multiplicand, and 15 is a multiplicand or double multiplicand register 12 stored in the multiplicand register 1. The double or triple multiplicand stored in the register The triple or quadruple multiplicand of the multiplicand stored in the register 13
A selection circuit for selecting one of the quadruple values of the multiplicand stored in 14 and adding it to the B input of the arithmetic circuit 5b, and 16 is a multiplier register 2
Selection circuit 15 by lower 3 bits of
Is a selection control circuit for controlling the selection in the step (a).

The principle of the conventional multiplication circuit configured as described above will be described below.

As a method of multiplication, there is a Booth algorithm. This conventional multiplication circuit uses a 4-bit Booth's algorithm, and selects a partial product by cutting out 4 bits (one bit of which overlaps) from the least significant bit side of the multiplier and selecting the partial product. Find the product by accumulating. FIG. 8 is a control relation diagram of the arithmetic control circuit 10b and the selection control circuit 16 based on this algorithm.
The arithmetic circuit 5b decodes a total of 4 bits including the lower 3 bits of the multiplier register 2 indicated by 1, M0 and the carry flag 7 indicated by C.
And the selection of the selection circuit 15 to be the B input of the arithmetic circuit 5b.

 The operation of the circuit will be described below.

First, the multiplicand and the multiplier are input to the multiplicand register 1 and the multiplier register 2, respectively, and the upper product register 3b, the lower product register 4, and the carry flag 7 are cleared to zero.

The operation of the arithmetic circuit 5b and the B input are determined from the lower 3 bits of the multiplier register 2 and the carry flag 7, and the arithmetic circuit
In FIG. 8, the output of 5b is the A input as it is if the operation column is "A", the addition result of the A input and B input if "A + B",
If "AB", the result is the subtraction of the A and B inputs. In FIG. 8, if the B input field is "X" in FIG. 8, the multiplicand stored in the multiplicand register 1 is "2X", and the double value of the multiplicand stored in the double multiplicand register 12 is "2X". 3X "
If this is the case, the triple value of the multiplicand stored in the triple multiplicand register 13 is selected, and if "4X", the quadruple value of the multiplicand stored in the quadruple multiplicand register 14 is selected by the selection circuit 15. After the operation, the multiplier shifter 6, the upper accumulation partial product shifter 8b, and the lower accumulation partial product shifter 9b all shift right by 3 bits, and store the shift results in predetermined registers.

The above operation and shift are performed as follows: [bit length of multiplier 乗 3]
(Or rounded up if not divisible).

The multiplication result is stored in the upper product register 3b and the lower product register 4 separately for the upper product and the lower product register.

The above is a description of a conventional multiplying circuit using a 4-bit Booth algorithm, but the same applies to a circuit using a Booth algorithm exceeding 4 bits. That is, in the conventional multiplication circuit using the N-bit Booth algorithm, the operation of the operation circuit 5b and the B input are determined from the lower (N-1) bits of the multiplier register 2 and the carry flag 7, and the B input is , The selection circuit 15 selects a value up to the (N-2) th power of the multiplicand from the 2 (N-2) th power registers. Each of the multiplier shifter 6, the upper accumulation partial product shifter 8b and the lower accumulation partial product shifter 9b performs an (N-1) bit shift operation to the right.
The calculation and the shift are repeated for the bit length of the multiplier divided by (N-1) times (when it is not divisible, the fractional part is rounded up).

However, in the above configuration, since the input of the arithmetic circuit 5b requires a value up to four times the multiplicand, a means for generating and holding these values is indispensable. Of 4
Time must be expended to generate values up to double. In addition, to express a quadruple value of the multiplicand as a signed binary number, the bit length of the multiplicand + 2 bit length is required. Therefore, the arithmetic circuit 5b, the high-order product register 3b, the high-order accumulation partial product shifter 8b, Everything including the selection circuit 15 and the bus connecting them requires a bit length of the multiplicand bit length + 2.

The above is a problem of the conventional multiplication circuit using the 4-bit Booth's algorithm, but the same applies to the case using the Booth's algorithm exceeding 4 bits. That is, N
In the Booth's algorithm of bits, since the input of the arithmetic circuit requires values up to the multiplied value of 2 (N−2) times, means for generating and holding these values is indispensable. The problem of consuming time to generate a value up to the 2 (N-2) th power and the 2 (N-2) th power of the multiplicand are represented by a signed binary number. Requires the bit length of the multiplicand + (N−2). Therefore, the arithmetic circuit, the high-order product register, the high-order accumulation partial product shifter, the selection circuit, and the bus connecting these components are all multiplicands. Bit length + (N−
There is a problem that the bit length of 2) is required.

In view of the foregoing, the present invention does not require any multiplicative value of the multiplicand at the input of the arithmetic circuit, enables arithmetic processing with an arithmetic circuit having a bit length equal to the multiplicand, and has a higher speed than a multiplier circuit that does not use the Booth algorithm. It is an object to provide a simple multiplication circuit.

Means for Solving the Problems The present invention provides an arithmetic means for performing an operation between an accumulated value of a partial product and a multiplicand, and an accumulated value of a partial product used for a next operation by shifting an output of the arithmetic means. The multiplication circuit includes a shift unit to be generated and capable of controlling the number of shifts, and a control unit that determines the operation of the arithmetic unit and the shift number of the shift unit by decoding a bit string of a multiplier.

According to the present invention, the addition and subtraction of the multiplicand of the multiplicand can be controlled by the addition and subtraction of the multiplicand and the shift number of the shift process performed before and after the operation, or can be replaced with the repetition of the multiplication of the multiplicand. In addition, it is not necessary to increase the bit length of the arithmetic circuit.

Embodiment FIG. 1 is a block diagram of a multiplication circuit according to an embodiment of the present invention. 1 is a multiplicand register for inputting and holding a multiplicand. 2 is a multiplier input at the start of multiplication. A multiplier register 3a holds a multiplier shifted by 3 bits each, and a multiplicand register 3a stores therein the higher order of the accumulated partial product during the operation processing and stores the higher order of the product as the operation result when the operation is completed. A lower product register having a bit length equal to the multiplier register 2 for storing the lower order of the accumulated partial product during operation processing and storing the lower order of the product at the end of the operation; Is an arithmetic circuit for calculating the value of the multiplicand register 1 and the value of the high-order product register 3a, and performs a calculation having the same bit length as that of the multiplicand register 1. 6 shifts the numerical value held in the multiplier register 2 to the right by 3 bits and shifts the result again to the multiplier register 2
, 7 is a carry flag for holding the overflow of the multiplier shifter 6, and 8a is an arithmetically right-shifted output of the arithmetic circuit 5a, which is the upper part of the accumulated partial product, and is a higher-order product register 3a.
The upper accumulative partial product shifter 9a has the same bit length as the multiplicand register 1 stored in the lower accumulator partial shifter 9a. Is shifted to the right and the result is again stored in the lower product register 4. A lower accumulating partial product shifter having the same bit length as the multiplier register 2; 10a is an arithmetic circuit based on the lower 3 bits of the multiplier register 2 and the carry flag 7;
An operation control circuit for controlling the operation executed by 5a. A shift 11 for controlling the number of shifts by the upper accumulation partial product shifter 8a and the lower accumulation partial product shifter 9a by the lower 6 bits of the multiplier register 2 and the carry flag 7. It is a number control circuit.

The principle of the multiplying circuit of this embodiment configured as described above will be described below.

The multiplication circuit of this embodiment is based on the 4-bit Booth algorithm. In this algorithm, the accumulated value of the partial product is shifted right by 3 bits, and zero, ± 1 times the multiplicand, ± 2 times the multiplicand, ± 3 times the multiplicand,
A product is obtained by repeating accumulation of any partial product of ± 4 times the multiplicand. Here, as shown in FIGS. 3 (a) and 3 (b), a series of processes of shifting the immediately preceding operation result to the right by 3 bits, adding / subtracting the double value of the multiplicand, and shifting the operation result to the right by 3 bits are performed as follows. Since the least significant bit of the doubled value of the multiplicand is 0, it is replaced by a series of processes including a 4-bit right shift of the immediately preceding operation result, an addition / subtraction of the multiplicand, and a 2-bit right shift of the operation result. Further, addition and subtraction of a triple value of a multiplicand is equivalent to consecutively performing addition and subtraction of a multiplicand and addition and subtraction of a double value of a multiplicand. Since the least significant bit of the double value of the multiplicand is 0, the fourth As shown in FIGS. 7A and 7B, a series of processes of shifting the immediately preceding operation result to the right by 3 bits, adding and subtracting a triple value of the multiplicand, and shifting the operation result to the right by 3 bits are performed in series. It is replaced by a series of processing including a 3-bit right shift of the operation result, addition / subtraction of the multiplicand, a 1-bit right shift of the operation result, an addition / subtraction of the multiplicand, and a 2-bit right shift of the operation result. Similarly, since the lower two bits of the quadruple value of the multiplicand are both 0, FIGS. 5 (a) and 5 (b)
As shown in the figure, the previous operation result is shifted right by 3 bits,
A series of processing of addition / subtraction of a quadruple value of a multiplicand and a 3-bit right shift of an operation result is a series of processing including a 5-bit right shift of a previous operation result, an addition / subtraction of a multiplicand, and a 1-bit right shift of an operation result. Be replaced. From these facts, the multiplying circuit of this embodiment is capable of adding / subtracting the multiplicand and adding 1
The product is obtained by repeating a right shift of bits to 5 bits.

FIG. 2 shows an arithmetic control circuit 10a based on the above concept.
In the control relationship diagram of the shift number control circuit 11, the lower 3 bits of the multiplier register 2 indicated by M2, M1, and M0 and the carry flag 7 indicated by C are decoded to a total of 4 bits, and the operation of the operation circuit 5a is performed.
Lower 5 bits of multiplier register 2 indicated by M5, M4, M3, M2, M1, M0 (K1 and K2 in FIG. 2A are 4 to 6 bits from lower order of multiplier register 2 as shown in FIG. 2B) And C)
The 7 bits of the carry flag 7 indicated by the symbol (7) are decoded to determine the shift numbers of the upper accumulation partial product shifter 8a and the lower accumulation partial product shifter 9a. In FIG. 2, the operation "A" represents the A input as it is, "A + B" represents the addition of the A input and the B input, and "AB" represents the subtraction of the A input and the B input.

 The operation will be described below.

First, the multiplicand and the multiplier are input to the multiplicand register 1 and the multiplier register 2, respectively, and the upper product register 3a, the lower product register 4, and the carry flag 7 are cleared to zero.

The value of the multiplicand register 1 and the value of the high-order product register 3a are input to the arithmetic circuit 5a, and the operation determined by the arithmetic control circuit 10a is performed. The shifter 8a and the lower accumulation partial product shifter 9a shift right by the number of bits determined by the shift number control circuit 11, and store the shift results in the upper product register 3a and the lower product register 4, respectively. Here, in the case where the number of calculations and shifts are described in the second column in FIG. 2A, the above calculation and shift are performed twice according to the contents. Further, the shift (2 in FIG. 2A)
If the number of operations and the number of shifts are listed in the second column,
In parallel with the second shift), the value of the multiplier register 2 is shifted to the right by 3 bits by the multiplier shifter 6, and the result is stored in the multiplier register 2 and overflow is stored in the carry flag 7.

The above operation and shift are performed by the number of shifts in the multiplier shifter 6 (the operation control circuit 10a and the shift number control circuit 11
Is repeated until the bit length of the multiplier is divided by three times (if it is not divisible, the fractional part is rounded up).

The result of the multiplication is stored in the upper product register 3a and the lower product register 4 separately for upper and lower products.

As described above, according to this embodiment, the number of shifts in the high-order accumulation partial product shifter 8a and the low-order accumulation partial product shifter 9a that is provided after the arithmetic circuit 5a is made variable from 1 bit to 5 bits, and the shift is performed. By controlling the number with the lower 6 bits of the multiplier register 2 and the carry flag 7, a multiple value of the multiplicand is not required at the input of the arithmetic circuit, and arithmetic processing can be performed by the arithmetic circuit having a bit length equal to the multiplicand. In addition, the processing time is reduced by an average of 2.4 in comparison with a multiplier circuit that does not use the Booth algorithm. This is 1
The average operation corresponding to decoding is 1 × 12/16 + 2 × 4/1
Since 6 = 1.25 times, the processing time in the present algorithm that shifts by 3 bits is based on the calculation that it becomes 1 / (3 ÷ 1.25).

Although the multiplication circuit of this embodiment is based on the 4-bit Booth algorithm, the present invention does not limit the number of bits of the Booth algorithm based on this.

The arithmetic control circuit 10a of the multiplier circuit according to the embodiment of the present invention based on the N-bit Booth algorithm controls the arithmetic circuit 5a by decoding the lower (N-1) bits of the multiplier register 2 and the carry flag 7, Shift number control circuit 11
Decodes the lower 2 (N-1) bits of the multiplier register 2 and the carry flag 7 to control the upper accumulation partial product shifter 8a and the lower accumulation partial product shifter 9a. The shift number of the upper accumulation partial product shifter 8a and the lower accumulation partial product shifter 9a is variable from 1 bit to (2N-3) bits.
The multiplier shifter 6 shifts to the right by (N-1) bits. The average processing time decreases with increasing N. Figure 6 shows 5
In the control relation diagram of the arithmetic control circuit 10a and the shift number control circuit 11 of the multiplication circuit according to another embodiment of the present invention based on the Bit Booth algorithm, the lower 4 bits of the multiplier register 2 indicated by M3, M2, M1, and M0. The arithmetic circuit 5a decodes a total of 5 bits of the carry flag 7 indicated by the bit and C, and calculates M7, M6,
The lower 8 bits of the multiplier register 2 indicated by M5, M4, M3, M2, M1 and M0 and the carry flag 7 indicated by C, that is, 9 bits in total, are decoded, and the upper accumulated partial product shifter 8a and the lower accumulated partial product shifter 9a are decoded. Is determined.

Effect of the Invention As described above, according to the present invention, the multiplication value of the multiplicand is not required at the input of the arithmetic circuit, the arithmetic processing can be performed by the arithmetic circuit having a bit length equal to the multiplicand, and the Booth algorithm can be used. Signed multiplication can be performed faster than a multiplication circuit that does not use it, and its practical effect is large. In addition, in an arithmetic logic unit (ALU) as arithmetic means or a microprocessor having a shift means, by adding a small amount of hardware, a multiplicand having a bit length equal to the bit length of the arithmetic logic arithmetic unit can be obtained. There is also an effect that multiplication can be realized at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiplication circuit in one embodiment of the present invention, FIG. 2 is a control relation diagram of an arithmetic control circuit and a shift number control circuit in the embodiment, and FIG. 3 is twice the multiplicand in the embodiment. FIG. 4 is an explanatory view showing the principle of replacement of addition and subtraction of values;
FIG. 5 is an explanatory view showing the principle of addition and subtraction of a triple value of a multiplicand in the embodiment, FIG. 5 is an explanatory view showing the principle of addition and subtraction of a quadruple value of a multiplicand in the embodiment, and FIG. FIG. 7 is a block diagram of a conventional multiplication circuit, and FIG. 8 is a block diagram of a conventional multiplication circuit, and FIG. 8 is a block diagram of a calculation control circuit and a selection control circuit in the conventional example. It is a control relation diagram. 1 multiplicand register, 2 multiplier register, 3a, 3b upper product register, 4 lower product register, 5a, 5b arithmetic circuit,
6: Multiplier shifter, 7: Carry flag, 8a, 8b: Higher accumulation partial product shifter, 9a, 9b: Lower accumulation partial product shifter, 10a, 10b
... Arithmetic control circuit, 11 shift number control circuit, 12 double multiplicand register, 13 triple multiplicand register, 14 quadruple multiplicand register, 15 selection circuit, 16 selection control circuit.

Claims (1)

(57) [Claims] An arithmetic means for performing an operation between an accumulated value of a partial product and a multiplicand; and a shift number for shifting an output of the arithmetic means to generate an accumulated value of a partial product used in a next operation. A multiplication circuit comprising: a shift unit that can be controlled; and a control unit that determines an operation of the arithmetic unit and a shift number of the shift unit by decoding a partial bit string of a multiplier.