JPS63298627A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To decrease the number of clocks without executing the operation itself and to execute the high speed of a multiplication by adding or subtracting the circuit to n-fold a partial product and a multiplier at the multiplying circuit with the Booth's algorithm and shifting the partial product by an arbitrary bit. CONSTITUTION:In the example of 0000, 0010bX0011, 0001b, control data (a), (b) and (c) are calculated from multipliers 0011 0001b. This is calculated with a control data generating circuit 10 from a multiplier 4 and the shifting quantity (a) of multiplicand is sent to a shifting circuit 7, +/- control data (b) are sent to a control circuit 8 and a partial product shifting quantity (c) is sent to a control circuit 5. For the shifting quantity of the multiplicand, '1' is (-), '0' is (+), and for the partial shifting quantity, '00' is '2', '01' is '4', '10' and '6', and '11' is '8'. At the time of the adding to add '0' to the partial product, at the multiplying circuit, by shifting the partial product of many bits, the operation itself is not executed and the number of clocks can be decreased.

Description

[Detailed description of the invention] <Industrial application field> The present invention relates to multiplication circuits, and more particularly to high-speed multiplication circuits.

<Prior Art> Conventionally, high-speed multiplication circuits of this type often use the Booth algorithm.

<Problems to be Solved by the Invention> When attempting to realize the above-mentioned conventional multiplication circuit by repeating processing to obtain partial products for each clock using the n-th order Booth algorithm, the number of bits of the multiplier/n (n is integer) clock is required. Therefore, there was a problem that the multiplication speed was low.

For example, in the second-order Booth algorithm, the values of O1±1 and ±2 of the multiplicand are added depending on the value of the multiplier.

As shown in Table 1 above, roOOJ and "111" only need to be shifted by adding "0", and no calculation is required.

<Means and operations for solving the problems> The present invention has a means for adding or subtracting a partial product and a multiplier multiplied by n (n is an integer) in a multiplication circuit using Booth's algorithm; It is characterized by having a shift means for shifting a partial product by arbitrary bits to obtain the next partial product.

Therefore, in contrast to the above-mentioned conventional multiplication circuit, the present invention has an original content in that when performing an operation of adding '0' to a partial product, by shifting a multi-bit partial product, the number of clocks is reduced without performing the operation itself. .

<Example> Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1, FIG. 2, and FIG. 3 are diagrams showing one embodiment of the present invention.

In Figure 1, 1 is the barrel shifter, 2 is the partial product, 3 is the multiplicand,
4 is a multiplier, 5 is a partial product shift control circuit, 6 is a multiplicand shift circuit, 7 is a multiplicand shift control circuit, 8 is an addition/subtraction control circuit, 9 is an adder/subtractor, and 10 is a control data generation circuit.

The explanation will now be made according to the examples shown in FIGS. 2 and 3. This is 000
0 0010bXOO110001b is taken as an example. First, control data a, b, and c are calculated from multipliers 0011 0001b as shown in FIG. In FIG. 1, this is calculated using the circuit 10 from the multiplier 4, and the shift amount of the multiplicand of a is sent to the shift circuit 7, the +/- control data of b is sent to the control circuit 8, and the shift amount of the partial product of C is The signal is sent to the control circuit 5. Note that the shift amount of the multiplicand is 01 x 1.10 x 2, and the +/- control data is 1 (-) and O ((-).
+), and the partial product shift amount is 00 is 2.01 is 4.
10 is 6.11 is 8.

Next, explanation will be given using FIG. First, in step 1, 1 times the multiplicand is added to the partial product. At this time, C in Figure 2 is 4
Since this shows a bit shift, the next partial product is one shifted by 4 bits by barrel shifter 1. Next, in step 2.3, calculate each partial product, and the result is 0100 00
10b is obtained.

FIG. 4 is a block circuit diagram showing a second embodiment of the present invention. In FIG. 4, numerals 1 to 9 have the same configuration as in FIG. 11 is a microcode ROM. now.

The same result can be obtained by configuring the system to perform the processing in FIGS. 2 and 3 using the value of the multiplier 4. The second embodiment has the effect of reducing the amount of hardware compared to the first embodiment.

<Effects of the Invention> As explained above, the present invention has the effect of providing a high-speed multiplication circuit by executing arbitrary bit shifts of partial products.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the first embodiment of the present invention, FIG. 2 is a flow chart showing the procedure for forming control data from multipliers, FIG. 3 is a flow chart showing the calculation procedure, and FIG. Second
FIG. 2 is a block circuit diagram showing an example. 1... Barrel shifter, 2... Partial product, 3... Multiplicand, 4... Multiplier. 5... Partial product shift control circuit, 6... Multiplicand shift circuit, 7... Multiplicand shift control circuit, 8... Addition/subtraction control circuit, 9... Addition/subtraction device, 10... ...Control data generation circuit, 11...Micro code ROM. Patent applicant Kiyoshi Kuwai, agent for NEC Corporation and patent attorney - Figure 1-10. 2n Thousand Days 5TEP 32 1 Figure 2 Figure 4

Claims (1)

[Claims] A multiplication circuit using Booth's algorithm has means for adding or subtracting a partial product and a multiplier multiplied by n (n is an integer), and further has a means for shifting the partial product by arbitrary bits to obtain the next partial product. A multiplication circuit characterized in that it has a means.