JPH01193932A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To realize an arithmetic processing in an arithmetic circuit having the same bit length as a multiplicand by providing a shift means which shifts the output of an operation means, generates the accumulation value of a partial product used for a subsequent operation and controls the number of shifts. CONSTITUTION:The value of a multiplicand register 1 and that of a high-order product register 3a are inputted to the arithmetic circuit 5a, and the operation decided in an arithmetic control circuit 10a is executed, whereby the operated result and the content of a low-order register 4 are shifted to right in a high- order accumulation partial product shifter 8a and a low-order accumulation partial product shifter 9a by the number of bits decided in a shift number control circuit 11. Shift results are respectively stored in the high-order product register 3a and the low-order product register 4. The number of shifts in the high-order accumulation partial product shifter 8 and the low-order accumulation partial product shifter 9a are set to be variable to one bit and five bits, and the number of shifts is controlled by low-order six bits in a multiplication register 2 and a carry flag 7. Thus, the multiple value of the multiplicand is eliminated in the input of the arithmetic circuit, and the arithmetic processing is realized in the arithmetic circuit having the same bit length as the multiplicand.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplication circuit that is used in a central processing unit of a digital computer and performs signed multiplication.

Conventional technology Conventional multiplication circuits include, for example, "In Blue But Approach to Use of Blue Multiplication Algorithm" published by IBM.
Technical Disclosure Bulletin (“Imp
roved approach to the use
of Booth's multiple
ion algorithm-IBM Technic
al Disclosure Bulletin)
Vol. 27 No. 111985.

FIG. 7 shows a block diagram of this conventional multiplier circuit, in which 1 is a multiplicand register that inputs and holds the multiplicand, 2
3b is a multiplier register that inputs a multiplier at the start of multiplication and holds the multiplier shifted by 3 bits in the direction of the least significant bit (hereinafter referred to as right) during arithmetic processing. an upper product register, 4, in which the upper part of the partial product is held and the upper part of the product, which is the calculation result, is stored when the calculation is completed;
is a lower product register, 5, which holds the lower part of the accumulated partial product during the calculation process and stores the lower part of the product when the calculation ends.
b is an arithmetic circuit that performs an operation between two inputs A and B;
6 is a multiplier shifter that shifts the numerical value held in multiplier register 2 to the right by 3 bits and stores the result in multiplier register 2 again, 7 is a carry flag that maintains overflow of multiplier shifter 6, and 8b is an accumulated partial product. 9b is an upper accumulation partial product shifter which arithmetic shifts the output of the arithmetic circuit 5b, which is the higher order of the bit, to the right by 3 bits (the sign bit is copied from the most significant bit) and stores it in the upper product register 3b. While shifting the digits of the partial product shifter 8b from the upper part, the lower part of the cumulative partial product held in the lower product register 4 is shifted to the right by 3.
12 is a lower cumulative partial product shifter that bit-shifts and stores the result again in the lower product register 4; A double multiplicand register 13 inputs and holds a double value of the multiplicand; 13 a triple multiplicand register inputs and holds a triple value of the multiplicand;
4 is a quadruple multiplicand register that inputs and holds the quadrupled value of the multiplicand, and 15 is a multiplicand stored in multiplicand register 1 or a double value of the multiplicand stored in double multiplicand register 12 or stored in triple multiplicand register 13. A selection circuit 16 selects either the triple value of the multiplicand stored in the multiplicand register 14 or the quadruple value of the multiplicand stored in the quadruple multiplicand register 14 and applies it to the B input of the arithmetic circuit 5b. This is a selection control circuit that controls the selection in the selection circuit 15 using the flag 7.

The principle of the conventional multiplication circuit configured as described above will be explained below.

Booth's algorithm is a multiplication method. This conventional multiplier circuit uses the 4-bit Booth algorithm, and uses 4 bits from the least significant bit of the multiplier.
The product is obtained by cutting out bits (of which one bit overlaps), selecting partial products, and accumulating the partial products.

FIG. 8 shows an arithmetic control circuit 10 based on this algorithm.
b and the control relationship diagram of the selection control circuit 16, M2, Ml, M
The lower 3 bits of the multiplier register 2 indicated by O and the carry flag 7 indicated by C, a total of 4 bits, are decoded and sent to the arithmetic circuit 5b.
and the selection of the selection circuit 15 which becomes the B input of the calculation circuit 5b.

The operation of the circuit will be explained below.

First, a multiplicand and a multiplier are input into multiplicand register 1 and multiplier register 2, respectively, and upper product register 3b, lower product register 4, and carry flag 7 are cleared to zero.

The calculation of the arithmetic circuit 5b and the 8-man power are determined from the lower 3 bits of the multiplier register 2 and the carry flag 7, and if the operation column in FIG. ”, the result is the addition of the eight-person force and the B input, and “A − B” is the result of the subtraction, the eight-person force and the B input. In addition, the B input in FIG. , if "3X", the triple value of the multiplicand stored in the triple multiplicand register 13 is selected, and if "4X", the quadruple value of the multiplicand stored in the quadruple multiplicand register 14 is selected in the selection circuit 15.

After the calculation, the multiplier shifter 6, the upper accumulated partial product shifter 8b, and the lower accumulated partial product shifter 9b all shift three bits to the right, and store the shift results in respective predetermined registers.

The above operations and shifts are as follows: [Bit length of multiplier ÷ 3]
Repeated times (if not divisible, round up the decimal part).

The multiplication results are held in the upper product register 3b and the lower product register 4 separately into upper and lower parts.

The above description is about a conventional multiplication circuit using a 4-bit Booth algorithm, but the same applies to a multiplication circuit using a Booth algorithm of more than 4 bits. That is, in the conventional multiplication circuit using the N-bit Booth's algorithm, the calculation and the input power of the calculation circuit 5b are determined from the lower (N-1) bits of the multiplier register 2 and the carry flag 7, and the B input is , the selection circuit 15 selects 2 of the multiplicand from 2 (N-2) east side registers.
Values up to the (N-2) power are selected.

The multiplier shifter 6, the upper cumulative partial product shifter 8b, and the lower cumulative partial product shifter 9b all perform a (N-1) bit shift operation to the right, and the calculation and shift is calculated by dividing the bit length of the multiplier by dividing the bit length of the multiplier.
It is repeated (N-1) times (if it is not divisible, the decimal part is rounded up).

Problems to be Solved by the Invention However, in the above configuration, a value up to four times the multiplicand is required as an input to the arithmetic circuit 5b, so a means to generate and hold these values is essential. 4
Time must be spent to generate the value up to the double value. In addition, in order to express the quadrupled value of the multiplicand in a signed binary number, the bit length of the multiplicand + 2 is required, so the arithmetic circuit 5b, the upper product register 3b, the upper cumulative partial product shifter 8b, Everything including the selection circuit 15 and the bus connecting them requires a bit length of the multiplicand plus two.

The above are the problems of the conventional multiplication circuit using the 4-bit Booth algorithm, but the problems are also the same for those using the Booth algorithm of more than 4 bits. That is, in the N-bit Booth algorithm, values up to the multiplicand multiplied by 2 (N-2) are required as inputs to the arithmetic circuit, so a means to generate and hold these values is essential.
There is also the problem that time must be consumed to generate a value up to the multiplicand multiplied by 2 (N-2).
To express the (N-2) multiplication value of 2 of the multiplicand in a signed binary number, the bit length of the multiplicand + (N-2) is required. The problem is that everything including the upper cumulative partial product shifter, the selection circuit, and the bus connecting these requires a bit length of the multiplicand plus (N-2).

In view of these points, the present invention eliminates the need for multiples of the multiplicand in the input of the arithmetic circuit, allows arithmetic processing to be performed using an arithmetic circuit with a bit length equal to the multiplicand, and is faster than a multiplication circuit that does not use Booth's algorithm. The purpose of this invention is to provide a multiplication circuit that is easy to use.

Means for Solving Problem and a control means for determining the calculation in the calculation means and the shift number in the shift means by decoding a bit string of a part of the multiplier. .

Effect of the Invention With the above-described configuration, the present invention can replace the addition and subtraction of multiples of the multiplicand by controlling the number of shifts in the shift processing performed before and after the addition and subtraction of the multiplicands, or by repeating the same. Also, there is no need to increase the bit length of the arithmetic circuit for this purpose.

Embodiment FIG. 1 shows a block diagram of a multiplication circuit in an embodiment of the present invention. 1 is a multiplicand register for inputting and holding a multiplicand, and 2 is a register for inputting a multiplier at the start of multiplication and a register on the right during arithmetic processing. 3a is a multiplicand register 1 that holds the multiplier shifted by 3 bits into the multiplier register 3a, which holds the high-order part of the accumulated partial product during calculation processing, and stores the high-order value of the product that is the calculation result when the calculation is completed. 4 is a lower product register with a bit length equal to that of multiplier register 2; 4 is a lower product register with a bit length equal to multiplier register 2; 4 is a lower product register that holds the lower part of the accumulated partial product during calculation processing and stores the lower part of the product when the calculation is completed; is an arithmetic circuit that performs an operation on the value of the multiplicand register 1 and the value of the upper product register 3a, and performs an operation with the same bit length as the multiplicand register 1. 6 is a multiplier shifter that shifts the value held in multiplier register 2 by 3 bits to the right and stores the result in multiplier register 2 again; 7 is a carry flag that maintains the overflow of multiplier shifter 6; 8a is an accumulated partial product An upper cumulative partial product shifter with a bit length equal to the multiplicand register 1, which arithmetic shifts the output of the arithmetic circuit 5a, which is the upper one, to the right and stores it in the upper product register 3a.9a is an overflow of the upper cumulative partial product shifter 8a. Shift the lower part of the accumulated partial product held in the lower product register 4 to the right while manually shifting from the upper part, and store the result in the lower product register 4 again.Lower accumulated part with bit length equal to multiplier register 2 product chic, 10
11 is an arithmetic control circuit that controls the arithmetic operation executed in the arithmetic circuit 5a using the lower 3 bits of the multiplier register 2 and the carry flag 7; and 11, the upper cumulative partial product shifter 8a and This is a shift number control circuit that controls the number of shifts shifted by the lower cumulative partial product shifter 9a.

The principle of the multiplication circuit of this embodiment configured as described above will be explained below.

The multiplication circuit of this embodiment is based on a 4-bit Booth algorithm. In the same algorithm,
Shift the accumulated value of partial products to the right by 3 bits and accumulate any of the partial products of zero, ±1 times the multiplicand, ±2 times the multiplicand, ±3 times the multiplicand, or ±4 times the multiplicand 1m. Find the product by repeating the calculation.

Here, as shown in FIGS. 3(a) and 3(b), the series of processes of shifting the previous operation result by 3 bits to the right, adding or subtracting the double value of the multiplicand, and shifting the operation result to the right by 3 bits is , since the least significant bit of the double value of the multiplicand is O, it is replaced by a series of processing consisting of a 4-bit right shift of the previous operation result, addition/subtraction of the multiplicand, and 2-bit right shift of the operation result. Furthermore, adding and subtracting the triple value of the multiplicand is equivalent to adding and subtracting the multiplicand and adding and subtracting the double value of the multiplicand, and since the least significant bit of the double value of the multiplicand is 0, the fourth As shown in Figures (a) and (b), the series of processes of shifting the previous operation result by 3 bits to the right, adding or subtracting the triple value of the multiplicand, and shifting the operation result by 3 bits to the right This is replaced by a series of processing consisting of a 3-bit right shift of the operation result, addition and subtraction of the multiplicand, 1-bit right shift of the operation result, addition and subtraction of the multiplicand, and 2-bit right shift of the operation result.

Similarly, since the lower two bits of the quadrupled value of the multiplicand are both 0, 1
The series of processes of shifting the previous operation result by 3 bits to the right, adding or subtracting the quadrupled value of the multiplicand, and shifting the operation result to the right by 3 bits is as follows:
This is replaced by a series of processing consisting of a 5-bit right shift of the previous operation result, addition/subtraction of the multiplicand, and a 1-bit right shift of the operation result. For these reasons, the multiplication circuit of this embodiment repeatedly adds and subtracts the multiplicands and shifts the result by 1 to 5 bits to the right to obtain a product.

FIG. 2 shows an arithmetic control circuit 10a based on the above-mentioned concept.
and the control relationship diagram of the shift number control circuit 11, M2. Ml,
The lower 3 bits of the multiplier register 2 indicated by MO and the carry flag 7 indicated by C, a total of 4 bits, are decoded and sent to the arithmetic circuit 5.
a calculation, and M5. M4. M3゜M2. The lower 6 bits of multiplier register 2 indicated by Ml and MO (K in FIG.
l, K2 are multiplier registers 2 as shown in the same figure (b).
(determined by 4 to 6 bits from the lowest order) and a carry flag 7 indicated by C, a total of 7 bits are decoded to determine the shift number of the upper cumulative partial product shifter 8a and the lower cumulative partial product shifter 9a. . In Figure 2, the operation “3
A'' is eight-person power as is, “A + B” is eight-person force and B
Addition of inputs, "A-B" represents subtraction of A and B inputs.

The operation will be explained below.

First, a multiplicand and a multiplier are input into multiplicand register 1 and multiplier register 2, respectively, and upper product register 3a, lower product register 4, and carry flag 7 are cleared to zero.

After inputting the value of the multiplicand register 1 and the value of the upper product register 3a to the arithmetic circuit 5a and performing the arithmetic operation determined by the arithmetic control circuit 10a, the result of the operation and the contents of the lower product register 4 are used as the upper cumulative partial product. The shifter 8a and the lower cumulative partial product shifter 9a shift to the right by the number of bits determined by the shift number control circuit 11, and store the shift results in the upper product register 3a and the lower product register 4, respectively. Here, the second
If the number of calculations and shifts is written in the second column in Figure (a), the above calculations and shifts are performed twice according to the contents. In addition, the above shift (Fig. 2 (a)
), in parallel with the second shift), the multiplier shifter 6 shifts the value of the multiplier register 2 to the right by 3 bits, and the result is transferred to the multiplier register 2. Then, the overflow is stored in the carry flag 7.

The above calculations and shifts are performed by the number of shifts in the multiplier shifter 6 (calculation control circuit 10a and shift number control circuit 1).
1) is the bit length of the multiplier divided by 3 times (
If it is not divisible, round up the decimal part.

The multiplication results are held in the upper product register 3a and the lower product register 4 separately into upper and lower parts.

As described above, according to this embodiment, the number of shifts in the upper cumulative partial product shifter 8a and the lower cumulative partial product shifter 9a provided after the arithmetic circuit 5a is made variable from 1 bit to 5 bits, and the shift Lower 6 of multiplier register 2
Control using bits and the carry flag 7 eliminates the need for multiples of the multiplicand in the human power of the arithmetic circuit, and allows arithmetic processing to be performed using an arithmetic circuit having the same bit length as the multiplicand. Furthermore, the processing time is reduced to 1/2.4 on average compared to a multiplication circuit that does not use Booth's algorithm. This means that the calculation corresponding to one decoding is on average lX12/
16+2X4/16=1.25 times, so the processing time for this algorithm that shifts 3 bits is (3÷1.2
5) It is based on the calculation that it becomes 1/1.

Although the multiplication circuit of this embodiment is based on a 4-bit Booth's algorithm, the present invention does not limit the number of bits of the Booth's algorithm on which it is based.

The arithmetic control circuit 10a of the multiplication circuit in the embodiment of the present invention based on the N-bit Booth algorithm decodes the lower (N-1) bits of the multiplier register 2 and the carry flag 7 to control the arithmetic circuit 5a, Shift number control circuit 1
1 decodes the lower 2 (N-1) bits of the multiplier register 2 and the carry flag 7 to control the upper accumulated partial product shifter 8a and the lower accumulated partial product shifter 9a. Additionally, an upper cumulative partial product shifter 8a and a lower cumulative partial product shifter 9a
The number of shifts is variable in the range of 1 bit to (2N-3) bits, and the multiplier shifter 6 shifts (N-1) bits to the right. The average processing time is shortened as N increases. FIG. 6 shows an arithmetic control circuit 1 of a multiplication circuit in another embodiment of the present invention based on the 5-bit Booth algorithm.
0a and the control relationship between the shift number control circuit 11 and M3. M
2. A total of 5 bits of the lower 4 bits of the multiplier register 2 indicated by Ml and MO and the carry flag 7 indicated by C are decoded to perform the operation of the arithmetic circuit 5a and M? , M6. M5. M4. M=
16=3, M2. A device that decodes a total of 9 bits of the lower 8 bits of the multiplier register 2 indicated by Ml and MO and the carry flag 7 indicated by C to determine the shift number of the upper accumulated partial product shifter 8a and the lower accumulated partial product shifter 9a. It is.

As described in detail, the present invention eliminates the need for multiples of the multiplicand at the input of the arithmetic circuit, allows arithmetic processing to be performed using an arithmetic circuit with a bit length equal to the multiplicand, and allows the Booth algorithm to be implemented. Signed multiplication can be performed faster than a multiplication circuit that is not used, and its practical effects are great. Also, an arithmetic logic unit (ALU) as a calculation means.
In a microprocessor or the like equipped with a shift means or a shift means, by adding a small amount of hardware, the multiplication of a multiplicand having a bit length equal to the bit length of the arithmetic and logic unit can be multiplied at high speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a multiplication circuit in one embodiment of the present invention, Fig. 2 is a control relationship diagram of the arithmetic control circuit and shift number control circuit in the same embodiment, and Fig. 3 is a multiplicand twice the number in the same embodiment. Explanatory diagram showing the substitution principle of addition and subtraction of values, Part 4
The figure is an explanatory diagram showing the replacement principle for adding and subtracting a value 3 times the multiplicand in the same embodiment. Figure 5 is an explanatory diagram showing the replacement principle for adding and subtracting a value 4 times the multiplicand in the same embodiment. Figure 6 is an explanatory diagram showing the replacement principle for adding and subtracting a value 4 times the multiplicand in the same embodiment. FIG. 7 is a block diagram of a conventional multiplier circuit, and FIG. 8 is a control diagram of an arithmetic control circuit and a selection control circuit in the conventional example. FIG. 1... Multiplicand register, 2... Multiplier register, 3a
. 3b... Upper product register, 4... Lower product register,
5a, 5b... Arithmetic circuit, 6... Multiplier shifter, 7.
... Carry flag, 8a, 8b... Upper cumulative partial product shifter, 9a, 9b... Lower cumulative partial product shifter, 10a
, 10b... Arithmetic control circuit, 11... Shift number control circuit, 12... 2x multiplicand register, 13... 3x multiplicand register, 14... 4x multiplicand register, 15
...Selection circuit, 16...Selection control circuit.

Claims (1)

[Claims] A calculation means for performing an operation between an accumulated value of partial products and a multiplicand, and a shifting means for shifting the output of the operation means to generate an accumulated value of partial products to be used for the next operation, the number of shifts being controllable. . A multiplication circuit comprising: a control means for determining an operation in the arithmetic means and a shift number in the shift means by decoding a part of a bit string of a multiplier.