JPH01314020A - Decimal/binary conversion system - Google Patents

Abstract

PURPOSE:To reduce the processing time and to suppress the increase in the quantity of hardware by applying the decimal to binary conversion in the unit of two digits in a decimal number (in the unit of byte). CONSTITUTION:A value being a multiplication of a high-order 1 digit by 10 in a decimal 2-digit (1 byte) segmented sequentially from the high order of a decimal numeral string 2 by a selector 1 is given to an adder 5, the low-order 1 digit is given directly to the adder 5 and values being the result of multiplication of a carry and a sum by a factor of 100 respectively by shifters 4-1, 4-2 are supplied to the adder 5. Then the addition of (100 times the result of preceding cycle)+(10 times the high-order decimal 1 digit)+(low-order decimal 1 digit) is applied and the sum of carriers and check-sum being the result of addition is outputted as the result of decimal-binary conversion. Since the signal is converted into a binary signal by decimal 2-digit (1 byte) each in such a way, the processing time is reduced and the quantity of hardware is decreased.

Description

[Detailed Description of the Invention] [Summary] ■Regarding a decimal-to-binary conversion method for converting a θ-adic number into a binary number, converting two decimal digits into a binary number at a time to shorten processing time and reduce the amount of hardware. The purpose is to convert the decimal number to 10.
It is equipped with a shifter that multiplies a plurality of decimal numbers, an adder that adds a plurality of input decimal numbers, and a shifter that multiplies each of the carry and sum output from this adder by 100.
Cut out the top two digits of the 0-decimal number, and select the top 1 of them.
Input the value obtained by multiplying the digit by 10 using the shifter, the value of the lower 1 digit, and the value obtained by multiplying the carry and sum output from the adder in the previous cycle by 100 using the shifter, into the adder. The process of calculating the sum is repeated and the sum of the carry and sum is output as a decimal-to-binary conversion result.

[Industrial application field]

The present invention uses decimal 2 when converting a decimal number into a binary number.
This invention relates to a decimal-to-binary conversion method that aims to shorten processing time and reduce the amount of hardware by converting digits (1 byte) at a time into binary numbers.

[Conventional technology]

Conventionally, there is a method shown in FIG. 3 as one method for converting a decimal number into a binary number. This is performed by cutting out the decimal string 32 one digit (4 bits) from the higher order by the selector 31 and inputting it into a binary ADD (three-man power adder) 35, as well as the output of the adder 35 obtained in the previous cycle. (output of the Result register 40) is multiplied by 8 (3-bit shift) and doubled (1-bit shift) by the shifter 33.
There is a method in which decimal-binary conversion is performed by inputting the obtained values into two systems and performing binary addition.

[Problem to be solved by the invention]

This conventional method cuts out one decimal digit every cycle and adds it to the result of the previous cycle while aligning the digits to convert it into a binary number, so the total number of cycles required to convert to a binary number is However, the number of digits of the decimal number + (previous and subsequent processing) is required, and there is a problem that the processing time increases when the number of digits of the decimal number to be converted is large.

The present invention aims to shorten processing time and reduce the amount of hardware by converting two decimal digits into binary numbers.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, a selector 1 cuts out a decimal number string 2 to be converted into a binary number into two decimal digits (one byte) at a time.

Shifter 3 is for multiplying one decimal digit by 10. Shifter 4
-1.4-2 is for multiplying each of the carry and sum output from the adder 5 by 100.

The adder 5 transfers the upper one digit of the two decimal digits (1 byte) extracted from the decimal string 2 by the selector l to the shifter 3.
The value obtained by multiplying by 10, the value of the lower one digit, and the value obtained by multiplying each of the carry and sum sent from the adder 5 in the previous cycle by 100 are added.

[Effect]

In the present invention, as shown in FIG.
Out of the two decimal digits (1 byte) that are sequentially cut out from the high-order decimal number string 2, the value obtained by multiplying the high-order 1 digit by 10 using the shifter 3 is input to the adder 5, and the low-order 1 digit is directly input to the adder 5. Input,
The values obtained by multiplying the carry and sum sent from the adder 5 in the previous cycle by 100 using shifters 4-1 and 4-2 are inputted to the adder 5, and the result is (previous cycle result x 100 times) + (upper decimal 1). digit XIO times) + (lower 1 decimal digit)
is added, and the sum of the carry and sum of the addition result is output as a decimal-to-binary conversion result.

Therefore, by converting two decimals (1 hyde) into binary, it is possible to shorten the processing time, and by simply adding a selector to the existing multiplier (see Figure 2), a special Since there is no need to provide a dedicated circuit, it is possible to reduce the amount of hardware.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be sequentially explained in detail using FIG.

Shifter (SFT) and decoder based on Booth's algorithm and C3A (Carry 5aye Ad
der), in which the number of multiplier bits to be decoded in l cycles is large, C3A
Focusing on the fact that multiple shifters are provided in front of the Give an example.

In FIG. 1, a selector 1 cuts out a decimal number string 2 to be converted into a binary number into two decimal digits (one byte) at a time.

Shifter 3 multiplies one decimal digit by 10, and 2
It consists of two shifters [8x (3-bit shift) and 2x (1-bit shift)].

Shifters 4-1 and 4-2 each multiply the carry and sum sent from the adder 5 by 100, and
They are each composed of three shifters: 64 times (6-bit shift), 32 times (5-bit shift), and 4 times (2-bit shift)].

The adder (C3A) 5 is a multi-input adder capable of high-speed operation, and performs addition on a bit-by-bit basis and separately outputs the result as a carry and a sum on a bit-by-bit basis. This addition is performed by multiplying the upper 1 digit of the 2 decimal digits (1 byte) extracted by the selector l by 10 using the shifter 3, the value of the lower 1 digit, and the carrier output from the adder 5 in the previous cycle. and the sum multiplied by 100 by shifters 4-1 and 4-2 are added.

The ALU 8 adds the carry and sum sent from the adder 5 to generate a decimal-to-binary conversion result.

Next, the operation will be explained.

First, in the l-th cycle, the most significant decimal 2 of the 16-digit (8-byte) decimal number string 2 that is the target of the decimal-to-binary conversion instruction is
Digit (1 byte) For example, cut out KL shown in the figure using selector 1, divide the number KL into 1 digit (4 bits) each, and use shifter 3 to divide the upper digit by 10 times [8 times (3 bit shift) + 2 times (
1 bit shift)], the digits are aligned and inputted to the adder 5, and the lower digits are directly inputted to the adder 5. At this time, the shifters 4-1, 4-2 are suppressed by '01', and "O" is inputted to the adder 5 from these shifters 4-1, 4-2. As a result, ×10 is added to the output of shifter 3, and the outputs “O” of shifters 4-1 and 4-2 that are directly input are input to adder 5 and added, and the two most significant decimal digits “KL
The result of converting `` into a binary number is stored in the carry register 6 and the sum register database as a carry and a sum.

In the second cycle, selector 1 cuts out the next upper two digits (1 byte) MN of decimal number string 2, divides the number into 1 digit (4 bit) units, and multiplies the upper digit M by 10 using shifter 3. The digits are aligned and inputted to the adder 5, and the lower digit N is directly inputted to the adder 5.

Further, the shifter 4-1, 4-2 transfers the carry and sum sent from the adder 5 in the previous cycle, that is, in this case, the first cycle, by 10 each in a loop bank manner.
After being multiplied by 0 times [64 times (6-bit shift)) + 32 times (5-bit shift) + 4 times (2-bit shift)], it is input to the adder 5. As a result, the adder 5 calculates [1st cycle result (+L to 10) x 100) + (higher 1 digit (
M)

Thereafter, the same operation as in the second cycle is repeated for the number of remaining bytes of decimal string 2, and then the carry and sum held in the carry register 6 and the sum register 7 are added by the ALU 8, and the result is decimal -2. Calculate the result of the base conversion.

As mentioned above, the number cut out in two decimal digits and the carry and sum of the previous cycle are adjusted to make the converted 10
By repeating addition for 1/2 cycles of the number of digits in the base number, it becomes possible to convert the decimal number into a binary number at high speed.

FIG. 2 shows an example of an 8 byte x 2 byte multiplier. In the figure, SFT is a shifter that aligns each digit of the multiplicand column 2-1 and shifts the multiplicand in accordance with the multiplier. The result of shifting corresponding to this digit alignment and multiplier is CS A (Carry 5ave Add
er) The carry and sum resulting from the addition by 5 are held in the carry register 6 and the sum register. Then, by repeating this operation, multiplication is performed.

By adding a selector as shown in FIG. 1 to this multiplier in FIG.
It becomes possible to configure a circuit that extracts 0-digits into two digits at a time and converts them into binary numbers at high speed. This makes it possible to manufacture a circuit that achieves the decimal-to-binary conversion method in FIG. 1 by adding a small amount of hardware to the multiplier shown in FIG. 2.

Here, the functions of the selectors 9 to 19 added in FIG. 1 to the multiplier in FIG. 2 will be briefly explained.

In FIG. 1, selectors 1 and 9 are for cutting out two arbitrary decimal digits from decimal string 2, selectors 18 and 10 to
12 inputs the carry of the previous cycle sent from the adder 5 to the shifter 4-1; selectors 19.13 to 15;
is the sum of the previous cycle sent from adder 5 to shifter 4
-2 input, selector 16 is cut out 10
The lower one digit of the two decimal digits is input to the adder 5, and the selector 17 is used to input 0'' to the adder 5.

〔Effect of the invention〕

As explained above, according to the present invention, 10
Cut out the decimal number into two decimal digits (1 byte) and multiply the upper 1 digit by 10 by thick, the lower 1 digit, and the carry and sum sent from the adder in the previous cycle by 100. Since we have adopted a configuration that performs decimal-to-binary conversion by repeatedly adding the values, it is possible to perform decimal to binary conversion in units of two decimal digits (in units of 1 byte), reducing processing time. It is possible to shorten the time. Furthermore, since the present invention can provide a decimal-to-binary conversion function by adding simple hardware such as a shifter to the existing multiplier shown in FIG. 2, there is no need to provide a special dedicated circuit. It is possible to suppress an increase in the amount of hardware.

[Brief explanation of the drawings] Fig. 1 is a configuration diagram of one embodiment of the present invention, Fig. 2 is an 8-byte)
An example of a 2-byte multiplier, FIG. 3 shows an explanatory diagram of the prior art. In the figure, 1 is a selector, 2 is a decimal string, and 3 is a chic (1
4-1.4-2 is a shifter (100 times), 5 is an adder (C3A), 6 is a carry register, 7 is a sum register, and 8 is an ALU (adder). Patent distributor Fujitsu Limited

Claims (1)

[Claims] A decimal-to-binary conversion method for converting a decimal number into a binary number includes: a shifter (3) that multiplies a decimal number by 10; an adder (5) that adds a plurality of input decimal numbers; , and shifters (4-1) and (4-2) that multiply the carry and sum output from this adder (5) by 100, respectively, cut out the upper two digits of the decimal number to be converted, and The value obtained by multiplying the first digit by 10 using the shifter (3) above,
The value of the lower 1 digit and the above adder (5) in the previous cycle
The carry and thumb output from the shifter (4-1
) and the value multiplied by 100 in (4-2), respectively, are input to the adder (5) and the process of calculating the sum is repeated, and the sum of carry and sum is output as a decimal-to-binary conversion result. A decimal-to-binary conversion method characterized by the following configuration.