JPS5957342A - Decimal adder - Google Patents

Abstract

PURPOSE:To improve the processing speed by executing a correcting phase in the same cycle as the phase of intermediate sum for the addition being the 2nd and succeeding, in executing the accumulative addition of plural binary coded decimal numbers by means of 3-input binary adders. CONSTITUTION:In executing the accumulative addition of n-set of decimal numbers Di, values D1, D2 are set respectively to registers 2, 3, intermediate sums S0-S3 outputted from the adder 1 are set to the register 2 in the 1st addition phase, carry outputs C0-C3 of each digit are set to a holding register 5 and the next value D3 is set to the register 3. The intermediate sum of the (i-1)th addition from the register 2 in the i-th adder is applied to the 1st input of the register 3, a value Di+1 is applied to the 2nd input from the register 3, (0) is applied to a CIN input, and (0) or (6) is selected at each digit depending on the content of the register 5 and applied to the 3rd input. In the final correcting phase, 0000 is applied to the 2nd input from the register 3, (1) is applied to the CIN input and the selecting circuit 4 selects (9) or F and applies it to the 3rd input.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decimal adder in an information processing device that performs cumulative addition of a plurality of binary coded decimal numbers in an alongside cycle.

[Prior art]

Conventionally, when adding two decimal numbers using the only three-manpower binary adder, two cycles of processing were required for one decimal addition because correction as an io-base number was required. I was going. Namely.

In the first addition (intermediate sum phase), the summand, the addend, the hexadecimal display values '°66...6''' and 0'' are respectively added to the first and second nodes of the three-man binary adder. Addition is made to the third manpower and carry manpower.

At this time, derive the carry output from each digit.

hold this. In the next second addition (correction phase), among the results obtained by the first addition, the corresponding carry output is "°6" independently from the °'0" digit.
The decimal number is obtained by subtracting ', and in order to do so, the intermediate sum obtained from the first addition result, the hexadecimal display value °°000'', and the decimal number in the first addition are Set the digit of output par 0'' as "F"' II I
Hexadecimal number with digit II as '9'': and II I
II respectively to the first . Second. Binary addition is performed by applying it to the third human power and the carry human power, resulting in an accurate decimal number. However, n 1
In order to perform cumulative addition of decimal numbers by repeating the above method, 2 (n-1) addition cycles are required, which is a factor that reduces the processing speed of decimal cumulative addition. Furthermore, when this method is applied to a decimal multiplication method in which multiplicands corresponding to multipliers are repeatedly added, the processing speed required for cumulative addition becomes even more noticeable.

[Purpose of the invention]

An object of the present invention is to perform cumulative addition of a plurality of binary coded decimal numbers using a three-person binary adder.

The object of the present invention is to provide a decimal adder in an accumulator by eliminating the conventional drawbacks by controlling the correction phase in the second and subsequent additions to be executed in the same cycle as the phase for calculating the intermediate sum.

[Structure of the invention]

The decimal addition device of the present invention is an information processing device that performs cumulative addition of a plurality of binary coded decimal numbers in a plurality of cycles. a binary adder; means for selecting either the summand or an intermediate sum obtained as an output of the adder and supplying the selected sum to a first input of the adder; Addend to one of the intermediate sums.

or means for selecting one of the constants and supplying it to the second input of the adder, and independently for each digit, the hexadecimal display value I
I Q II, 115''', "9" or II F
and means for selecting one of the IHs and supplying it to the third input of the adder.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to the configuration diagram of FIG. In this figure, 1 is a three-person binary adder I
(hereinafter i1i will be referred to as an adder), 2 is a register that supplies the summand at the time of the first addition or the output of adder 1 to the first input of this adder l.

3 is a register that supplies the addend for the first input of adder l to the second input of adder 1; 4 is a hexadecimal display value II Q II for each digit (4 bits, 1.) independently; 1.61+
.

9" or F11 and supplies it to the third input of the adder. 5 is a register that holds the carry output of each digit obtained from the adder 1.

The output logic of the selection circuit 4 is as follows: In a decimal adder configured as shown in Table 1, cumulative addition of n decimal numbers (1≦i≦n) is performed. D
The procedure for executing 1+D2+...+D is as follows. First, as preprocessing, register 1
and D and D2 are set in the laser star 2, respectively. Next, the first addition phase (initial addition phase)
, the output of register 2 is input to the first input of adder 1, the output of register 3 is input to the second input, and 0''' is input to the carry input CIN.Furthermore, 2 selections Ii'il Path 4 is designated with ``first addition'', and the third input of adder 1 is supplied with ``6666''.

When the adder 1 receives these inputs, the adder 1 calculates the intermediate sum as S. -8
3, and the carry output of each digit of the intermediate sum as C
6-Output to C5. S of adder 1. The intermediate sum outputted from -83 is set in register 2, and the carry output of each digit taken out from C6-C5 is set in holding register 5, respectively. D3 is set in register 3 in preparation for the primary addition.

In the i-th addition phase (2≦1≦n-1) (intermediate addition and correction phase), the first input of adder l is either the intermediate sum by the (+-1)th addition from register 2, or
The second input is supplied with D, +, and "0" from the register 3, respectively, and the IN input is supplied with "0". °'1st addition''
As shown in Table 1, the selection circuit 4 that is instructed to select "'"
0″' or 6″″ is selected for each digit and supplied to the third input of adder 1. When adder 1 receives these inputs, it calculates the intermediate sum D1-1-D2+ that requires correction.・・・・・・
10, +1 to S. -85, the carry output of each digit is output from C3-C3, respectively. The intermediate sum output from 5o-83 is set in register 2, and the carry output of each digit is set in holding register 5, respectively. here,
If 1 is i (n - 1), DI+2 is set in register 3 in preparation for the next (i+1) addition, and 1
2. Repeat the process described in section 2 until = n-2. 1=n-
If it is 1, register 3 contains "oooo" in preparation for the nth addition.
” is set.

In the nth addition phase (final correction phase),
The first input of adder 1 is the intermediate sum that requires correction from register 2, +D2+...+Dn, and the second input is ``o o o o'' from register 3.

°°1'' is supplied to the C1N input, respectively.The selection circuit 11 is instructed to perform the ``nth addition''.

As shown in Table 1, select II 9 II or II F II for each digit according to the contents of the corresponding holding register 5 [2. It supplies the third power of adder l. When the adder 1 receives these inputs, it adds the desired value (D, 102+...+D) to S by an addition operation. -Output from 83.

In order to understand more specifically the contents of the processing cycle in the above addition operation, as an example, five decimal numbers are 0.
278, D2=121.4. D3=2165°D4-390.4 and D5-0580 are selected, and their addition result is D1+D2+D3+D4+D5-8141
The input/output states of the force adder 1 in each addition phase to obtain the following are shown below.

Below margin [1st addition] 1st human power 0278 2nd human power 1214 3rd human power 6666 C1N input + 0 ssss output 7AF2 0 1 23 CCCC output 0001 01 25 [2nd addition] 1st input 7AF2 2nd human power 2165 3rd human power 0006 C1N input 10 05sss output 9C5D 01 25 CoC1C2C5 output 0010 [3rd addition] 1st human power 9C5D 2nd human power 3904 3rd human power 0060 CIN input 10 0 8oS1S2S3 output D5CI CoC1C2C3 output 01 01 [4th addition] 1st human power D5C1 1st 2 human power 0580 3rd human power 0606 C1N input + 0 ssss output E147 0125 cccc output 0110 01 23 [5th addition] 1st human power E147 2nd human power 0000 3rd human power 9FF9 C1N input + 1 SoS1S2S3 output 814 1 [Effect of the invention] Above As is clear from the explanation of 1. According to the present invention, when performing cumulative addition of lO base numbers of n (L) using only one three-manpower binary adder, n times of addition including decimal correction are required. It becomes possible to process.

This makes it possible to speed up decimal cumulative addition.

The effects that can be obtained when applied to information processing devices to improve processing performance are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In the figure, ] is a three-person binary adder + 2 +
3 + 5 is a register, and 4 is a selection circuit. Figure 1

Claims (1)

[Scope of Claims] 1. An information processing device that performs cumulative addition of a plurality of binary coded decimal numbers in a plurality of cycles, comprising a carry manual means to the lowest digit and a carry output means from each digit.
Manual binary adder and summand. or means for selecting one of the intermediate sums obtained as the output of the adder and supplying it to the first power of the adder;
The addend for either the summand or the intermediate sum, or the -i value constant, is selected and the second of the adder is selected.
and means of supplying human power. The hexadecimal display value °゛0''', “15” is displayed independently for each digit.
I+. A decimal addition device characterized by comprising means for selecting either °"9" or °"Fll and supplying it to the third human power of the adder.