JPH0621983B2 - Multiplier - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a multiplication method, and in particular, a multiplication that can directly perform 2N double precision multiplication only by adding a simple circuit to the N double precision multiplication circuit. Regarding the scheme.

[Background of the Invention]

FIG. 1 shows a configuration example of a conventional high speed multiplier. In the figure, the multiplier set in the multiplier register 2 is divided into four, sequentially selected from the lower order by the multiplier selection circuit 3, and the multiple generation circuit 4 generates a multiple of the multiplicand set in the multiplicand register 1. The generated multiple is input to the carry save adder touri 5. Carry save
The adder and tree 5 has a plurality of carry
The save adders (carry-hold adders) 6 to 13 are arranged in a tree shape, and the number of a plurality of addition targets is finally reduced to two. The operation of the carry-save adder itself is held in the form of a half carry separately from the sum without propagating the carry from three inputs as shown in the addition example of FIG. At this time, the sum is also called a half-sum because it is different from the usual meaning. In addition, since carry takes the longest time to propagate, in the high-speed multiplier, as shown in FIG. Carry propagation addition is carried out by a propagator adder (carry propagation adder) 14 and is put together. A partial product in the form of a harp carry and a half sum due to a lower multiplier is right-shifted by a multiplier bit to add to a higher partial product,
It is input to carry-save-adder-towery 5 again. At this time, due to the right shift, the portion spilled from the carry save adder tree 5 is summed by the spill adder (spill adder) 15 and set to a predetermined lower position of the multiplication result register 16.

FIG. 4 is a diagram showing a configuration example of a conventional quad precision multiplication circuit,
Quadruple precision multiplication is performed by multiplying the multiplicand and the multiplier set in the multiplicand register 21 and the multiplier register 22 by the upper α (double precision), the lower β (double precision), and the multiplier of the multiplicand, as shown in FIG. It is divided into upper γ (double precision) and lower δ (double precision), and is multiplied by the multiplier 23 in the order of β × δ, α × δ, β × γ, α × γ, and the result is the multiplication result register 24. Set to. This multiplication result is added in the following order by the double precision adder 25 having an additional circuit for the quadruple precision operation, and the final result is obtained.

(1) β × δ _H + α × δ _L ... Carrying to the upper level.

(2) (Addition result of the above (1)) + β × γ _L ... Carrying to the upper rank.

(3) α × δ _H + β × γ _H + (carry from addition in (1) above) + (carry from addition in (2) above) ... Carry hold to higher rank.

(4) (Addition result of (3) above) + α × δ _L ... Carrying to the upper rank.

(5) α × γ _H + (carry from addition of (3) above) + (above
Carry from addition of (4)).

Although the final product normalization is omitted here, further normalization may be necessary. Also, α ×
The last H and L such as β _H and α × δ _L are 4 in the multiplier 23.
The upper and lower sides of the double precision multiplication result are shown, respectively.
FIG. 3 diagrammatically shows the digit alignment of the above four products.

As described above, since the quadruple precision multiplication is conventionally performed in the above-described procedure, the execution time is four times the execution time of the double precision multiplication.
It had the drawback of being considerably longer than double.

[Object of the Invention]

The present invention has been made in view of the above points, and has a basic configuration of an N-double precision multiplication circuit, and by adding a simple means, 2N-double precision multiplication is directly performed, and 2N-double precision multiplication is performed. An object of the present invention is to provide a multiplication method that makes the time shorter than four times the execution time of N-fold precision multiplication.

[Outline of Invention]

The gist of the present invention is that 2N double precision data using a multiplication circuit of N double precision data having a multiple generation circuit to which n bit data and m (n is an integer multiple of m, where m ≠ n) are input. In the multiplier, the multiplicand selection means for dividing the 2N-precision multiplicand by adding zeros as lower bits to 2n-bit data and selecting one as upper data and lower data, and the 2N double-precision multiplier Multiplier selecting means for selecting data divided into m bits by adding zero as a lower bit to 2n bits and selecting a multiplier division part of an arbitrary digit, the multiplicand selecting means and the multiplier selecting means are provided. , The selection of the data by the multiplicand selection means and the digit division of the partial product of the multiplier division part selected by the multiplier selection means are performed in the order from the lower order to the higher order. The multiple generation circuit multiplies the data selected by the multiplicand selection means and the multiplier division part selected by the multiplier selection means to obtain a multiple, and further adds the obtained multiple and a lower partial product. And a carry save adder touri that outputs the upper partial product and the upper partial product or the upper partial product that is right-shifted by the m bits are regarded as the lower partial product and the carry Shifting of the digit aligning means by the digit aligning means feeding back to the save adder tree, and the correspondence between the digit position of the selected multiplier division part and the upper / lower position of the data selected by the multiplicand selecting means It has a control means for controlling the presence / absence, and a carry propagator adder and a spill adder to which the upper partial product is input.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a diagram showing the configuration of a multiplication circuit according to an embodiment of the present invention. The multiplicand registers 31, 32 and the multiplier register 3 are shown.
3, 34, the upper 56 bits of the multiplicand and the multiplier, the lower 56
Each bit is set. In the multiplication circuit shown in FIG.
The multiplier used for the multiplication of degrees is 16 bits, and the multiplicand selection circuit 35 outputs 64 bits, which is four times 16 bits, to the multiple generation circuit 37 as the multiplicand. That is, the upper 8 bits of the lower data are merged with 56 bits of the upper data as the data A1, and 16 zeros are merged with the remaining 48 bits of the lower data as the data A2. On the other hand, in the multiplier selection circuit 6, when 16 zeros are added to the upper data 33 and the lower data 34 of the multiplier to make 128 bits, B1 and B
2, ... Out of the eight data of B8, one is sent to the multiple generation circuit 37. The multiple generation circuit 37 is composed of eight multiple generators. Each multiple generator has a multiplier of 1 bit + data 2 bits of 3 as shown in FIG.
A multiple is generated corresponding to each bit pattern with one bit as a set, and the lower bit of the 2 bits of the multiplier data in a certain multiplier generator overlaps with the multiplier correction bit in the adjacent lower multiplier generator. And is using it. Therefore, when 16 bits of the multiplier data B _i are sent to the multiple generation circuit 37, they are simultaneously sent to the least significant bit multiple generation circuit 37 of the data B _i −1. The reason why the data B8 is sent to the multiple generation circuit 37 even though the data B8 is zero is that the lowest bit of B7, which is the lowest data of the multipliers sent at the same time, is used for correction. Further, the correction bit for the data B1 is 0. To briefly explain FIG. 8, since the multiple of the multiplicand is generated only by shifting and inverting the multiplicand without adding, for example, when the multiplier in a certain multiple generator is “011”, it is not a triple but a quadruple. Is generated, and when the multiplier is “100” in the adjacent lower-order multiple generator, by generating a negative four-fold number (corresponding to a negative one-fold number in the original multiple generator), it becomes substantially a triple number. To do. FIG. 8 shows that the 2's complement conversion needs to be corrected to the 2's complement because the 1's complement can be obtained only by inverting the multiplicand. Further, when the multiplier is “111” in the figure, all the multiplicands are set to 1 and the correction of 2 is set to zero.

First, an outline of the operation when the multiplication circuit of FIG. 5 is used as a double precision multiplier will be described with reference to the multiplication order of FIG.

(1) A multiple of the multiplicand of 56 bits × the multiplier of 3 bits is output to each of the eight output lines of the multiple generation circuit 37, which is input to the carry save adder tree 38 to output the data A1 and the data B4. Partial product (A1 x B4) 5
1 is required in the form of half carry and half thumb.

(2) As in (1) above, data A1 and data B are generated by the multiple generation circuit 37 and the carry save adder tree 38.
The partial product (A1 × B3) 52 with 3 is obtained. the above
The difference from (1) is that the partial product A1 × B4 in (1) is shifted to the right by 16 bits by the partial product digit alignment selection circuit 39 and is input to the carry save adder tree 38 and A
The sum of 1 × B3 is taken and by shifting to the right,
The spilled A1 × B4 lower 16 bits are summed by the spill adder 41.

(3) Similar to (2) above, the partial product 53 of A1 × B2 is obtained.

(4) Similar to (2) above, the partial product 54 of A1 × B1 is obtained.

(5) Carry Propagate Adder 4 with partial products 51 to 54 required in the form of half carry and half sum.
By 0, they are combined into one and the multiplication result is obtained.

Next, the operation when the multiplication circuit of FIG. 5 is used as a quad precision multiplier will be described. The 16-bit multiplication is executed in the order shown in FIG. At this time, the difference from the double precision multiplication is in the following four cases. That is, (i) partial product 61 or partial product 65 and partial product 66, (ii) partial product 61 or partial product 67 and partial product 68, and (iii) partial product 61 or partial product 69 and partial product 70. And (iv) the sum of the partial product 61 or the partial product 71 and the partial product 72 is different from the double precision multiplication. In this case, the partial product is input to the carry save adder tree 38 without shifting it by 16 bits to the right. At this time, the spill adder 41 is not used either.

Here, it is the partial product digit matching selection circuit 39 that selects whether the partial product is 16 bits to the right or is left as it is.

In quad precision multiplication, 16-bit multiplication is executed 16 times,
For the lower part, only the carry to the upper part is picked up, and as a result, only 116 bits of the result register groups 42 to 46 are obtained. The 4 bits of the result register 46 are used as a card digit when the most significant result is 0 when 4 bits are 1 digit. Result register group 42-
The data set by 46 will be described below according to the calculation means shown in FIG.

When shifting the partial products 61 to 73 to the right by 16 bits, the upper 4 bits of the bits are set in the result register 46.

In the result register 45, when shifting the partial products 61 to 74 to the right by 16 bits, the sum 16 bits obtained by the spill adder 41 is set.

In the result register 44, when shifting the partial products 61 to 75 to the right by 16 bits, the sum 16 bits obtained by the spill adder 41 is set.

The result register 43 corresponds to the upper 65 to 80 bits of the partial product 61 to the partial product 76.
The 16 bits of the sum obtained by the adder 41 are set.

In the result register 42, the 64-bit sum corresponding to the upper 1 to 64 bits of the partial product 61 to the partial product 76, which is obtained by the carry propagate adder 40, is set.

As described above, according to the above-described embodiment, the 2N double precision multiplication circuit is converted into the N double precision multiplication circuit without doubling the scales of the multiple generation circuit 37 and the carry save adder tree 38 which are the main parts of the multiplication circuit. You can basically configure
The effects shown in (1) to (3) are obtained.

(1) It is not necessary to divide the 2N double precision multiplication into four N double precision multiplications as in the conventional case, and the execution time can be shortened.

(2) Conventionally, if 2N double precision multiplication is divided into N double precision four multiplications and the product of these four multiplications is combined into one by an N double precision adder, 2N double precision is specially conscious. I had the circuit that I did in the N double precision adder
The structure of the double precision adder can be simplified.

(3) When the 2N double precision is divided into four multiplications of N double precision and the product of these four multiplications is sent to the N double precision adder as in the conventional case, even if the most significant digit is zero. It is not necessary to select a special result of sending without normalization, and the selection circuit of the result of multiplication can be simplified.

〔The invention's effect〕

As described above, in the multiplier according to the present invention, the data selected from the multiplicand and the multiplier division part selected from the multiplier are sequentially selected such that the digit positions of these partial products are from the lower order. . Therefore, the partial product of the data selected from the multiplicand and the multiplier division part selected from the multiplier,
The sum of the output of the carry-save-adder-towery that was calculated the last time where there was no right shift,
That is, the accumulation of the partial products of the data selected from the multiplicand and the multiplier division part selected from the multiplier can be sequentially obtained by carry-save-adder-towery. Therefore, the output of the carry propagator adder and spill adder at the time when the carry save adder touri operation for the upper and lower data of the multiplicand and all the multiplier division parts of the multiplier is completed is 2N.
The result is the multiplication of the double precision multiplicand and the multiplier. That is, it is possible to directly obtain the 2N-double precision multiplication result without obtaining the N-double precision multiplication result. As a result, in the present invention, 2N
Compared with the method of dividing double-precision multiplication into N-double precision four-degree multiplication, an adder for adding the divided and calculated results is not required, so that the configuration can be simplified, and As a result of not requiring addition, it is possible to obtain a remarkable effect that the execution time can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a conventional high speed multiplier, FIG. 2 is a diagram showing an example of carry-save addition, FIG. 3 is a diagram showing multiplication order and digit alignment, and FIG. FIG. 5 is a diagram showing a configuration example of a double precision multiplication circuit, FIG. 5 is a diagram showing a configuration of a 2N double precision multiplication circuit based on the N double precision multiplication circuit according to the present invention, and FIG.
FIG. 7 and FIG. 7 are views showing the order of multiplication by N double precision multiplication and multiplication by 2N double precision multiplication and digit alignment, respectively, using the multiplication circuit of FIG. 5, and FIG. 8 shows the multiples generated by the multiple generator. FIG. 1 ... Multiplier register, 2 ... Multiplier register, 3 ... Multiplier selection circuit, 4 ... Multiple generation circuit, 5 ... Carry save adder tree, 6 to 13 ... Carry save
Adder, 14 ... Carry Propagate Adder, 15
... Spill Adder, 16 ... Multiplication result register, 21
…… Multiplicand register, 22 …… Multiplier register, 23 ……
Multiplier, 24 ... Multiplication result register, 25 ... Adder,
26 ... Addition result register, 31, 32 ... Multiplicand register, 33, 34 ... Multiplier register, 35 ... Multiplier selection circuit, 36 ... Multiplier selection circuit, 37 ... Multiple generation circuit, 38 ... Carry save・ Adder Toury, 40
... Carri Propagate Adder, 41 ... Spill
Adder, 42-46 ... Result register group.

Continuation of front page (56) Reference JP-A-57-59245 (JP, A) JP-A-50-115740 (JP, A) JP-A-58-137045 (JP, A) JP-A-53-135534 (JP , A)

Claims (1)

[Claims] 1. Multiplication of 2N double-precision data using an N-double precision data multiplication circuit having a multiple generation circuit into which n-bit data and m (n is an integer multiple of m, where m ≠ n) are input. In the device, a multiplicand selecting means for dividing data having 2n bits by adding zero as a lower bit to the 2N double precision multiplicand and selecting one as upper data and lower data, and a lower number for the 2N double precision multiplier Add zero as a bit to 2
There is provided multiplier selection means for dividing the data configured into n bits every m bits to select a multiplier division part of an arbitrary digit, and the multiplicand selection means and the multiplier selection means are selected by the multiplicand selection means. The digit selection is performed in the order in which the digit positions of the partial products of the data and the multiplier division part selected by the multiplier selection means are from lower to higher, and the multiple generation circuit is selected by the multiplicand selection means. A carry save adder for multiplying the data by the multiplier division part selected by the multiplier selecting means to obtain a multiple, and further adding the obtained multiple and the lower partial product to output an upper partial product. Torie and the upper partial product, or the upper partial product shifted to the right by m bits to the right, is regarded as the lower partial product and fed to the carry save adder tree. Whether or not the shift is performed by the digit aligning means is controlled by the correspondence between the digit aligning means to be locked and the digit position of the selected multiplier division part and the upper / lower position of the data selected by the multiplicand selecting means. Control means and a carry propagator to which the upper partial product is input.
A multiplier having an adder and a spill adder.