JPS6149715B2 - - Google Patents

Info

Publication number
JPS6149715B2
JPS6149715B2 JP56185018A JP18501881A JPS6149715B2 JP S6149715 B2 JPS6149715 B2 JP S6149715B2 JP 56185018 A JP56185018 A JP 56185018A JP 18501881 A JP18501881 A JP 18501881A JP S6149715 B2 JPS6149715 B2 JP S6149715B2
Authority
JP
Japan
Prior art keywords
circuit
signal
absolute value
digital
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56185018A
Other languages
Japanese (ja)
Other versions
JPS5886637A (en
Inventor
Toshiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56185018A priority Critical patent/JPS5886637A/en
Publication of JPS5886637A publication Critical patent/JPS5886637A/en
Publication of JPS6149715B2 publication Critical patent/JPS6149715B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Description

【発明の詳細な説明】 本発明は自然2進数にPCM(パルス符号変
調)化された2つのデイジタル信号の混合比の和
が常に1となるよう混合制御するデイジタル混合
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital mixing circuit that performs mixing control such that the sum of the mixing ratios of two digital signals converted into PCM (pulse code modulation) into natural binary numbers is always 1.

この種の混合制御は次式に示されるものであ
る。
This type of mixing control is shown in the following equation.

A×C+B×(1−C) (0C1)
………1 ここでAは一方のデイジタル入力信号、Bは他
方のデイジタル入力信号、Cは混合比制御信号で
ある。単純にこの制御を実現するには式1の第1
項と第2項のために乗算手段を2つ備えねばなら
ない。デイジタル乗算器は専用のLSiを必要とす
るほど複雑となり、またその単価も高く、使用数
を削減することが好ましい。
A×C+B×(1-C) (0C1)
......1 Here, A is one digital input signal, B is the other digital input signal, and C is a mixing ratio control signal. To simply realize this control, the first equation of Equation 1
Two multiplication means must be provided for the term and the second term. Digital multipliers are so complex that they require a dedicated LSi, and their unit costs are high, so it is desirable to reduce the number of digital multipliers used.

そこで式1を展開して次式とし、乗算手段を1
つにする方法も考えられる。
Therefore, formula 1 is expanded to the following formula, and the multiplication means is 1
There are also ways to make it.

B+(A−B)×C ………2 これは式2の第2項の演算のために、減算器と
乗算器、更に第1項と第2項との加算用として加
算器があればよい。しかし第2項括弧内の正負は
入力信号ABの如何によるもので、前記乗算器は
補数扱い(符号付き演算)でなければならない。
このように限定された乗算器を使用するのは好ま
しくない。特にビツト長が小さくてよい場合、乗
算をP−ROMで代行する手段がよく用いられる
が符号付き演算であるサインビツト分1ビツトの
増加は無視できない。
B+(A-B)×C......2 This means that for the calculation of the second term in Equation 2, there is a subtracter and a multiplier, and if there is an adder for addition of the first term and the second term, good. However, the sign in the parentheses of the second term depends on the input signal AB, and the multiplier must be treated as a complement (signed operation).
It is undesirable to use such a limited multiplier. In particular, when the bit length may be small, a means of substituting multiplication by P-ROM is often used, but the increase of one bit corresponding to the sign bit, which is a signed operation, cannot be ignored.

本発明は、このような従来の問題を解決し、1
個の符号なし乗算手段を用い、入力信号の混合比
の和が1となる混合制御を行なう回路を実現しよ
うとするものである。以下に本発明について説明
する。
The present invention solves these conventional problems and provides 1
The present invention attempts to realize a circuit that performs mixing control such that the sum of the mixing ratios of input signals is 1 using unsigned multiplication means. The present invention will be explained below.

前記した式2を更に分解すれば次のようにな
る。
Further decomposition of the above equation 2 results in the following.

A−B0ならB+|A−B|×C
………(3−1) A−B<0ならB−|A−B|×C
………(3−2) 上式で明らかなように、あらかじめ2つの入力
信号A,Bの差の正負判別を行ない。その結果に
より(3−1)式と(3−2)式とのいずれかの
信号処理結果を出力すれば、第2項は2つの入力
信号の差の絶対値|A−B|と混合比Cという、
いずれも正の信号同志の乗算となり、符号つき乗
算手段を必要としなくなる。
If A-B0 then B+ | A-B | ×C
......(3-1) If A-B<0 then B-|A-B|×C
(3-2) As is clear from the above equation, it is determined in advance whether the difference between the two input signals A and B is positive or negative. Depending on the result, if the signal processing result of either equation (3-1) or equation (3-2) is output, the second term is the absolute value of the difference between the two input signals |A-B| and the mixing ratio Called C.
In either case, positive signals are multiplied together, eliminating the need for signed multiplication means.

図は本発明を適用した一実施例の構成を示す図
であり、デイジタル入力信号AとBとを混合比制
御信号Cで制御し、出力信号Dを得ようとするも
のである。
The figure shows the configuration of an embodiment to which the present invention is applied, in which digital input signals A and B are controlled by a mixing ratio control signal C to obtain an output signal D.

同図において1は絶対値回路、2は乗算器、3
はALU(Arithmetic Logic Units)である。
In the same figure, 1 is an absolute value circuit, 2 is a multiplier, and 3 is a multiplier.
are ALUs (Arithmetic Logic Units).

この実施例において、デイジタル入力信号Aと
Bとはいずれも絶対値回路1に供給され、差の絶
対値信号|A−B|と同時に正負極性信号とを出
力する。絶対値信号|A−B|は乗算器2の一方
の入力に導かれ、もう一方の入力には混合比制御
信号Cが供給される。乗算器2はこうした2つの
正数同志を乗算し、適当なビツト長に丸めた後、
積信号|A−B|×CをALU3の一方の入力に
導く。またALU3のもう一方の入力にはデイジ
タル入力信号Bが供給される。ALU3は例えば
SN74S381のような切換信号により加減算の切換
えを行なうことができるもので、前記の絶対値回
路1で差の絶対値信号|A−B|を求める際生し
た正負極性信号により、この切換えが行なわれ
る。この動作はデイジタル入力信号の大小関係で
AがBより大なら、B+|A−B|×Cと加算を
行ない、AがBより小ならばB−|A−B|×C
と減算を行なうものである。このALU3の出力
信号Dを前記入力デイジタル信号AとBとを混合
比の和が1となるよう混合比制御信号Cで制御さ
れた混合信号とすればよい。ここで使用する絶対
値回路は一般によく知られているもので、加算器
とExclusiue−OR回路1組で構成されるものか、
またはALU3と同様なもので減算値と被減算値
とを逆にしA−BとB−Aの両方を行ない、正の
結果を得られる方を選択するといつた方法などが
ある。
In this embodiment, both digital input signals A and B are supplied to an absolute value circuit 1, which outputs a positive and negative polarity signal at the same time as a difference absolute value signal |A-B|. The absolute value signal |A-B| is guided to one input of the multiplier 2, and the mixing ratio control signal C is supplied to the other input. Multiplier 2 multiplies these two positive numbers, rounds them to an appropriate bit length, and then
The product signal |A−B|×C is led to one input of ALU3. Further, the digital input signal B is supplied to the other input of the ALU 3. For example, ALU3 is
Addition and subtraction can be switched by a switching signal such as SN74S381, and this switching is performed by the positive and negative polarity signals generated when obtaining the absolute value signal |A-B| of the difference in the above-mentioned absolute value circuit 1. . This operation is based on the magnitude relationship of the digital input signals. If A is greater than B, addition is performed as B+|A-B|×C, and if A is smaller than B, B-|A-B|×C.
It performs subtraction. The output signal D of the ALU 3 may be a mixed signal in which the input digital signals A and B are controlled by the mixing ratio control signal C so that the sum of the mixing ratios becomes 1. The absolute value circuit used here is a generally well-known one, consisting of an adder and an Exclusiue-OR circuit, or
Alternatively, there is a method similar to ALU3 in which the subtracted value and the subtracted value are reversed, both A-B and B-A are performed, and the one that yields a positive result is selected.

また実際には、処理速度の関係で各処理ブロツ
クをレジスタではさみ、パイプライン式とするよ
うにしてもよい。
Furthermore, in practice, each processing block may be sandwiched between registers to provide a pipeline system for reasons of processing speed.

以上説明したように本発明によれば正数だけ扱
かえばよい乗算器を1つ備え、従来と同等の混合
処理が行なうことが可能となる。また前述したよ
うに絶対値回路や加減算の切換えを行なう回路が
必要となるが、いずれもALUで簡単に処理でき
符号付き乗算器を不要としただけ回路構成が簡単
になり、有効である。
As explained above, according to the present invention, one multiplier that only needs to handle positive numbers is provided, and it is possible to perform mixing processing equivalent to the conventional one. Also, as mentioned above, an absolute value circuit and a circuit for switching between addition and subtraction are required, but both can be easily processed by the ALU, and the circuit configuration is simple and effective as the signed multiplier is not required.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例によるデイジタル混合回
路のブロツク図である。 1……絶対値回路、2……乗算器、3……
ALU。
The figure is a block diagram of a digital mixing circuit according to one embodiment of the present invention. 1... Absolute value circuit, 2... Multiplier, 3...
ALU.

Claims (1)

【特許請求の範囲】[Claims] 1 自然2進数にパルス符号化変調された2つの
デイジタル入力信号の差の絶対値演算と正負判別
を行なう回路と、前記絶対値信号と混合比制御信
号との乗算を行なう乗算回路と、この乗算回路の
出力信号を前記デイジタル入力信号の一方と加算
あるいは減算するかを、前記正負判別結果により
切換え演算出力する回路を設けたことを特徴とす
るデイジタル混合回路。
1. A circuit that calculates the absolute value of the difference between two digital input signals pulse code modulated into natural binary numbers and determines whether it is positive or negative, a multiplication circuit that multiplies the absolute value signal by a mixing ratio control signal, and this multiplication circuit. 1. A digital mixing circuit comprising: a circuit for switching and outputting a calculation whether to add or subtract an output signal of the circuit from one of the digital input signals, depending on the result of the positive/negative determination.
JP56185018A 1981-11-18 1981-11-18 Digital mixing circuit Granted JPS5886637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56185018A JPS5886637A (en) 1981-11-18 1981-11-18 Digital mixing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56185018A JPS5886637A (en) 1981-11-18 1981-11-18 Digital mixing circuit

Publications (2)

Publication Number Publication Date
JPS5886637A JPS5886637A (en) 1983-05-24
JPS6149715B2 true JPS6149715B2 (en) 1986-10-30

Family

ID=16163324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56185018A Granted JPS5886637A (en) 1981-11-18 1981-11-18 Digital mixing circuit

Country Status (1)

Country Link
JP (1) JPS5886637A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06100961B2 (en) * 1988-04-18 1994-12-12 富士通テン株式会社 Digital signal processor

Also Published As

Publication number Publication date
JPS5886637A (en) 1983-05-24

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