JPS5886637A - Digital mixing circuit - Google Patents

Digital mixing circuit

Info

Publication number
JPS5886637A
JPS5886637A JP56185018A JP18501881A JPS5886637A JP S5886637 A JPS5886637 A JP S5886637A JP 56185018 A JP56185018 A JP 56185018A JP 18501881 A JP18501881 A JP 18501881A JP S5886637 A JPS5886637 A JP S5886637A
Authority
JP
Japan
Prior art keywords
signal
input
circuit
positive
mixing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56185018A
Other languages
Japanese (ja)
Other versions
JPS6149715B2 (en
Inventor
Toshiro Watanabe
渡辺 俊郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56185018A priority Critical patent/JPS5886637A/en
Publication of JPS5886637A publication Critical patent/JPS5886637A/en
Publication of JPS6149715B2 publication Critical patent/JPS6149715B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE:To simplify the constitution of a circuit which performs such mixing control that the sum of mixing rates of input signals is one, by using a code-free multiplying means of handling only one positive number. CONSTITUTION:Digital input signals A and B are both supplied to an absolute value circuit 1, which outputs a positive/negative polarity sigal simultaneously with their absolute-value difference signal¦A-B¦. The absolute-value signal ¦A-B¦is led to one input of a multiplier 2, and a mixing ratio controlling signal C is supplied to the other input. The multiplier 2 multiplies two positive numbers by each other to round the product to an adequate bit length, and then supplies the product signal¦A-B¦XC to one input of an ALU3. A signal B is supplied to the other input of the ALU3. The ALU3 performs arithmetic B+¦A-B¦XC when the signal A is greater than the signal B, or B-¦A- B¦XC when A is less than B.

Description

【発明の詳細な説明】 本発明は自然2進数′にPCM(パルス符号変調)化さ
れた2つのディジタル信号の混合比の和が常に1となる
よう混合制御するディジタル混合回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital mixing circuit that performs mixing control so that the sum of the mixing ratios of two digital signals PCM (pulse code modulated) into natural binary numbers is always 1.

この種の混合制御は次式に示されるものである。This type of mixing control is shown in the following equation.

AxC・+BX(1−C)  (o(Cく1)・・・・
1ココテ^は一方のディジタル入力信号、Bは他方のデ
ィジタル入力信号、Cは混合比制御信号である。単純に
この制御を実現するには式1の第1項と第2項のために
乗算手段′ft2つ備えねばならない。ディジタル乗算
器は専用のLS i′ft必要とするなど複雑となり、
またその単価も高く、使用数を削減することが好ましい
AxC・+BX(1-C) (o(Cku1)...
1 is one digital input signal, B is the other digital input signal, and C is a mixing ratio control signal. To simply implement this control, two multiplication means 'ft must be provided for the first and second terms of Equation 1. Digital multipliers are complicated, such as requiring a dedicated LS i′ft,
In addition, the unit cost is high, so it is preferable to reduce the number of units used.

そこで式1を展開して次式とし、乗算手段を1つにする
方法も考えられる。
Therefore, it is also possible to expand Equation 1 into the following equation and use only one multiplication means.

B+(A−B)xC・・・・・・ 2 これは式2の第2項の演算のために、減算器と乗算器、
更に第1項とs2項との加算用として加算器があればよ
い。しかし第2項括弧内の正負は入力信号A都の如何に
よるもので、前記乗算器は補数扱い(符号付き演算)で
なければならない。このように限定された乗算器を使用
するのは好ましくない。特にビット長が小さくてよい場
合、乗算iP−ROMで代行する手段がよく用いられる
が符号付き演算であるサインビット分1ビットの増加は
無視できない。
B+(A-B)xC...2 This requires a subtracter, a multiplier,
Further, an adder may be provided for adding the first term and the s2 term. However, the sign in the parentheses of the second term depends on the input signal A, and the multiplier must be treated as a complement (signed operation). It is undesirable to use such a limited multiplier. In particular, when the bit length may be small, a multiplier iP-ROM is often used as a substitute, but the increase of one bit by the sign bit, which is a signed operation, cannot be ignored.

本発明は、このような従来の問題を解決し、1−個の符
号なし乗算手段を用い、入力信号の混合比の和が1とな
る混合制御を行なう回路を実現しようとするものである
。以下に本発明について説明する。
The present invention aims to solve such conventional problems and realize a circuit that performs mixing control such that the sum of the mixing ratios of input signals becomes 1 by using 1- unsigned multiplication means. The present invention will be explained below.

前記した式2を更に分解すれば次のようになる。If Equation 2 above is further decomposed, it becomes as follows.

A−13くOならB+ l A−B l xC−−−−
(3−1)A−B(QならB −l A−B l xC
−−−・(a−2)上式で明らかなように、あらかじめ
2つの入力信号A、Hの差の正負判別を行ない。その結
果により(3−1)式と(3−2)式とのいずれかの信
号処理結果を出力すれば、第2項は2つの入力信号の差
の絶対値IA−Blと混合比Cという、いずれも正の信
号同志の乗算となり、符号つき乗算手段を必要としなく
なる。
If A-13kuO, then B+ l A-B l xC----
(3-1) A-B (for Q, B -l A-B l xC
---(a-2) As is clear from the above equation, the difference between the two input signals A and H is determined in advance to be positive or negative. Depending on the result, if the signal processing result of either equation (3-1) or equation (3-2) is output, the second term is the absolute value IA-Bl of the difference between the two input signals and the mixing ratio C. , all result in multiplication of positive signals, eliminating the need for signed multiplication means.

図は本発明を適用した一実施例の構成を示す図であシ、
ディジタル入力信号AとBとを混合比制御信号Cで制御
し、出力信号りを得ようとするものである。
The figure is a diagram showing the configuration of an embodiment to which the present invention is applied.
The digital input signals A and B are controlled by a mixing ratio control signal C to obtain an output signal.

同図において1は絶対値回路、2は乗算器、3はA L
 U (Arithmetic Logic Uni 
ts)である。
In the same figure, 1 is an absolute value circuit, 2 is a multiplier, and 3 is an A L
U (Arithmetic Logic Uni
ts).

この実施例において、ディジタル入力信号AとBとはい
ずれも絶対値回路1に供給され、差の絶対値信号IA−
Blと同時に正負極性信号とを出力する。絶対値信号I
A−Bl−は乗算器2の一方の入力に導かれ、もう一方
の入力には混合比制御信号Cが供給される。乗算器2は
こうした2つの正数同志を乗算し、適当なビット長に丸
めた後、積信号IA−BlxCをALU3の一方の入力
に導く。まfcALU3のもう一方の入力にはディジタ
ル入力信号Bが供給される。ALUaは例えば5N74
8381のような切換信号によシ加減算の切換えを行な
うことができるもので、前記の絶対値回路1で差の絶対
値信号IA−alt求める除虫じた正負極性信号により
、この切換えが行なわれる。この動作はディジタル入力
信号の大小関係でAがBより大なら、B+1A−Blx
Cと加算を行ない、AがBより小ならばB−IA−Bl
xCと減算を行なうものである。このALU3の出力信
号りを前記入力ディジタル信号AとBとを混合比の和が
1となるよう混合比制御信号Cで制御された混合信号と
すればよ込。ここで使用する絶対値回路は一般によく知
られているもので、加算器とEialusiue−OR
回路1組で構成されるものか、またはALUaと同様な
もので減算値と被減算値とを逆にしA−BとB−Aの両
方を行ない、正の結果を得られる方を選択するといった
方法などがある、 また実際には、処理速度の関係で各処理ブロックをレジ
スタではさみ、パイプライン式とするようにしてもよい
In this embodiment, digital input signals A and B are both fed to an absolute value circuit 1, which outputs a difference absolute value signal IA-
It outputs positive and negative polarity signals at the same time as Bl. Absolute value signal I
A-Bl- is led to one input of the multiplier 2, and the other input is supplied with the mixing ratio control signal C. The multiplier 2 multiplies these two positive numbers together, rounds them to an appropriate bit length, and then guides the product signal IA-BlxC to one input of the ALU 3. Digital input signal B is supplied to the other input of fcALU3. For example, ALUa is 5N74
It is possible to switch between addition and subtraction by a switching signal such as 8381, and this switching is performed by the positive and negative polarity signals obtained by the absolute value signal IA-alt of the difference in the absolute value circuit 1. . This operation is based on the magnitude relationship of the digital input signal, and if A is greater than B, then B+1A-Blx
Perform addition with C, and if A is less than B, then B-IA-Bl
It performs subtraction with xC. The output signal of the ALU 3 is a mixed signal obtained by controlling the input digital signals A and B with the mixing ratio control signal C so that the sum of the mixing ratios becomes 1. The absolute value circuit used here is generally well known, and includes an adder and an Eialusiue-OR circuit.
Either it is composed of one set of circuits, or it is similar to ALUa, and the subtracted value and the subtracted value are reversed, and both A-B and B-A are performed, and the one that yields a positive result is selected. There are many ways to do this, and in practice, for reasons of processing speed, each processing block may be sandwiched between registers to create a pipeline system.

以上説明したように本発明によれば正数だけ扱かえばよ
い乗算器を1つ備え、従来と同等の混合処理が行なうこ
とが可能となる。また前述したように絶対値回路や加減
算の切換えを行なう回路が必要となるが、いずれもAL
Uで簡単に処理でき符号付き乗算器を不要としただけ回
路構成が簡単になり、有効である。
As explained above, according to the present invention, one multiplier that only needs to handle positive numbers is provided, and it is possible to perform mixing processing equivalent to the conventional one. Also, as mentioned above, an absolute value circuit and a circuit for switching between addition and subtraction are required, but both are AL
It is effective because it can be easily processed by U, and the circuit configuration is simplified to the extent that a signed multiplier is not required.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例によるディジタル混合回路のブロ
ック図である。 1・・・・・絶対値回路、2・・・・・乗算器、3・・
・・A−LU。
The figure is a block diagram of a digital mixing circuit according to an embodiment of the present invention. 1... Absolute value circuit, 2... Multiplier, 3...
...A-LU.

Claims (1)

【特許請求の範囲】[Claims] 自然2進数にパルス符号化変調された2つのディジタル
入力信号の差の絶対値演算と正負判別を行なう回路と、
前記絶対値信号と混合比制御信号との乗算を行なう乗算
回路と、この乗算−回路の出力信号を前記ディジタル入
力信号の一方と加算あるいは減算するかを、前記正負判
別結果により切換え演算出力する回路を設けたことを特
徴とするディジタル混合回路。
a circuit that calculates the absolute value of the difference between two digital input signals pulse code modulated into natural binary numbers and determines whether the signal is positive or negative;
a multiplication circuit that multiplies the absolute value signal and the mixing ratio control signal; and a circuit that outputs a calculation that switches whether to add or subtract the output signal of the multiplication circuit from one of the digital input signals, depending on the result of the positive/negative determination. A digital mixing circuit characterized by being provided with.
JP56185018A 1981-11-18 1981-11-18 Digital mixing circuit Granted JPS5886637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56185018A JPS5886637A (en) 1981-11-18 1981-11-18 Digital mixing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56185018A JPS5886637A (en) 1981-11-18 1981-11-18 Digital mixing circuit

Publications (2)

Publication Number Publication Date
JPS5886637A true JPS5886637A (en) 1983-05-24
JPS6149715B2 JPS6149715B2 (en) 1986-10-30

Family

ID=16163324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56185018A Granted JPS5886637A (en) 1981-11-18 1981-11-18 Digital mixing circuit

Country Status (1)

Country Link
JP (1) JPS5886637A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148161A (en) * 1988-04-18 1992-09-15 Fujitsu Ten Limited Digital signal processor for fixed and floating point data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148161A (en) * 1988-04-18 1992-09-15 Fujitsu Ten Limited Digital signal processor for fixed and floating point data

Also Published As

Publication number Publication date
JPS6149715B2 (en) 1986-10-30

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