JPH0962489A - Multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the multiplier which can easily cope with an increase in the number of bits and is made small-sized. SOLUTION: As for two numbers X and Y which are inputted, an adder 1 calculates X+Y, a switch 2 outputs X and Y, and X+Y in this order, and a square calculator 3 squares the numeral inputted from the switch 2; and a polarity controller 4 changes the sign of the square of the X into a minus, the square of the Y into a minus, and the square of the (X+Y) into a plus, an adder 5 totalizes the values inputted from the polarity controller 4 and stores the result in a register 6, and a divider 7 divides the result stored in the register 6 by 2 to find the product of the X and Y.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose multiplier used in digital equipment, and more particularly, it can easily cope with an increase in the number of bits of a number to be multiplied (multiplicand) and is small in size. And a multiplier that can be configured as follows.

[0002]

2. Description of the Related Art A conventional multiplier will be described with reference to FIG. FIG. 2 is a configuration block diagram of a conventional multiplier.
As shown in FIG. 2, the conventional multiplier is composed of a plurality of shift registers 8a to 8n, a switch 9 having a plurality of switches 9a to 9n, and a plurality of adders 10a to 10n.

The function of each part will be specifically described. The shift register 8 shifts the input bit string of the numerical value (X) to the left (multiplies 2 to the nth power). A plurality of shift registers 8 are prepared, one that does not shift (multiply by 2 to the power of 0) (8a), one that performs one left shift (multiply by 2 to the power of 1) (8b), and 2 For example, the left shift is performed twice (2 to the power of 2) (8c), the left shift is performed i times (the input 2 to the power of 2 is calculated). i is any number between 0 and the number of bits involved in the multiplication. For example, when the maximum limit of the number obtained as a result of multiplication is “9999”, the binary representation of this is “100111000011.
Since "11" is 14 bits, i becomes 0 to 14.

All of the switches 9 are initially in the open state. Depending on the bit of the numerical value (Y) related to multiplication, if the bit is set, the corresponding switch is closed, and if the bit is not set, the corresponding switch is set. It leaves the switch to open. For example, when the numerical value (Y) is “5”,
Since the binary number representation of "5" is "101", the switch (9a) corresponding to the power of 2 and the switch (9c) corresponding to the power of 2 are closed and the remaining switches are opened. Leave. Then, the adder 10 calculates and outputs the sum of the two input numbers.

Next, the operation of the conventional multiplier will be described by giving an example of calculating the product of "7" and "5". The binary expression of "7" is "111", and the binary expression of "5" is "101". First, "7" as X
Is input, the shift register 8 shifts 8a to “11.
1 ”, 8b is“ 1110 ”, 8c is“ 11100 ”
Is output to the switch 9. In the switch 9, the switches 9a and 9c are closed and the switch 9b is left open, corresponding to "101" of Y "5".

Since the switch 9b is open, the adder 10b does not add the contents of the shift register 8b and inputs "111" through the switch 9a.
Is output to the adder 10c as it is. And adder 1
0c adds "111" output from the adder 10b and "11100" output via the switch 9c, and outputs "100011". This corresponds to "35" in decimal notation. Then, the conventional multiplier is designed to output "35" which is the product of "7" and "5".

[0007]

However, in the conventional multiplier described above, when the number of calculations becomes large and the number of bits increases, it is necessary to add a shift register, a switch, and an adder, respectively. However, there is a problem in that it cannot be easily dealt with and the size cannot be reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multiplier which can easily cope with an increase in the number of bits and can be constructed in a small size.

[0009]

The invention according to claim 1 for solving the above-mentioned problems of the conventional example is a first adder for calculating the sum of two numbers to be multiplied, and the two multiplications. A number that is output in the order of the sum of the two multiplied numbers, a square calculator that squares and outputs the numerical value input from the switch, and an input from the square calculator. The sign of the numerical value is converted into "negative", "negative", "positive" in the input order and output, and the numerical value input from the polarity controller is added and output. Of the second adder, a register for storing the value input from the second adder, and a divider for dividing the value stored in the register by 2 and outputting the divided value. Even if the number of bits increases and the number of bits increases, the square calculator By changing only volume, without increasing the number of parts, easily can handle, and,
Can be made compact.

[0010]

Embodiments of the present invention will be described with reference to the drawings. Multiplier according to the present invention (this multiplier)
Takes advantage of the fact that the square of (X + Y) is the sum of twice the product of X squared, Y squared, and X and Y, (X + Y)
By subtracting the square of X from the square of X and the square of Y and then dividing by 2 to obtain the product of X and Y, it is possible to easily cope with an increase in the number of bits, and It can be miniaturized.

This device will be described with reference to FIG. FIG.
FIG. 3 is a configuration block diagram of a multiplier according to the present invention. This multiplier includes a first adder 1 and a switch 2 as shown in FIG.
, The square calculator 3, the polarity controller 4, and the second adder 5
And a register 6 and a divider 7.

Next, each part will be described in detail. The first adder 1 switches the sum of the two numbers (X and Y) input to the switch 2
Is output to The switching device 2 receives the input X and Y
And the sum thereof are output to the square calculator 3 in that order. The square calculator 3 calculates in advance and R
With reference to the numerical value stored in the OM, the squared value of the input numerical value is output to the polarity controller 4. The polarity controller 4 inputs the signs of the input numerical values in the order of input,
It is changed in the order of negative, negative, positive, and the result is changed to the second adder 5
Is output to The polarity controller 4 outputs a signal to the divider 7 at that time when a numerical value to be changed to a positive sign is input.

The second adder 5 calculates the sum of the input numerical value and the numerical value stored in the register 6, and overwrites and stores it in the register 6. The register 6 is initially initialized to “0” and stores the numerical value input from the second adder 5. And the divider 7
Is a shift register, which waits until a signal is input from the polarity controller 4, and when the signal is input, shifts the bit contents of the register 6 to the right once (by dividing by 2) and outputs the result. Is.

Next, the operation of this multiplier will be described by taking as an example the case where the product of "5" and "7" is calculated. First, when the first adder 1 inputs “5” as X,
The sum “12” with “7” input as Y is output to the switch 2. The switching device 2 sets these as "5", "7", "1".
2 ”is output to the square calculator 3 in this order.

The square calculator 3 refers to the ROM and stores "25" corresponding to "5", "49" corresponding to "7", and "144" corresponding to "12", respectively. Are output to the polarity controller 4 in this order, the polarity controller 4 changes the respective polarities in the order of negative, negative and positive, and
5 ”and“ −49 ”are output to the second adder 5, and“ + ”is output.
144 ”to the second adder 5, and at that time outputs a signal to the divider 7.

Then, the second adder 5 calculates the sum of "0" stored in the register 6 and "-25" and stores "-25" in the register 6. Next, "-49"
And the sum of “−25” stored in the register 6, “−”
74 ”is overwritten and stored in the register 6. Next, the sum of "-74" and "+144", "70", is overwritten and stored in the register 6.

Then, the divider 7 receives the signal from the polarity controller 4, bit-shifts the contents of the register 6 to the right once (divides by 2), and outputs the result "35". . Although the above calculation is represented by a decimal number, this multiplier is actually performed by a binary method using "0" and "1".

According to the present multiplier, when the multiplicand increases, it is sufficient to replace the ROM or the like, and therefore, it is possible to easily cope with the increase in the number of bits and increase the number of parts. Since it does not exist, there is an effect that it can be made compact.

[0019]

According to the present invention, the first adder calculates the sum of two multiplied numbers, and the switcher calculates the sum of two multiplied numbers and the sum of two multiplied numbers. Output in this order,
The square calculator squares and outputs the numerical value input from the switching device, and the polarity controller outputs the sign of the numerical value input from the square calculator in the order of input, "negative""negative"" The value is converted to "positive" and output, the second adder adds and outputs the value input from the polarity controller, the register stores the value input from the second adder, and the divider enters the register. Since it is a multiplier that divides the value stored in 2 by 2 and outputs it, even if the number to be multiplied increases and the number of bits increases, only the contents of the squaring calculator will remain unchanged without changing the overall configuration. By changing the number, there is an effect that the number of parts can be easily increased and the size can be reduced without increasing the number of parts.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a multiplier according to the present invention.

FIG. 2 is a configuration block diagram of a conventional multiplier.

[Explanation of symbols]

1, 5, 10 ... Adder, 2 ... Switcher, 3 ... Square calculator, 4 ... Polarity controller, 6 ... Register, 7 ... Divider, 8 ... Shift register, 9 ... Switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenzo Urabe 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Co., Ltd.

Claims (1)

[Claims] 1. A first adder for calculating the sum of two multiplied numbers, a switch for outputting the two multiplied numbers, and a switch for outputting the sum of the two multiplied numbers in order. The square calculator that squares and outputs the numerical value input from the switching device, and the sign of the numerical value input from the square calculator are “negative”, “negative”, and “positive” in the input order. A polarity controller for converting and outputting, a second adder for adding and outputting the numerical values input from the polarity controller, a register for storing the value input from the second adder, and And a divider that divides the value stored in the register by 2 and outputs the divided value.