JPS57150217A - Digital signal processing circuit - Google Patents
Digital signal processing circuitInfo
- Publication number
- JPS57150217A JPS57150217A JP56035571A JP3557181A JPS57150217A JP S57150217 A JPS57150217 A JP S57150217A JP 56035571 A JP56035571 A JP 56035571A JP 3557181 A JP3557181 A JP 3557181A JP S57150217 A JPS57150217 A JP S57150217A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- holding circuit
- signal
- digital signal
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To simplify the constitution, by processing an input digital signal by dividing it into plural bit sequence parts whose number of bits is less than the number of bits of a multiplier. CONSTITUTION:Hihg-order 8 bits of an input digital signal Xn consisting of 16 bits are held by a holding circuit 14, and are applied to a multiplier and adder 17 as they are. Also, low-order 8 bits are held by a holding circuit 15, and 7 bits except LSB among them are applied to a signal processor 16. In the signal processor 16, in addition to 7 bits from the holding circuit 15, ''0'' is inserted as MSB, they are converted to a signal of total 8 bits, and are applied to the multiplier and adde 17. The multiplier and adder 17 multiplies and adds the signals from the holding circuit and the signal processor 16, and a coefficient from a coefficient device 18, respectively and its results are held by holding circuits 19, 20, respectively. An output signal of the holding circuit 20 is shifted to the right by 7 bits by a signal processor 21, and after that is added with an output signal of the holding circuit 19 by an adder 22, and is outputted from an output terminal 23 as an output digital signal yn displayed by two's complement.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56035571A JPS57150217A (en) | 1981-03-12 | 1981-03-12 | Digital signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56035571A JPS57150217A (en) | 1981-03-12 | 1981-03-12 | Digital signal processing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57150217A true JPS57150217A (en) | 1982-09-17 |
JPS6363130B2 JPS6363130B2 (en) | 1988-12-06 |
Family
ID=12445437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56035571A Granted JPS57150217A (en) | 1981-03-12 | 1981-03-12 | Digital signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57150217A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03242247A (en) * | 1990-02-16 | 1991-10-29 | Matsushita Seiko Co Ltd | Air cleaner |
JPH0551459U (en) * | 1991-12-13 | 1993-07-09 | 日栄電機産業株式会社 | Electrostatic air purifier |
-
1981
- 1981-03-12 JP JP56035571A patent/JPS57150217A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6363130B2 (en) | 1988-12-06 |
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