JPS6363130B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal processing circuit that is expressed in complement representation and has a multiplier with a smaller number of bits than the input digital signal for a digital signal with a large number of bits. It is an object of the present invention to provide a digital signal processing circuit that can perform calculations in a very short time with a simple circuit configuration and few calculation errors using a filter.

FIG. 1 shows a block diagram of an example of a conventional digital signal processing circuit used for imparting predetermined frequency characteristics to a digital signal in a digital signal recording and reproducing system. In the figure, reference numeral 1 denotes an input terminal, through which a digital pulse-modulated digital signal (for example, a pulse code modulated signal) is applied to a modulator 2. The modulator 2 is configured such that the input digital signal is e.g.
When expressed in complement representation, the circuit converts this into a BCD code for reasons to be described later, and the output signal is held in a holding circuit 3 and then applied to a multiplier 4. On the other hand, 5 is a coefficient unit in which required coefficients are stored in advance, and the stored coefficients are read out as needed. This coefficient is, for example, a binary signal expressed in two's complement representation, and is converted into a BCD code by a converter 6 in the same way as converter 2, and is applied to a multiplier 4, where it is multiplied by the signal from the holding circuit 3. be done.

The multiplier 4 is normally configured with a number m of bits which is smaller than the number of bits of the input digital signal (this is referred to as n). In the case of
The result of multiplying the bits by the coefficient is applied to the adder 9 via the holding circuit 7, and the result of multiplying the lower m bits and the coefficient obtained after that is applied to the adder 9 via the holding circuit 8. The signal added by adder 9 is held in holding circuit 10 and then applied to adder 9, and also fed back to holding circuit 3. Furthermore, the output signal of this holding circuit 10 is supplied to a converter 11, where the BCD code is converted into two's complement representation and taken out from an output terminal 12.

In this way, in the conventional digital signal processing circuit configured with a cyclic digital filter, when the number m of bits of the multiplier 4 is smaller than the number of bits of the input signal or coefficient, multiplication is performed by dividing. . On the other hand, since there are many advantages to handling digital signals in two's complement representation, they are usually represented in two's complement representation. However, when the multiplier 4 performs the above division multiplication process on a two's complement signal, a correct multiplication result cannot be obtained if the input signal is negative or the coefficient is negative. For example, if the input signal is 8 bits and is expressed as ``0.101 1101'', and the coefficient is 4 bits and is expressed in two's complement notation as ``1.010'', the correct multiplication result is ``11.01 1101 0010'', but the multiplication Assuming that the circuit 4 has 4 bits, if the above division multiplication process is performed on the upper 4 bits of the input signal "0.101" and the lower 4 bits "1101", we get This results in a completely different result from the correct multiplication result.
In two's complement representation, the MSB represents the polarity, but the MSB of the lower 4 bits "1101" is "1".
This is because it will be multiplied as a negative number.

For this reason, in conventional digital signal processing circuits, as shown in FIG. The final output was obtained by converting the signal from a BCD code to two's complement representation using a converter 11.
For this reason, conventional digital signal processing circuits have disadvantages in that the circuit configuration is complicated, the calculation processing time is long, and calculation errors are likely to occur.

The present invention eliminates the above-mentioned drawbacks,
Each embodiment will be described below with reference to FIGS. 2 and 3.

FIG. 2 shows a block system diagram of a first embodiment of the digital signal processing circuit according to the present invention. In the same figure,
13 is an input terminal into which a digital signal subjected to digital pulse modulation is input. This input digital signal is displayed in two's complement representation, but the time
It is assumed that the digital signal x _o at nT (T is the sampling period of the digital signal) is expressed as "0.010 1101 0101 0110" in 16 bits, for example. Furthermore, assuming that the coefficients from the coefficient multiplier 18 (described later ₎ are 8 bits, the input digital signal x _o has more bits than the coefficients, so the bit sequence of the input digital signal 8, which is smaller than 16 bits, which is the number of bits in adder 17
Since this 16-bit input digital signal _xo is divided into two bit series parts, its upper 8 bits "0.010 1101" are held in the holding circuit 14, and its lower 8 bits "0101 0110" are held. It is held in the circuit 15. The holding circuit 14 applies the input 8-bit signal "0.010 1101" as it is to the multiplier and adder 17.

On the other hand, the holding circuit 15 outputs the remaining 7 bits excluding the LSB (least significant bit) out of the input 8-bit signal "0101 0110" and applies the output to the signal processor 16. Signal processor 1
6 inserts "0" as the MSB (Most Significant Bit) in the bit above the most significant bit of the 7-bit signal from the holding circuit 15, converting it into a total of 8-bit signal "0010 1011". is applied to the multiplier and adder 17. That is, the holding circuit 15 and the signal processor 16 add "0" as the MSB to the lower 8 bits of the input digital signal _xo .
is added, and this 9-bit signal is shifted to the right by 1 bit, with the least significant bit being discarded, resulting in a total of 8-bit signals.

The multiplier/adder 17 multiplies the 8-bit signal from the holding circuit 14 by, for example, an 8-bit coefficient expressed in two's complement from the coefficient unit 18, and then adds the results of each multiplication. Then, the addition output p _o is held in the holding circuit 19, and then the 8-bit signal from the signal processor ₁₆ (the lower 7 bits of the input digital signal ”) is multiplied by the coefficient from the coefficient unit 18, and then each multiplication result is added up and the added output q _o is held by the circuit 2.
Hold it at 0.

The output signal of the holding circuit 20 is applied to a signal processor 21, where it is shifted to the right by 7 bits, and then applied to an adder 22, where it is added to the output signal of the holding circuit 19. The output signal of the adder 22 is output from the output terminal 23 as an output digital signal expressed in two's complement representation, and is fed back to the holding circuit 14.

As described above, according to this embodiment, the difference equation formed by the cyclic digital filter is expressed by the following equation, for example.

y _o = a ₀ x _o + a ₁ x _o-1 −b ₁ y _o-1 However, in the above equation, x _o-1 is the input digital signal sequence at time (n-1) T, and x _o-1 = x _o . In addition, y _{o and} y _o-1 are output digital signal sequences at times nT and (n-1)T, and as an example, x _o =
Let y _o-1 . Further, a ₀ , a ₁ , and b ₁ indicate 8-bit coefficients stored in the coefficient unit 18 in advance. here,
Coefficient a ₀ is “0.001 1111”, a ₁ is “1.110 0001”, −b ₁
is "0.001 1101".

As a result, to specifically explain the calculation results in the multiplier and adder 17, first, the coefficient a ₀ is multiplied by the upper 8 bits x _o ^H of the input digital signal x _o ,
Next, the coefficient a ₁ is multiplied by the high-order 8 bits of x _o-1, x _o-1 ^H , and then the coefficient -b ₁ is multiplied by the high-order 8 bits of y _o-1 , y _o-1 ^H , and each multiplication The results are added together and the signal p _o
and is held in the holding circuit 19. That is, Next, the coefficient from the coefficient unit 18 and the signal from the signal processor 16 are multiplied. That is, first, the lower 7 bits of coefficients a ₀ and x _o are set to "0" as the MSB.
is multiplied by the added signal x _o ^L , and then the coefficient a ₁
is multiplied by the signal x _o-1 ^L in which "0" is added as the MSB to the lower 7 bits of x _o-1 , and then the coefficient -b ₁
is multiplied by a signal y _o -1 ^L in which “0” is added as the MSB to the lower 7 bits of y _o-1 , and these multiplication results are added to form a signal q _o , which is sent to the holding circuit 20.
is maintained. That is, becomes. Since the output signal _qo of the holding circuit 20 is shifted to the right by 7 bits by the signal processor 21, the output digital signal _yo of the adder 22 is as follows.

As mentioned above, the output digital signal y _o expressed in two's complement notation is correct even though the multiplier and adder 17 multiplies the input signal expressed in two's complement notation by the coefficient. Get results. This is due to the following reason. In other words, when the lower bit series x _o ^L of the input digital signal x _o is multiplied by a coefficient, the MSB of the lower bit series x _o ^L becomes "1" or "0" depending on the value of the input digital signal x _o .
However, in two's complement representation, the MSB represents the polarity (sign), so when the MSB of x _o ^L is "1", it represents a negative number in decimal notation, so by the above multiplication, the above As you can see, a result that is completely different from the correct multiplication result is obtained. However, in this embodiment, the MSB of the lower bit series x _o ^L is always "0".
Therefore, even if signals expressed in two's complement representation are multiplied together, a correct multiplication result can be obtained.

Therefore, according to this embodiment, the converter 2,
6, 11 are unnecessary, while signal processors 16,
Since the operation of 21 only involves adding "0" to the MSB and performing bit shifting, the calculation time can be significantly shortened compared to conventional circuits, and the circuit configuration can also be simplified.

Next, a second embodiment of the circuit according to the present invention will be described. FIG. 3 shows a block system diagram of the second embodiment of the digital signal processing circuit according to the present invention. In the figure, the same components as in Figure 2 are given the same numbers.
The explanation will be omitted. In FIG. 3, multiplier 2
4 is the input digital signal from the holding circuit 14.
High order bit sequence of x _{o H} and coefficient from ^coefficient unit 18
Multiplying with a ₀ is performed, and the holding circuit 19 holds the multiplication result a ₀ x _o ^H. Next, the signal x _o L obtained by adding "0 ^" as the MSB to the lower bit series of x _o from the signal processor 16 is multiplied by a coefficient a ₀ , and the multiplication result a ₀ x _o ^L is held by the circuit 20. hold it.
Thereafter, the adder 25 adds the signal _a0xoH from the holding circuit 19 and ^the _{signal a0xoL} shifted to the right by a predetermined number of bits by the ^signal processor ₂₁ , and the addition result _{is a0xoH} ^. +a ₀ x _o ^L is held in the holding circuit 26 while being fed back to the adder 25 .

Next, as a result of the multiplication by the multiplier 24, the holding circuit 19 holds the multiplication result a ₁ x _o-1 ^H , and the holding circuit 20 holds the multiplication result a ₁ x _o-1 ^L , in the same way as above. Retained. Then, by the adder 25, (a ₁ x _o-1 ^H
+a ₁ x _o-1 ^L ) and (a ₀ x _o ^H +a ₀ x _o ^L ) are added. After that, in the same manner as above, the adder 25
Then, the addition result up to now and (-b ₁ y _o-1 ^H -b ₁ y _o-1 ^L ) are added, and the output digital signal y defined by the difference equation is obtained as in the first embodiment. _o is obtained, and this output digital signal y _o is fed back to the input side of the holding diodes 14 and 15, and is output from the output terminal 23.

In the case of this embodiment as well, similarly to the first embodiment,
The signal processor 16 shifts the lower bit series of the input digital signal _xo to the right by 1 bit and adds "0" to its MSB, and the signal processor 21 shifts the lower bit series to match the upper bit series. Since bit shifting is performed, input digital signals expressed in two's complement representation can be processed as they are without converting them into BCD codes or the like. Therefore, calculation time can be significantly reduced.

In the first and second embodiments described above, the signal processor 16 discards 1 bit of the LSB of the input digital signal x _o , so an error of only 1/2 LSB occurs, but for example, if the input digital signal x _o In the case of 16 bits, there is no problem if the calculation signal output of the multipliers 17 and 24 is made larger, for example, 32 bits.

Furthermore, in the digital signal processing circuit shown in FIG. 2 or 3, which is configured with a first-order cyclic digital filter shown by the above-mentioned difference equation, the coefficient a ₀ is 0.23944732, a ₁ is -0.24288672, and b ₁ is -
0.22916992 (the coefficients a ₀ , a ₁ , b ₁ are actually digital signals expressed in two's complement representation, but here they are shown as values converted to decimal numbers), the obtained amplitude frequency characteristic is a turn over frequency 61
It shows a type of high-pass filter characteristic that shows an increasing characteristic from Hz to a roll-off frequency of 100Hz. In this way, by selecting the coefficients a ₀ , a ₁ , and b ₁ , desired amplitude-frequency characteristics can be obtained.

In each of the above embodiments, it has been explained that the input digital signal is processed by the signal processors 16 and 21, but it is also possible to adjust the quantization on the coefficient side in advance and use a plurality of holding circuits in the same way as for the input digital signal. A similar effect can be obtained even if the division process is performed using the same method. Furthermore, in each embodiment, a cyclic digital filter is used, and the order of the filter is set to be 1st order as seen from the above-mentioned difference equation, but it may be set to 2nd order or higher. Furthermore, since it is composed of a digital filter, it does not have to be a cyclic type, and may be a non-cyclic type by removing the feedback loop. Also, bit shifting is performed by the signal processor 16, but the number of bit shifts may be 2 bits or more (however, it is necessary to always add "0" as the MSB). Furthermore, since the present invention can be applied as long as the MSB is a binary representation representing polarity, a one's complement representation or other representation may be used.

Furthermore, if the number of bits of the input digital signal is extremely large compared to the number of bits of the multiplier, the bit sequence of the digital signal is divided into three or more, but in this case as well, a converter should be used in the same manner as above. (Note that the number of bits in each divided bit sequence is less than that of the multiplier).

As described above, the digital signal processing circuit according to the present invention divides the bit sequence of the input digital signal and coefficient, whichever has a larger number of bits, into a plurality of bit sequence parts each having a number of bits less than or equal to the number of bits of the multiplier. The most significant bit sequence part of the divided parts is multiplied by the above multiplier and then sequentially added, and the lower bit part of the divided parts is added with "0" as the MSB. ,
means for shifting each bit or more to the right, sequentially multiplying by a multiplier, and then sequentially adding;
After each addition output of the multiplication result of the bit sequence part with "0" added as MSB is shifted to the right by a predetermined number of bits, the addition output of the multiplication result of the most significant bit sequence part by the multiplier and each adder (or means for shifting each multiplication result of the bit sequence portion to which "0" is added as the MSB to the right by a predetermined number of bits and applying it to an adder; The adder (or means for holding the output signal of this adder and adding the output signal to the above-mentioned most significant bit sequence part multiplied by the coefficient of the same value from the coefficient unit). Since the configuration is configured to output the signal from the output holding circuit (which feeds back to the device) as an output digital signal, the digital signal displayed in a binary display format (for example, two's complement display) where the MSB indicates the polarity can be displayed in that format. Therefore, it is possible to eliminate the need for a converter between two's complement representation and BCD code as in conventional circuits, and at the same time, the shift to the right by more than 1 bit and the shift to the right by a predetermined number of bits are both possible. Since it can be configured by simply changing the wiring of the input of the multiplier and the output of the output holder,
Compared to conventional circuits, the circuit configuration is simpler and easier, and because it does not require a converter, calculation time can be significantly reduced compared to conventional circuits, and the occurrence of calculation errors can be significantly reduced. It has a number of features.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing an example of a conventional circuit, and FIGS. 2 and 3 are block system diagrams showing respective embodiments of the circuit of the present invention. 1, 13...Digital signal input terminal, 4, 2
4... Multiplier, 5, 18... Coefficient unit, 9, 22,
25... Adder, 12, 23... Digital signal output terminal, 16, 21... Signal processor, 17...
Multipliers and adders.

Claims (1)

[Claims] 1. A digital signal that has been digitally pulse modulated and is displayed in a binary format in which the MSB indicates the polarity is supplied, and a plurality of predetermined coefficients from a coefficient multiplier are applied to the digital signal. In a digital signal processing circuit composed of a digital filter using multipliers that perform sequential multiplication, a multiplier having an addition function is used as the multiplier, and the input digital signal and the coefficient, whichever has a larger number of bits, are processed. A means for dividing a bit sequence into a plurality of bit sequence parts each having a number of bits less than or equal to the number of bits of the multiplier, and a means for dividing the bit sequence into a plurality of bit sequence parts each having a number of bits less than or equal to the number of bits of the multiplier, and sequentially adding the most significant bit sequence part of the divided parts after being multiplied by the multiplier as is. means for adding "0" to the lower bit sequence part of the divided bits as MSB, shifting each bit to the right by one or more bits, sequentially multiplying them by a multiplier, and then sequentially adding them; After each addition output of the multiplication result of the bit sequence part to which "0" is added as MSB is shifted to the right by a predetermined number of bits, it is added to the addition output of the multiplication result of the most significant bit sequence part by the multiplier. 1. A digital signal processing circuit comprising means for sequentially adding signals in an adder, and configured to output a signal from the adder as an output digital signal. 2. A multiplier that is supplied with a digital signal that has been digitally pulse modulated and is displayed in a binary format in which the MSB indicates the polarity, and that sequentially multiplies the digital signal by a plurality of predetermined coefficients from a coefficient multiplier. In the digital signal processing circuit configured with the used digital filter, the bit sequence of the signal with a larger number of bits among the input digital signal and the coefficient is converted into a plurality of bit sequence parts having a number of bits less than or equal to the number of bits of the multiplier. means for dividing the most significant bit sequence part into the multiplier, and sequentially adding the bit sequence part on the lower side of the divided part as MSB. means for shifting each multiplication result by one or more bits to the right after adding ", respectively, and multiplying by a multiplier; and means for shifting each multiplication result to the right by a predetermined number of bits and then applying it to the adder;
The adder is a means for adding at least the most significant bit sequence part multiplied by a coefficient of the same value from the coefficient unit in the multiplier, and holds the output signal of the adder and also outputs the output signal. A digital signal processing circuit characterized in that it is configured to output an output digital signal from an output holding circuit that feeds back a signal to the adder.