JP3008842B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital roll-off filter used in a digital radio communication system, and more particularly to a QPSK (Quadrature Phase).
The present invention relates to a digital roll-off filter used for a Shift Keying (Shift Keying) modulator.

[0002]

2. Description of the Related Art In a digital microwave communication system, a filter (roll-off filter) for waveform shaping is required for each of a modulator and a demodulator. With the progress, digital filters that perform filtering by digital signal processing on the baseband time axis have been put into practical use, and those that have no problems such as characteristic variations, aging, and temperature changes have been realized. .

A digital filter includes an IIR (Infi)
Nite Impulse Response) type and F
IR (Finite Impulse Responses)
There are two types of e) type, but in the digital microwave communication system, an FIR type capable of realizing a linear phase is used.

[0004] This conventional system will be described with reference to the drawings.

FIG. 9 is a block diagram of one channel of a transmission-side roll-off filter for QPSK constituted by a conventional FIR type digital filter.

One line of transmission data is input from a terminal 81 and is provided with a shift register 15 comprising a plurality of D clip crops.
It flows in one. The output of each register is input to taps (multipliers) 411 to 416 and multiplied by tap coefficients. The outputs of the taps (multipliers) 411 to 416 are input to the adder 311 and the outputs of all taps (multipliers) are added and output. At this time, the sampling value of the impulse response corresponding to the frequency characteristic of the digital filter is the tap coefficient Cj of each tap (multiplier) (j is (2N +
1) In the case of tap, -N to an integer from N). Assuming that the data inside the shift register is ak-j, the output bk of the digital filter is

[0007]

(Equation 1)

Thus, a frequency characteristic corresponding to the discrete Fourier transform of the tap coefficient Cj is given. If the number of taps is increased indefinitely, an arbitrary frequency characteristic can be realized.

[0009]

However, when steep frequency characteristics are to be realized by a conventional FIR digital filter, the convergence of the impulse response is poor, that is, Cj becomes so small as to be negligible. Is very large and requires many taps. For example, FIG.
Are respectively shown in FIG. 1.
0 and a circuit as shown in FIG. That is,
Since the multiplier of FIG. 10 is a multiplication of 1 × n bits, it can be realized by simple logic gates 561 to 563. However, since the adder shown in FIG. 11 is configured by combining two input full adders (the number of taps-1), there is a disadvantage that the circuit scale becomes large if the number of taps is large. .

As a countermeasure against this, a method in which the FIR digital filter is constituted by a ROM has been conventionally performed.
All the data ak-j in the shift register are made to correspond to the address of the ROM, the output bk of the digital filter corresponding to the input signal is calculated in advance, and the value is calculated as R
By inputting OM data, one ROM can be used for FIR
Type digital filter. However, this method is limited by the operating speed of ROM and the number of address bits.
There is a drawback that the modulation speed is relatively low and the band-limit is not so strict, and it can be applied only to a modulator having a roll-off rate of about 0.4.

An object of the present invention is to provide a digital filter capable of coping with a low roll-off rate and a high modulation speed by reducing the circuit scale of an FIR digital filter constituted by hardware.

[0012]

In order to solve the above-mentioned problems, a digital filter according to the present invention includes a shift register for inputting a digital signal of one column, and a symmetrical structure with respect to the center of each output of the shift register. Two outputs and a tap coefficient corresponding to the two outputs are input, respectively. If the two outputs have the same sign, the tap coefficients corresponding to the two outputs have the same sign as the two outputs. Is selected and output. If the signs of the two outputs do not match,
There is a selecting means for outputting a logical value "0", and an adding means for adding each output of the selecting means.

Further, the digital filter has an adding means for adding an output at the center of the shift register to each output of the selecting means when the number of stages of the shift register is an odd number.

Further, the selection means includes a plurality of exclusive OR circuits each having one input as each bit of the tap coefficient and the other input as a code output of the two outputs, A plurality of AND circuits, each of which is an output of a plurality of exclusive OR circuits and the other input is an exclusive OR output of the two outputs, wherein the adding means adds each output of the selecting means The full adder has a carry input terminal to which an output indicating the sign of the two outputs of the selecting means is input.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 1 shows a configuration example of a digital filter using even-numbered taps. FIG. 1 shows a block diagram in the case of four taps. FIG. 2 is a block diagram showing a second embodiment of the present invention, and shows an example of an odd tap, but is a block diagram when there are five taps.
FIG. 3 is a block diagram of a product-sum circuit used in each block of FIGS.

First, the configuration of the first embodiment shown in FIG. 1 will be described. One column of digital signals input from the terminal 11 is input to a 4-bit shift register 101 driven by a clock at a sampling rate. Here, the sampling speed needs to be at least twice the clock speed of the digital signal input from the sampling theorem, and is usually set to twice, quadruple, or the like to the power of two. Each output signal of the shift register 101 is input from the input side to D-2, D-1, D + 1, D +
2, D−2 and D + 2 are added to the product-sum circuit 201 by D−
1 and D + 1 are input to the product-sum circuit 202. Product-sum circuit 2
01 and the product-sum circuit 202 are realized by the circuit shown in FIG.
The multiplication of one input signal and the tap coefficient Cj is performed, and the results are added. The outputs of the product-sum circuit 201 and the product-sum circuit 202 are input to an adder 301, and the result of addition is output to a terminal 21.

Next, the configuration of the second embodiment shown in FIG. 2 will be described. One column of digital signals input from the terminal 12 is input to a 5-bit shift register 102 driven by a clock at a sampling rate. The sampling speed is the same as in the case of the configuration shown in FIG. Each output signal of the shift register 102 is supplied from the input side to D-2, D-1, D
Assuming that 0, D + 1, and D + 2, D-2 and D + 2 are input to the product-sum circuit 203, D-1 and D + 1 are input to the product-sum circuit 204, and D0 is input to the multiplier 401. Sum of products circuit 20
3 and the product-sum circuit 204 are realized by the circuit shown in FIG. 3, and the operation content is the same as that shown in FIG. Multiplier 40
1 multiplies the input signal D0 by the tap coefficient. The outputs of the product-sum circuit 203, the product-sum circuit 204, and the multiplier 401 are input to the adder 302, and the added result is output to the terminal 22.

Finally, the product-sum circuits 201, 202, 2 in FIG.
The configuration of the devices 03 and 204 will be described. The n-bit tap coefficient Ci input from the terminal 33 is input to the selection circuit 601. The selection circuit 601 receives the D + i input from the terminal 32
A signal obtained by inverting the signal by the inverter 572 is used as a selection signal, and the tap coefficient is directly used according to the value of the selection signal.
Alternatively, an inverted signal of all the bits is output. The output signal of the n-bit selection circuit 601 is input to the selection circuit 602. The inverted signal of the D + i signal input from the terminal 32 and the Di signal input from the terminal 31 are EX-OR
The output is input to the gate 501 and becomes the selection signal of the selection circuit 602. The selection circuit 602 receives the signal input according to the value of the selection signal as it is, or outputs the signal of all bits “0” representing the value “0”. Is output.

Next, the operation of each unit in FIG. 1 will be described.

The impulse response of the roll-off filter is symmetric on the time axis as shown in FIG. Therefore,
The tap coefficient which is the sampling value is also symmetric with respect to the center tap coefficient, and C-j and C + j have the same value. However, there is no tap coefficients C0 to the center in the case of even number of taps.

The product-sum circuit 201 calculates the product of the output D-2 of the shift register 101 and the tap coefficient Cj, and the product of D + 2 and the tap coefficient Cj, and adds the two. However, at this time, it is assumed that Cj has a two's complement representation suitable for the subsequent addition. Here, the output signal D of the shift register 101 is a 1-bit signal because the modulation scheme is QPSK. If this value is "0", representing -1/2 and "1" representing +1/2, the product of D and Cj is -C
j, + Cj, or “0”. That is, the two multiplications and the addition of the result are performed as shown in FIG.
It is determined by the sign of the two D's and no calculations need to be performed. Therefore, it is only necessary to select whether or not Cj is to be inverted by the selection circuit 601 and then to select whether or not to make it “0” by the selection circuit 602.

With respect to the specific configuration of the selection circuit, the selection circuit 601 includes a plurality of EX-OR gates 502 as shown in FIG.
５０504, the selection circuit 602 outputs a plurality of ANs as shown in FIG.
Since it is realized by the D gates 551 to 553, the full adder 3
11 can be made smaller in circuit size as compared with the conventional system configured using.

Since all bits are not inverted in the two's complement representation, when the polarity of Cj is inverted, the value is reduced by 1 LSB. For example, when all bits of “0001” are inverted with 4's two's complement, “1110” is obtained.
Where the true sign inversion is “1111”. This shift is corrected by inputting a signal indicating that sign inversion has been performed (the inverted signal of D + i in FIG. 3) to the carry input of the full adder 351 used in the adder 301 shown in FIG. be able to.

In the case of the odd tap shown in FIG.
The addition of 3 and 204 is performed by the first adder 301, and the addition of the adder 301 and the multiplier 401 is performed by the second adder 301. In addition, since it is necessary to handle the center tap individually, a multiplication circuit 401 for the center tap is required.

Further, since the tap coefficient decreases rapidly as the distance from the center increases, the actual number of bits of the tap coefficient decreases. Since the above and the sum-of-products circuit operate on taps symmetrical about the center, the tap coefficients are the same, and the circuit scale can be set according to the magnitude of the tap coefficients. Therefore, the circuit scale can be reduced as compared with the case where all taps are configured by the same circuit.

The configuration described above shows four taps as an example of even taps and five taps as an example of odd taps.

The present invention is not limited to this,
In the case of 2n (n ≧ 2) even taps, the ith output and the (2n + 1-i) th output of the 2n-bit shift register are input, and two inputs and outputs are provided by n product-sum circuits. The multiplication with the tap coefficient is performed, and the multiplication result is added. Then, the outputs of the n product-sum circuits combine all inputs by combining (n-1) 2-input full adders. In addition, sign inversion information of each product-sum circuit is input to the carry input of these full addition circuits.

On the other hand, in the case of an odd tap of (2n + 1), the ith output and the (2n + 2-i) th output of the (2n + 1) -bit shift register are inputted, and the (n)
Except for the (+1) -th output, n inputs and outputs multiply the two inputs by the tap coefficients and add the multiplication results. The (n + 1) -th output multiplies the input signal by the tap coefficient by a multiplier. The outputs of the n product-sum circuits and the multipliers are added to all inputs by combining n 2-input full adders.

The carry input of these full adders receives the sign inversion information of each product-sum circuit.

[0032]

As described above, the digital filter of the present invention is constructed using a full adder from the first stage by integrating the multiplication circuit and the first stage addition circuit by utilizing the symmetry of the tap coefficient. The circuit scale can be reduced as compared with the above method.

Further, tap coefficients at taps far from the center become very small, and the scale of the sum-of-products circuit is set according to the magnitude of the tap coefficients in order to perform a sum-of-products operation of two taps having the same value. it can.

Accordingly, even when the number of taps is large, a digital roll-off filter having a small overall circuit size can be realized, and the power consumption and the cost can be reduced accordingly.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of an FIR digital filter according to the present invention.

FIG. 2 is a diagram showing a second embodiment of the FIR digital filter of the present invention.

FIG. 3 is a diagram illustrating a configuration of a product-sum circuit in FIGS.

FIG. 4 is a diagram showing an impulse response of a roll-off filter.

FIG. 5 is a diagram showing a relationship between data D + i and Di of a shift register.

FIG. 6 is a diagram illustrating a configuration of a selection circuit 601 in FIG. 3;

FIG. 7 is a diagram illustrating a configuration of a selection circuit 602 in FIG. 3;

FIG. 8 is a diagram showing a configuration of an adder 301 in FIG.

FIG. 9 is a diagram illustrating a configuration example of a conventional FIR digital filter.

10 is a diagram illustrating a configuration example of a tap (multiplier) in FIG. 9;

11 is a diagram illustrating a configuration example of an adder 311 in FIG. 9;

[Explanation of symbols]

 101, 102, 151 Shift registers 201-204 Product-sum circuits 301, 302, 311 Adders 351, 361, 362 Full adders 411-416 Multipliers 501-504 Exclusive OR 551-553 AND gates 571, 572 Inverters 601 , 602 selection circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03H 17/06 655 H03H 17/02 601 H04L 27/20

Claims (4)

(57) [Claims] 1. A shift register for inputting one column of digital signals.
And two outputs symmetrical with respect to the center of each output of the shift register.
Forces and tap coefficients corresponding to the two outputs
Input, if the sign of the two outputs match, the two outputs
From the tap coefficient corresponding to the sign of the two outputs.
Output the tap coefficients of the signals, and the codes of the two outputs do not match.
In this case, it is preferable to have a selecting means for outputting a logical value "0" and an adding means for adding each output of the selecting means.
An FIR digital filter characterized by the following . 2. The digital filter according to claim 1, wherein the digital filter is
When the number of stages of the register is odd, each output of the selecting means
Addition for adding the output of the center of the shift register
2. The digitizer according to claim 1, further comprising means.
Filter . 3. The method according to claim 2, wherein the selecting means inputs one of the inputs.
Each bit of the tap coefficient is used, and the other input is
A plurality of exclusive OR circuits for outputting the sign of the output, and one input of each of the outputs to the output of the plurality of exclusive OR circuits.
And the other input is the exclusive OR output of the two outputs.
And a plurality of AND circuits
The digital filter according to claim 1. 4. The apparatus according to claim 1 , wherein said adding means outputs each output of said selecting means.
And a full adder for adding
-An output indicating the sign of the two outputs of the selection means at the input terminal
The digit according to claim 1 or 2, which is inputted.
Tal filter .