JP5753639B1 - Communication device - Google Patents

Abstract

The amount of filtering processing is reduced, and the modem is reduced in size, weight, and power consumption. A signal point conversion unit 130 divides a transmission signal point into bit information with / without a plurality of signal points, and inputs the bit information to tap delay line units 130-134. ROM sections 135 to 142, first addition sections 145 to 148, and multiplication sections 150 to 153 receive tap data input to tap delay line sections 131 to 134 and tap data under the control of transmission ROF control section 157. Filter outputs corresponding to individual signal points are obtained from the division information divided into a plurality of groups and the sampling phase information necessary for filtering. The second adders 155 to 156 add the filter output information of individual signal points to obtain a final filtering output. [Selection] Figure 13

Description

  The present invention relates to a communication device. Examples of the communication device include a digital simple wireless modem using a π / 4 shift QPSK modulation method (Quadrature Phase Shift Keying). More specifically, it includes a 9600 bps modem capable of mounting a set of main baseband functions on a general-purpose one-chip CPU (Central Processing Unit).

Digital simple radio was institutionalized in 1995, and any revision (for example, rental) can be used by any registered station due to the revision of the Radio Law.
Digital simple radio can be used nationwide, unlike commercial radio.

  For this reason, the application area has expanded in a wide range of fields such as surveying, computerized construction, and wide-area agricultural machinery, and demands for higher speeds and more stable communications have increased with increasing demand. ing.

As a conventional modulation method, an FSK modulation method (Frequency Shift Keying) with a communication speed of 4800 bps is known.
In recent years, there is a π / 4 shift QPSK modulation method as one of the technologies that meet the demand for higher speed.

The π / 4 shift QPSK modulation method is a QPSK modulation method that is phase-shifted by 45 degrees (π / 4 rad: 45 degrees) each time, is strong against amplitude fluctuation, and can perform high-speed transmission of 2 bits / Hz by the QPSK modulation method.
For this reason, according to the QPSK modulation method, high-speed transmission of 9600 bps, which is twice that of the FSK modulation method of 4800 bps, is possible.

  For example, one application of digital simple radio is RTK-GPS survey (Real Time Kinematic-Global Positioning System survey: real-time kinematic GPS survey).

  RTK-GPS surveying is a method in which corrected observation information from a known point is transmitted to a mobile station using a mobile phone or radio, and the position of the mobile station is measured in real time. Up to about 20 satellite information can be received.

  However, in surveying using a low-speed modem of 4800 bps, satellite information transmission from a known point is about 10 and half of about 20 at maximum, and stable surveying on the mobile station side is difficult.

  Here, a low-speed modem using the FSK modulation method or the like (hereinafter simply referred to as a low-speed modem) is converted to a high-speed modem (hereinafter simply referred to as a high-speed) using a π / 4 shift QPSK modulation method or the like. In order to increase the speed (called a modem), a method of adding a device capable of high-speed signal processing is conceivable.

For this reason, each manufacturer attaches a dedicated DSP-LSI (Digital Signal Processor-Large Scale Integration) outside the CPU, or an ASIC-LSI (Application LSI with a dedicated DSP installed). Development of Specific Integrated Circuit-Large Scale Integration (Application Specific Integrated Circuit) supports high speed.
FIG. 1 is a block diagram illustrating an example of a modem.

  A DTE (Data Terminal Equipment) 010 generates transmission data, and outputs the transmission data to a transmission UART (Universal Asynchronous Receiver Transmitter) unit 011 via RS232C (Recommended Standard 232C).

The transmission UART unit 011 receives the data from the DTE 010, converts the asynchronous serial data with start / stop bits into parallel data, and outputs the parallel data to the transmission encoding unit 012.
Transmission encoding unit 012 performs processing such as scrambler / error correction / interleaver, and outputs transmission data to signal point generation unit 013 as parallel data.
FIG. 2 is a block diagram showing the signal point generator shown in FIG.

The signal point generation unit 013 realizes four functions of gray / natural conversion, QPSK signal point generation, differential encoding, and π / 4 shift by the signal point generation unit 060 and the tap delay line 061.
In FIG. 2, double lines indicate parallel signals and vector signals.

  The signal point generation unit 060 is realized by, for example, a ROM (Read Only Memory: ROM) or the like, and transmits 8-level transmission signal point data (for example, 16 bits * 2) and 8-level transmission signal point information. (3 bits) is output, and the 3-bit information is fed back to the signal point generator 060 as address information through the tap delay line 061.

The signal point generation unit 060 uses the address information 5 bits (2 bits of output data of the transmission encoding unit 012 + 3 bits of information of the tap delay line 061) to generate gray / natural conversion, QPSK signal point generation, differential in the ROM. Encoding and equivalent calculation of four functions of π / 4 shift are performed, and desired output data is converted and output by the signal point generator 060.
Returning to FIG. 1, the conventional transmission operation will now be described.

The transmission ROF unit 014 performs a filter operation of the transmission ROF (RollOff Filter: roll-off filter), for example, with the transversal filter 120 shown in FIG. 12, etc., shapes the output spectrum of the signal point generation unit 013, and the IPL unit 015 Output to (Interpolation).
At the same time, the sampling rate of the input signal, 4.8 kHz, is interpolated, for example, four times to obtain a 19.2 kHz sampling output.

  The IPL unit 015 further triples the 19.2 kHz sampling output signal of the transmission ROF unit 014 to obtain, for example, a 57.6 kHz sampling output, and a transmission D / A unit 016 (Digital / Analog: digital / analog) [Conversion] section).

  A transmission D / A unit 016 is a digital / analog converter, converts an input digital signal (real signal and imaginary signal) into an analog signal, and outputs the analog signal to a transmission LPF (Low Pass Filter) unit 017. .

  The transmission LPF unit 017 removes unnecessary harmonic components of the real signal and the imaginary signal using a filter, and outputs the result to a MOD (Modulation) unit 019.

  The MOD unit 019 modulates the input output signal of the transmission LPF unit 017 by the local modulation frequency output from the LO unit (Local Oscillator) 018, obtains a passband modulation signal, and transmits this The data is output to a BPF (Band Pass Filter) unit 020.

The transmission BPF unit 020 removes unnecessary harmonic components generated at the time of modulation by a filter and outputs the result to a PA (Power Amplifier) unit 021.
The PA unit 021 is a power amplifier, amplifies the input signal to a desired transmission power, and outputs it to the transmission / reception switching unit 022.

The transmission / reception switching unit 022 includes not only transmission / reception switching but also a coupling circuit with an antenna, and after switching signals, outputs a transmission signal to the antenna 023. The wireless signal is output as a radio wave from the antenna 023 to the space.
The transmission control unit 024 performs control of other sets of individual blocks such as frame control, which is a well-known technique, in accordance with standard specifications described later.
Next, the receiving side in FIG. 1 will be described.

  First, the signal received by the antenna 023 is input to the transmission / reception switching unit 022, and the reception signal is output to the GSW (Gain SWitch: gain switch) unit 030.

The receiving unit shown in FIG. 1 has a reception dynamic range of about 144 dB at the maximum from near reception at the time of transmission of maximum 5 W (about 144 dBμV) to far-field reception of the minimum reception level (about 0 dBμV) defined in the standard specifications. It is preferable to endure.
Actually, since there is a loss at the time of near reception, the range up to here is not necessary.

  For this reason, when the GSW unit 030 receives a signal that exceeds a predetermined level, the gain of the GSW unit 030 is changed (lost) and controlled so as to obtain a desired reception level. The data is output to the reception BPF unit 031.

The reception BPF unit 031 removes out-of-band noise by BPF, and outputs a reception signal to an LNA (Low Noise Amplifier) unit 032.
The LNA unit 032 amplifies a low reception level signal and outputs the amplified signal to a DEM (Demodulator) 034.

  When the GSW unit 030 determines that a signal with a high reception level has been received, the LNA unit 032 may be notified and the circuit of the LNA unit 032 may be bypassed.

  The DEM unit 034 demodulates the received signal based on the oscillation frequency of the VCXO (Voltage Controlled Crystal Oscillator) unit 033 and outputs the demodulation result to the reception LPF unit 035.

  The reception LPF unit 035 removes unnecessary harmonic components from the demodulated signal with a low-pass filter and outputs the reception signal to an A / D unit (Analog / Digital: analog / digital [conversion] unit) 036.

The A / D unit 036 converts the received analog signal into a digital signal by an analog / digital converter and outputs the digital signal to a DCM (DeCiMation) unit 037.
In the embodiment, the sampling frequency of the A / D unit 036 is set to 28.8 kHz, for example.

The DCM unit 037 decimates the 28.8 kHz sampling signal using a decimation filter, reduces the sampling frequency to 9.6 kHz, and outputs the result to the reception ROF unit 038.
The reception ROF unit 038 is a waveform shaping filter on the reception side, performs waveform shaping, and outputs the waveform to the AGC unit 039.

  The AGC unit 039 performs gain control on the signal from which unnecessary out-of-band noise is removed so as to obtain a desired reception level, and sends the result to the reception differential unit 042 and the TIM unit 040 (Timing: timing unit). Output.

The TIM unit 040 extracts a timing signal from the received signal, and controls the oscillation frequency of the VCXO unit 033 via the D / A unit 041 by a PLL (Phase Locked Loop) circuit to synchronize the frequency and phase with the transmission timing. Establish.
Since this timing phase synchronization circuit is a well-known technique, a detailed description thereof is omitted.

  The reception differential unit 042 performs −π / 4 (−45 degrees) phase rotation on a signal for which timing phase synchronization has been established, and removes + π / 4 phase rotation performed on the transmission side to obtain eight values. The received signal is converted into a quaternary received signal.

However, since the phase is still undefined at this time, the phase difference circuit calculates the phase difference of the received signal, reproduces the signal point transmitted on the transmission side, and outputs it to the signal point determination unit 043. To do.
The signal point determination unit 043 determines the region of the quaternary reception signal and outputs the original 2 bits of the digital data to the reception encoding unit 044.

  In addition, the signal point determination unit 043 performs a natural / gray conversion opposite to the gray / natural conversion performed on the transmission side when outputting reception data.

  The reception encoding unit 044 performs deinterleaver / error correction / descrambler and the like opposite to those on the transmission side, reproduces the original digital data, and outputs the result to the reception UART unit 045.

The reception UART unit 045 outputs the reception data to a DTE (Data Terminal Equipment) 050 via a UART and a DV (Driver) of RS232C.
The DTE 050 processes the received data.
The reception control unit 046 controls a set of individual blocks, such as frame control (including a frame synchronization circuit), which is a well-known technique, in accordance with standard specifications described later.

  Here, if the sampling rate of the transmission D / A unit 016 can be output as fast as possible, the circuit scale of the analog transmission LPF unit 017 can be reduced, but the processing amount of the filter operation increases, and a general-purpose one-chip CPU or the like can be obtained. It becomes difficult to load the process.

On the other hand, if the sampling rate of the transmission D / A unit 016 is reduced, the processing amount of the filter calculation can be reduced, but the circuit scale of the analog transmission LPF unit 017 increases dramatically.
Therefore, there is a certain optimum value for the output sampling rate of the transmission D / A unit 016.
However, it is preferable to reduce the processing amount of the filter operation on the transmission side, realize high-speed sampling, and reduce the circuit scale of the analog transmission LPF unit 017.
Here, the processing amount of the transmission-side filter when the conventional technique is used is shown below.

In the transmission filter, a process of increasing the low speed 4.8 kHz sampling to a high speed, for example, 57.6 kHz sampling, is performed. The technique used in this case is an interpolation technique.
In particular,
57.6 kHz / 4.8 kHz = 12 times (Equation 1)
Are interpolated, but if 12 is factored, 2 * 2 * 3 is obtained.

  Accordingly, there are five possible combinations of the interpolation of the transmission ROF unit 014 and the IPL unit 015: 2 * 6 times, 3 * 4 times, 4 * 3 times, 6 * 2 times, and 12 * 1 times.

FIG. 3 is a diagram illustrating the processing amount of the transmission filter according to the related art.
Incidentally, since the amount of filter processing depends not only on the calculation capability of the CPU to be used, but also on the software creation method and the optimization result by the compiler, it is assumed here that the transmission ROF unit 014 shown in the first term of FIG. The processing time is set to 50 μs / 4800bauds.
This value is a realistic value obtained by slightly reducing the CPU processing speed of 120 MHz.
By reducing the clock frequency of the general-purpose one-chip CPU, for example, 120 MHz, the power consumption of the apparatus can be reduced.

As shown in the column 065 of the processing t in FIG. 3, the processing time of the transmission ROF unit 014 increases from the processing time of 50 μs to the processing time of 294 μs as the IPL rate increases.
Similarly, as shown in the processing t column 066 in FIG. 3, the processing time of the IPL unit 015 decreases from the processing time of 224 μs to the processing time of 0 μs (no IPL) as the IPL rate decreases. .
As shown in the hour meter column 067 in FIG. 3, the optimum value of the processing time in FIG. 3 is four times the IPL rate of the transmission ROF unit 014 in the third term and three times the IPL rate of the IPL unit 015. It turns out that this is the case.

However, even in this case, the processing time length of 210 μs is required for the filter calculation.
Since the modulation rate is 4800Bauds, the allowable processing time is
1/4800 ≒ 208μs ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ （Formula 2）
Thus, it can be seen that it is difficult to mount the filter on a general-purpose one-chip CPU only by looking at the processing amount of the transmission filter.
An important parameter that determines the amount of calculation of the filter is the number of taps, which depends on the required filter characteristics.

FIG. 4 is a diagram illustrating the required characteristics of the transmission filter.
In FIG. 4, the horizontal axis indicates the frequency kHz, and the vertical axis indicates the level.
FIG. 4 shows the required characteristics of the transmission filter corresponding to each IPL rate when complying with a standard specification described later.
Since the calculation of these required characteristics is a well-known technique, a detailed description is omitted, but the characteristics of (a) to (d) in FIG. 4 correspond to the IPL rates of the first to fourth terms in FIG. doing.
Next, a measure for reducing the amount of filter processing on the receiving side will be described.

FIG. 5 shows an example of reducing the processing amount of the reception filter according to the prior art.
The DCM rate in FIG. 5 indicates an integer value n of 1 / n decimation.
Also, the sampling frequency on the reception side is enhanced by improving the filter characteristics of the analog reception LPF unit 035 in order to improve the characteristic against interference waves, and the sampling frequency of the A / D unit 036 is 28. which is half that of the transmission side 57.6 kHz. It is set to 8 kHz.

  Incidentally, since the amount of filter processing depends not only on the computing power of the CPU to be used, but also on the software creation method and the optimization result by the compiler, here, the same standard as defined on the transmission side (in the table of FIG. 3) The processing time of the transmission ROF unit 014 in the first term is set to 50 μs / 4800bauds).

As shown in the column 070 of the process t in FIG. 5, the processing time of the DCM unit 037 is 0 μs as the DCM rate increases from 1.0 (1/1) to 3.0 (1/3). The time is increased from 73 to 73 μs.
With respect to the DCM rate of 2.0 (1/2), since the generation probability of the zero point of the filter coefficient is large, the processing amount is reduced accordingly. (The calculation is omitted for the part where the filter coefficient is zero because it is not necessary to perform the calculation.)
Similarly, as shown in the column 071 of the process t in FIG. 5, the processing time of the reception ROF unit 038 decreases as the DCM rate decreases from 3.0 (1/3) to 1.0 (1/1). The processing time is reduced from 269 μs to 91 μs.

As shown in the hour meter column 072 in FIG. 5, the optimum value of the processing time shown in FIG. 5 is that the DCM rate of the DCM unit 037 in the fourth term is 3.0 (1/3), and the reception ROF unit 038 It can be seen that the DCM rate is 1.0 (1/1).
However, even in this case, the filter operation takes a processing time length of 164 μs.
Since the modulation rate is 4800Bauds, the allowable processing time is
1/4800 ≒ 208μs ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ （Formula 3）
However, the receiving side also has processing related to timing synchronization, and at least the target specification is preferably about half or less of the modulation speed time.
For this reason, it can be seen that the reception filter processing is difficult to mount on a general-purpose one-chip CPU even when the sampling frequency of the A / D unit 036 is set to half of the transmission side.
An important parameter that determines the amount of calculation of the filter is the number of taps, which depends on the required filter characteristics.

FIG. 6 is a diagram illustrating the required characteristics of the reception filter.
In FIG. 6, the horizontal axis indicates the frequency kHz, and the vertical axis indicates the level.
FIG. 6 shows the required characteristics of the reception filter corresponding to each DCM rate when complying with a standard specification described later.
Since the calculation of these required characteristics is a well-known technique, a detailed description is omitted, but the characteristics of (a) to (d) in FIG. 6 correspond to the DCM ratios in the first to fourth terms in FIG. doing.

FIG. 7 is a diagram showing further required characteristics of the reception filter.
In FIG. 7, the horizontal axis represents frequency, and the vertical axis represents level.
FIG. 7 clarifies the required characteristics for the interference wave on the receiving side and examines the limit specification for satisfying the required characteristics.
(A) of FIG. 7 examines the reception side required characteristic at the input point of the transmission / reception switching unit 022.

At a frequency of 12.5 kHz or higher, with respect to jamming waves, BTER (BiT Error Rate) is 1 * 10E-2 or higher so that the required S / N including margin is 13.5 dB. The required characteristics are 53.0 dB + 13.5 dB = 66.5 dB or more (Equation 4)
It becomes.
Similarly, the 4.35 kHz point has an adjacent CH selectivity of 42 dB,
42.0 dB + 13.5 dB = 55.5 dB or more (Equation 5)
Is a required characteristic.

In FIG. 7A, the portion indicated by the bold line is the final required characteristic.
FIG. 7B shows the required characteristics of the reception LPF unit 035.
Since these are the scope of the prior art, a detailed description is omitted, but the bold line is a required characteristic of the final reception LPF unit 035.
FIG. 7C shows the required characteristics of the A / D unit 036.
The required characteristic of the A / D unit 036 is obtained by subtracting the required characteristic shown in FIG. 7B from the required characteristic shown in FIG.
The loss above the 9.6 kHz point of the reception LPF unit 035 is 11 dB.
Similarly, the final required characteristic is the characteristic of the thick line in FIG.

JP-A-6-180808 JP 2002-118444 A JP 2005-500724 A

As described above, each manufacturer either attaches a dedicated DSP-LSI (Digital Signal Processor-Large Scale Integration) outside the CPU, or an ASIC-LSI equipped with a dedicated DSP. By developing (Application Specific Integrated Circuit-Large Scale Integration), it supports high speed.
However, with the addition of functions for realizing these high-speed signal processing, there are problems such as an increase in the number of parts, an increase in power consumption, and an increase in development costs.

  Moreover, the 9600 bps modem for digital simple radio (standardized by the π / 4 shift QPSK modulation method) currently standardized in Japan has a large overhead in terms of specifications, and an effective speed sufficient for RTK-GPS surveying cannot be obtained. .

  Furthermore, the mobile station 003 shown in FIG. 8 is required to be further reduced in size / light weight / low power consumption due to its portability. However, as the speed of 9600 bps increases, the circuit scale increases and the size / cost increases. Increased power consumption.

In order to reduce the size / lightweight / low power consumption of a high-speed modem to the same level as a low-speed modem and to obtain an effective speed sufficient for surveying, for example, the following four points can be cited. First, "Effective minimization of overhead" and "Absorption of speed deviation between terminal and modem" achieves an effective speed of 9600bps. Second, "Digitalization of timing phase synchronization circuit" reduces the size of the analog circuit. Third and fourth, there is a concept of minimizing baseband processing by “reducing transmission / reception filtering processing amount”.
Among the above, what is considered to be particularly important is a reduction in the amount of filtering processing.

  Patent Document 1 describes an example of a waveform equalization circuit that always obtains an optimal equalization characteristic regardless of a change in transmission rate. However, a general transversal filter is important for essential filter processing. The amount of filter processing is not reduced.

  In Patent Document 1, waveform equalization is realized by changing the tap coefficient of the transversal filter and timing phase control is possible, but the amount of processing is not reduced.

  Patent Document 2 describes an embodiment of a digital filter circuit in which a high-speed operation is achieved in a digital filter. However, although a multiplier is used, the high-speed operation is possible. However, a significant reduction in processing amount has not been realized.

In Patent Document 3, multiplication is performed by logarithmically converting an input signal in an AGC circuit (Automatic Gain Control circuit), adding the signal in a logarithmic domain, and returning the logarithmic domain signal after the addition to the linear domain. However, since logarithmic conversion is limited to positive values only, the sign bit is separated from the input signal to make it positive, and logarithmic conversion is performed. Yes.
However, this embodiment cannot be applied as it is to filtering that performs multiple multiplication and addition.
As described above, the object of the present invention is to reduce the amount of filtering processing, to enable the main baseband function to be mounted on a general-purpose one-chip CPU, to realize a small size / light weight / low power consumption of the apparatus and an effective speed of 9600 bps. And more stable surveying on the mobile station side.

In order to achieve the above object, a disclosed communication device is provided. This apparatus has the following configuration.
(Configuration 1)
In a communication apparatus for filtering transmission signal point information, a plurality of tap delays including a signal point conversion unit that converts the transmission signal point information into bit information with or without a signal point, and 1 for inputting the bit information A transmission ROF control unit that divides bit information of each tap of the tap delay line unit into a plurality of groups including 1 and generates and outputs the divided division information, and the transmission ROF control The unit generates and outputs sampling phase information at the time of filtering, and accesses a plurality of ROM units including 1 based on the division information, the sampling phase information, and bit information of each tap, and A plurality of first addition units including 1 for obtaining an output and adding the output of the ROM unit, and a multiplication unit for multiplying the output of the first addition unit by a predetermined coefficient The multiplication result and the second addition unit for adding, by providing a communication apparatus characterized by realizing a reduction in the processing amount of the filtering.
(Configuration 2)
In a communication device for filtering a received signal, a logarithmic conversion ROM1 unit that virtually adds a DC offset to the received signal and performs logarithmic conversion, a tap delay line unit that time-shifts an output signal of the logarithmic conversion ROM1, and The filter coefficient of the communication device is virtually separated into a sign bit and absolute value information, and the absolute value information is separated into a mantissa part and an exponent part, and the mantissa part is logarithmically transformed, and the code The bit, the logarithm conversion mantissa information, the logarithmic conversion ROM 2 for outputting the exponent information, the tap data of the tap delay line, and the logarithm conversion mantissa information corresponding to the tap data are added. A plurality of first adders, a logarithmic inverse conversion ROM 3 for logarithmically transforming the result of the first adder, and an output of the logarithmic inverse conversion ROM 3 for the exponent information and the code bit A plurality of bit shifter / polarity control units for obtaining linear information, an addition unit for adding output signals of the plurality of bit shifters / polarity control units, and a value corresponding to the virtually added DC offset And a second adder for subtracting from the output of the adder, wherein the result of the second adder is used as the output of the filtering to achieve a reduction in processing amount.
(Configuration 3)
Extracts 1/2 Nyquist frequency components at a sampling frequency that is twice the Nyquist frequency, secures the data in the logarithmic conversion ROM 2 for a desired number of timing phases, and makes it possible to finely control the time phase of the filtering. The communication apparatus according to Configuration 2, wherein synchronization is realized.
(Configuration 4)
In a communication device that transmits and receives start / stop bit-attached start / stop bits, an ST / SPbit deletion unit that generates transmission data from which start / stop bits are deleted, and generates a no-transmission signal when there is no transmission data, and the transmission A transmission encoding unit that encodes data; a signal point generation unit that generates signal point information including an origin by the transmission encoding unit and the non-transmission signal; and the signal point information is received, and an origin signal Based on the output signal from the origin removing unit, the origin removing unit for removing the origin signal detected by the origin detecting unit, and the reception encoding unit opposite to the transmission encoding unit. When the start signal is detected by adding the start / stop bit deleted on the transmission side to the output of the reception encoding unit that performs encoding and the reception encoding unit, The configuration according to any one of configurations 1 to 3, wherein an effective speed of the start-stop data is maintained by including an ST / SPbit addition unit that marks and holds output data of the reception encoding unit. Communication device.

  According to the present invention, since the amount of filtering processing can be reduced, the main baseband function can be mounted on a general-purpose single-chip CPU, and the apparatus can be reduced in size, weight, and power consumption. Further, since the ST / SP bit deletion function and the origin signal transmission function can realize an effective speed of 9600 bps, more stable surveying can be realized on the mobile station side.

It is a block diagram which shows an example of a modem. FIG. 2 is a block diagram showing a signal point generator shown in FIG. 1. It is a figure which shows the processing amount of a transmission filter by a prior art. It is a figure which shows the required characteristic of a transmission filter. An example of receiving filter processing amount reduction according to the prior art will be described. It is a figure which shows the required characteristic of a receiving filter. It is a figure which shows the further required characteristic of a receiving filter. It is a figure which shows the comparison with the comparative example at the time of applying the communication apparatus of embodiment to RTK-GPS surveying. It is a figure which shows the specification comparison of the modem of this Embodiment. It is a figure which shows the whole block diagram of embodiment. It is a block diagram which shows the CPU part of the modem of embodiment. It is a figure which shows the general equivalent circuit of a transmission side filter. It is a block diagram which shows the transmission ROF part of embodiment. It is a figure which shows the further detailed equivalent circuit example of the transmission ROF part shown in FIG. It is a figure which shows the example of a transmission signal point by embodiment. It is a figure explaining the detail of the signal point generation part 101 in the case of Fig.15 (a). It is a figure which shows the ROM content of the signal point generation part 180 with which the signal point generation part 101 is provided. It is a figure which shows the modification of the signal point conversion part. It is a figure which shows an example of the value memorize | stored in the ROM part of a transmission ROF part. It is a figure explaining the reduction result of the processing amount of the transmission side filter of embodiment. It is a block diagram explaining the receiving filter part of embodiment. It is a figure which shows an example of the content memorize | stored in ROM of logarithmic conversion ROM1 part of embodiment. It is a figure which shows the time response waveform example of the receiving filter coefficient of embodiment. It is a figure which shows an example of the content memorize | stored in ROM of the logarithmic conversion ROM2 part of embodiment. It is a figure which shows an example of the ROM table content of logarithmic conversion ROM2 part by embodiment (applied to digital timing phase synchronization). It is a figure which shows an example of the content memorize | stored in ROM of logarithmic inverse conversion ROM3 part of embodiment. . It is a figure which shows the reduction result of the processing amount of the filtering by the receiving filter part of embodiment. It is a figure which shows the example of a frame structure by a prior art example and embodiment. It is a figure which shows the example of the transmission side speed deviation absorption circuit of embodiment. It is a figure which shows the time chart of the transmission side speed deviation absorption circuit of embodiment. It is a figure which shows the signal point of the transmission side of embodiment. It is a figure which shows the speed deviation absorption circuit of the receiving side of embodiment. It is a figure which shows the signal point example of the receiving side of embodiment. It is a figure which shows the circuit example of the origin detection part of embodiment. It is a figure which shows the circuit example of the origin removal part of embodiment. It is a figure which shows the circuit example of the ST / SPbit addition part of embodiment. It is a time chart which shows the operation | movement of the circuit of the ST / SPbit addition part of this Embodiment. It is a circuit block diagram of the TIM-PLL part by a prior art example. It is an extraction figure of a 1/2 Nyquist frequency component by a conventional example. It is an example of a time waveform after PWR composition by a conventional example. It is a figure which shows the circuit block diagram of the TIM-PLL part of embodiment. It is an example of the timing phase extraction vector of embodiment.

Hereinafter, a communication device according to an embodiment will be described in detail with reference to the drawings. In the figure, the same reference numerals indicate the same or equivalent “function / content / part”.
<Embodiment>

FIG. 8 is a diagram showing a comparison with a comparative example when the communication device of the embodiment is applied to RTK-GPS surveying.
The upper half of FIG. 8 is a system (comparative example) using a modem 90 with a communication speed of 4800 bps, and the lower half of FIG. 8 is a system to which the modem (communication apparatus) 1 of the present embodiment is applied.

  As shown in FIG. 8, for example, about 20 satellites 004 and 005 at maximum are visible in Hirono and the like with good visibility, and information on these satellites 004 and 005 is known on the known point 600 side and the mobile stations 002 and 003 side. Reception is possible.

  However, when the modem 90 having a communication speed of 4800 bps is used, only about 10 pieces of satellite information can be transmitted. Therefore, sufficient satellite information cannot be transmitted to the mobile station 002 side on the modem transmission side on the known point 600 side. An overflow condition occurs.

  Then, on the mobile station 002 side, it is not possible to sufficiently collate the information of up to about 20 satellites 004, 005 visible on the mobile station 002 side and the information of the satellites 004, 005 visible on the known point 600 side, As a result, stable surveying on the mobile station 002 side is difficult.

  On the other hand, in the system using the modem 1 of the present embodiment shown in FIG. 8, an effective speed of 9600 bps sufficient for realizing stable surveying is realized. For this reason, information transmission about twice that of the modem 90 is possible, and stable surveying on the mobile station 003 side can be realized.

  Specifically, the modem 1 first achieves an effective speed of 9600 bps by “minimizing overhead necessary” and “absorbing speed deviation between the terminal and the modem”. Second, the analog circuit is miniaturized by “digitalization of the timing phase synchronization circuit”. Third and fourth, the baseband processing is minimized by “reducing transmission / reception filtering processing amount”.

  As described above, all of the main baseband functions can be mounted on a general-purpose single-chip CPU, and an effective speed can be realized and the apparatus can be reduced in size, weight, and power consumption.

FIG. 9 is a diagram showing a comparison of specifications of the modems according to the present embodiment.
As shown in FIG. 9, the modem 1 not only can reduce the size of the analog circuit, but also can greatly reduce the amount of filtering processing, so that all the main baseband functions can be mounted on a general-purpose one-chip CPU.
For this reason, the modem 1 can achieve a small size / light weight / low power consumption at least as high as a conventional 4800 bps modem while realizing a high-speed transmission of 9600 bps.
As a result, it will become possible to expand the application area not only in the surveying field, but also in a wide range of fields such as the computerized construction field and the wide-area agricultural machinery field.
The modem 1 according to the present embodiment is a digital simple wireless π / 4 shift QPSK modem. The main specifications of the modem 1 will be described below.

The main specifications of “Digital Simplified π / 4 Shift QPSK Modem” are the standard specifications in Japan “Digital Simplified Radio Station Radio Equipment ARIB STD-T98 (Association of Radio Industries and Businesses Standard-T98: Radio Industry” Society standard T-98) 1.2 edition revised on July 15, 2010 ". The main specifications of the modem 1 conform to these standard specifications.
Although details are omitted, main specifications related to the modem 1 are as follows.
Radio frequency: 351 MHz band, 467 MHz band Channel spacing: 6.25 kHz
Modulation method: π / 4 shift QPSK method Transmission speed: 9600 bps
Modulation speed: 4800Bauds (baud: symbol / s)
Roll-off rate: 20%
Occupied frequency bandwidth: 5.8 kHz or less Transmission spurious: 60 dB or less Reception sensitivity: 0 dB μV or less Unmodulated interference wave: 53 dB or more Adjacent CH selectivity: 42 dB or more Intermodulation characteristics: 53 dB or more

(Overall block diagram)
FIG. 10 is a diagram showing an overall block diagram of the embodiment.
About the same function as FIG. 1, the same code | symbol is attached | subjected and description is omitted.
The modem 1 shown in FIG. 10 is different from the modem 90 shown in FIG. 1 in that a transmission encoding unit 100, a signal point generation unit 101, a transmission ROF unit 102, a transmission control unit 103, a TIM unit 104, a DCM unit 105, and a reception ROF. Unit 106, reception differential unit 107, reception encoding unit 108, and reception control unit 109.
Details of the individual differences will be described in detail in the individual embodiments shown below.

(Basic configuration of general-purpose 1-chip CPU)
As described above, as one method for realizing stable surveying and miniaturization / lightweight / low power consumption of a mobile station, all the main baseband functions can be mounted on a general-purpose one-chip CPU. Can be mentioned.
Here, first, a basic configuration of a general-purpose single-chip CPU unit will be described below.

FIG. 11 is a block diagram illustrating a CPU unit of the modem according to the embodiment.
A general-purpose single-chip CPU unit 110 shown in FIG. 11 includes a CPU 113 that performs arithmetic processing, a ROM 114 that stores arithmetic programs and data, and a RAM 115 that stores various data.
The input / output of information to be processed will be described.
First, the DTE side can input and output various kinds of digital information by the transmission side UART 111, the reception side UART 112, and other I / Os 116.
On the line side, various analog information can be input / output by D / A 117 and A / D 118.

  As described above, the general-purpose one-chip CPU 110 used in the present invention can take digital information and analog information outside the CPU 110 into the CPU 113, perform various signal processing, and output the results as digital information and analog information outside the CPU 110.

A general-purpose one-chip CPU is generally good at various judgments and logic processing under abundant memory, but it takes a relatively long time for high-speed signal processing involving multiplication and the like.
<Focus on the invention: Reduction of filter processing amount on the transmission side>
First, a general transmission side filter (other than the modem 1) will be described.

FIG. 12 is a diagram illustrating a general equivalent circuit of the transmission-side filter.
As shown in FIG. 12, the transversal filter 120 on the transmission side includes tap delay lines 121 to 123, a plurality of multipliers 125 to 128, and an adder 129, and is an equivalent circuit with high-speed signal processing. It has become.

On the other hand, the CPU unit 110 included in the modem 1 is not good at high-speed multiplication processing as described above, but has abundant ROM capacity (for example, ROM 114 is 2 Mbytes) and can perform high-speed logic processing.
From the above, one point of reducing the processing amount is how to eliminate multiplication / addition in the transmission side filter and realize multiplication / addition in the ROM 114.

For example, if the tap data A * filter coefficient B, which is the main part of the filter operation, is to be realized in the ROM 114, the tap data A and the filter coefficient B may be assigned to the address space of the ROM 114 as they are. Then, the tap data A and the filter coefficient B can be multiplied in the ROM 114, and the multiplication result can be obtained instantaneously.
However, if the tap data A is 16 bits and the filter coefficient B is 16 bits, 32 bits are required as an address, which is not practical.
Considering the above, the point is how to reduce the information of the tap data A and the filter coefficient B and reduce the address space.

  Fortunately, for tap data A, the number of signal points is limited to a total of 9 values (8 signal points + 1 origin signal value) as shown in FIG. It will be enough.

  Further considering, since this 4-bit information is generated from 3-bit information as shown on the input side of FIG. 16 to be described later, the tap data A information can be reduced from 16 bits to 3 bits. It becomes.

Although the filter coefficient B is 16 bits, the filter coefficient B itself is determined by the tap coefficient numbers C1 to Cn in FIG. Specifically, as shown in FIG. 3, it is only necessary to have tap number information for the number of taps from 45 to 265 taps.
Therefore, if the maximum is about 9 bits, 16-bit tap coefficient information B can be generated in the ROM 114.
In total, it can be realized with a total of 12 bits of tap data A (3 bits) + tap coefficient B (9 bits), which is a realistic number of bits.

As a result, multiplication of the tap data A * filter coefficient B can be performed in the ROM. However, these operations are temporarily performed by the multipliers 125 to 128, and these outputs are further output by the adder 129 in FIG. Addition takes time for processing. If possible, we want to reduce these addition processes.
That is, if attention is paid to further shortening the processing time, the reason for performing multiplication in the first place is that the value of the tap data A has nine-value information.
Therefore, if the 9-value information can be converted into 1-bit information with or without signal points, that is, logic 1 or logic 0, multiplication is not necessary, and it can be realized with only an adder.

  That is, as shown in FIGS. 15B and 15C, the transmission signal points are a total of eight signal points “A, −A, B, −B, C, −C, D, −D”. It was decided that each filter operation was performed with the decomposed information. An example of realizing this is the transmission ROF unit 102.

(Reduction of transmission filter processing amount)
FIG. 13 is a block diagram illustrating a transmission ROF unit according to the embodiment.
As shown in FIG. 13, the transmission ROF unit 102 has a function of filtering transmission signal point information.
Specifically, the transmission ROF unit 102 includes a signal point conversion unit 130, tap delay line units 131 to 134, ROM units 135 to 142, first addition units 145 to 148, multiplication units 150 to 153, Second addition units 155 and 156 and a transmission ROF control unit 157 are provided.
The signal point conversion unit 130 converts the information of the transmission signal point into bit information having one or more signal points or no signal point.

Specifically, the signal point information input to the transmission ROF unit 102 is assumed to be 3-bit information, as shown on the input side in FIGS. 18A and 18B, and this 3-bit information. 18 (a) and 18 (b), that is, information in the hex column 189 in FIG. 17 (signal point presence / absence information output: 8-bit information) is obtained.
More specifically, this 8-bit information is 8 points of logical information 1, 0, ± A, ± B, ± C, ± D shown in FIGS. 15B and 15C.

For example, when the modulation method is changed from π / 4 shift QPSK to 16-value QAM, the eye pattern is 16 points + origin point as shown in FIG. 15 (d), and this is similarly applied to the Real axis and Imag axis. When separated, the results are as shown in FIGS. 15 (e) and 15 (f).
Similarly, even when the modulation method is changed to 64-value QAM, 256-value QAM, and further to 1024-value QAM, it can be similarly developed.
Such logic information is output from the signal point conversion unit 130 shown in FIG.
The tap delay line units 131 to 134 are shift registers, for example, and each receives bit information.

  The transmission ROF control unit 157 divides the bit information of each tap of the tap delay line units 131 to 134 into one or more groups, generates divided division information, and outputs it.

The transmission ROF control unit 157 generates and outputs sampling phase information at the time of filtering, and accesses the ROM units 135 to 142 based on the division information, the phase information, and the bit information of each tap, and the ROM units 135 to 142. To obtain one or more outputs.
The first addition units 145 to 148 add the outputs of the ROM units 135 to 142.
Multipliers 150 to 153 multiply the outputs of first adders 145 to 148 by a predetermined coefficient.
The second addition unit 155 adds the multiplication results of the multiplication units 150 and 151. The second addition unit 156 adds the multiplication results of the multiplication units 152 and 153.
The transmission ROF unit 102 uses the result of the second addition units 155 to 156 as an output of filtering, and realizes a reduction in processing amount.
Hereinafter, the operation of the transmission ROF unit 102 will be briefly described.

  The logic information output from the signal point conversion unit 130 is input to the tap delay lines 131 to 134, and the tap data A in the tap delay lines 131 to 134 is input as address information of the ROM units 135 to 142.

  In the ROM sections 135 to 142, in addition to the tap data A described above, the tap data A described above is divided into a plurality of groups (for example, the ROM sections 135 to 136). For example, the ROM unit 135 is accessed by adding output phase information (described later), and a plurality of tap data A and a plurality of filter coefficients B are calculated (multiplication and addition) in the ROM unit 135 and a plurality of taps are performed. A filter output for data A is obtained.

This filter output is added by the first adder 145, and amplitude information with polarity information (for example, ± A, ± A) of each signal point when the signal point is converted into logic information by the multiplier 150 is added to the addition result. B, ± C, or ± D) is multiplied to obtain the filter output of each signal point, and this is further added by the second adder 155 to obtain the final filter output.
More specific examples will be described later.

FIG. 14 is a diagram illustrating a further detailed equivalent circuit example of the transmission ROF unit illustrated in FIG. 13.
In FIG. 14, the same numbers as those in FIG. 13 indicate the same contents as in FIG.
In FIG. 14, signal point information is input to the signal point conversion unit 130 and decomposed into information with / without a plurality of signal points, and individual 1-bit information is output to the corresponding individual tap delay line units 131. .
An example of an input signal of the signal point conversion unit 130 is shown in FIG. 15 (a) or FIG. 15 (d).

As shown in FIG. 15 (a) or FIG. 15 (d), the input signal example of the signal point conversion unit 130 is not the coordinate information of the signal point but only the number information indicating the position of each coordinate point.
For example, since (a) in FIG. 15 is 8 values and origin information, the total is 9 values, that is, 4-bit information is input to the signal point conversion unit 130.
Further, in the case shown in FIG. 15D, since 16 values and origin information are obtained, a total of 17 values, that is, 5-bit information is input to the signal point conversion unit 130.
FIG. 16 is a diagram for explaining the details of the signal point generator 101 in the case of FIG.
The signal point generation unit 101 includes a signal point generation unit 180, a WR control unit 181, and a tap delay line 182.

As shown in FIG. 16, the input signal of the signal point generator 101 is a total of 3 bits of information (hereinafter referred to as 3 bits information) including 2 bits of transmission data and 1 bit of information indicating no transmission (origin information). .
This 3-bit information is input to the signal point generator 180 as ROM address information, and a 4-bit signal point generator output is obtained as the ROM output.

  At the same time, the output 4 bits of the signal point generator 180 is input to the WR controller 181 (WRright: write). The WR control unit 181 controls whether or not 3 bits of the 4 bits excluding the origin are written to the tap delay line 182.

  The WR control unit 181 does not write to the tap delay line 182 when outputting the origin information, and writes 3-bit information excluding the origin information to the tap delay line 182 when outputting information other than the origin information.

  This tap delay line information is delayed by one symbol (in this embodiment, a time length of 4800 Hz) and used as address information of the signal point generator 180. This realizes differential encoding on the transmission side.

FIG. 17 is a diagram showing the ROM contents of the signal point generator 180 included in the signal point generator 101.
The input information column 185 of FIG. 17 shows the input information of the signal point generator 180, and includes 1 bit of no transmission information (1: transmission, 0: no transmission) and 2 bits of transmission data information (00, 01). , 11, 10) and reference point angle information (0 degrees, 90 degrees, 180 degrees, 270 degrees).

The past information column 186 is information fed back from the tap delay line 182 shown in FIG. 16 and has eight values (3 bits: 0 degree, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees), and shows 3-bit signal point information transmitted in the past.
Thus, differential encoding is performed in the ROM, and the differential encoding result is output to the output information 187.
The output information column 187 shows 4-bit angle information including origin information.
The signal point conversion unit 130 shown in FIG. 14 converts and outputs 8-bit information with / without signal points using a ROM based on the input 4-bit information.
The signal point information (± A, ± B, ± C, ± D) in FIG. 15B and FIG. 15C shows an image of the output of the signal point conversion unit 130.
The value described in the output bit information column 188 in FIG. 17 indicates bit information of signal point information (± A, ± B, ± C, ± D) indicating the presence / absence of individual signal points.
Next, a modification of the signal point conversion unit 130 will be described.

<Modification>
In the above-described embodiment, the signal point generation unit 101 and the signal point conversion unit 130 shown in FIG. 16 are independently connected. However, since the content is ROM conversion, signal point generation is performed. The ROMs included in the unit 180 and the signal point conversion unit 130 may be combined into a single ROM.
FIG. 18 is a diagram illustrating a modification of the signal point conversion unit 130.

As illustrated in FIG. 18A, the signal point conversion unit 130 a illustrated in FIG. 18B is a combination of the signal point conversion unit 183 and the signal point generation unit 101 included in the signal point conversion unit 130. The signal point generation conversion unit 184 outputs an 8-bit signal in response to an input of 3-bit input signal. The WR control unit 181 and the tap delay line 182 are the same as those in FIG.
The final ROM contents are as described with reference to FIG.

  As described above, the 4-bit information input to the signal point conversion unit 130 or the 3-bit information input to the signal point conversion unit 130a is converted into 8-bit signal point presence / absence information by the ROM shown in FIG. Are output to the individual tap delay lines 131.

Since the signal point presence / absence information is 1-bit information, that is, there is a signal point: 1, and no signal point is 0, even if this is multiplied by the filter coefficient B, 1 * B = B Since 0 * B = 0, multiplication is not necessary.
Therefore, the ROM sections 135 to 136 do not require multiplication in the ROM, and suddenly can perform cumulative addition after multiplication.

However, since the number of address bits in the ROM is limited, as shown in FIG. 3, it is 45 to 265 taps in ROF or 25 to 121 taps in IPL, and the number of filter taps is also a large value. It has become.
On the other hand, the sampling rate of the input signal point of the transmission ROF unit 102 is 4800Bauds in this embodiment, which is 4800 Hz.

  In this embodiment, the output of the transmission D / A unit 016 is 57.6 kHz sampling, and the transmission D / A unit 016 including the transmission ROF unit 102 is subjected to 12 times interpolation. It has become.

For this reason, in general, zero point insertion is performed on the input side of the filter, and filter operation is performed. In this embodiment, the data sequence in which zero point insertion is performed is converted into phase information, and tap delay is performed. The data in the line is in units of 4800 Hz.
Accordingly, the number of taps of 45 taps at 9600 Hz is sufficient if the number of taps is about half of 23 taps.

In the present embodiment, when the filter output is 57.6 kHz, in order to realize 12-fold interpolation, there are 12 output phases from PH0: phase 0 to PH11: phase 11 (total output phase of 4 bits). Information) output phase is defined.
Even in this case, since there are 23 taps, it is not realistic to access the 23-bit information as the address information of the ROM units 135 to 136 as it is.

For this reason, in the present embodiment, the transmission ROF control unit 157 groups tap data and divides the tap data into a plurality of groups, so that the number of address bits to the ROM units 135 to 136 is within an allowable range.
Specifically, for example, it is divided into four groups (division information 2 bits), and access to the ROM sections 135 to 136 by tap data is suppressed to 6 bits.

As described above, the number of access bits to the ROM units 135 to 136 includes 6 bits in the tap data 160 to 165 in the tap delay line unit 131, 2 bits of division information of the tap data, and 4 bits of output phase information of the filter. The total is 12 bits, which is a realistic value.
The address control of these ROMs is realized by causing the transmission ROF control unit 157 to operate the CPU with software.

  As described above, the ROM units 135 to 136 multiply and accumulate the tap data A and the filter coefficient B in units of groups / phases, and the same signal point is added by the first addition unit 145. The cumulative addition result of the filter is obtained.

However, since this filter result is a filter output result based on logical information with and without signal points, the size and polarity information (± A, ± B, ± C, ± D) of each signal point is reflected. Absent.
For this reason, the multiplier 150 multiplies predetermined coefficients (± A, ± B, ± C, ± D) to reflect these amplitude information and polarity information.

  Since the filter output of the multiplier 150 is filter output information of one point among a plurality of signal points (± A, ± B, ± C, ± D), the second adder 155 collects the filter output information. Then, predetermined signal point outputs 166 to 169 (± A, ± B, ± C, ± D) are added to obtain a final filter output.

For example, since this filter output is the Real side filter output, the ROF unit 176 in FIG. 14 similarly performs the calculation on the Imag side to obtain the Imag side filter output.
The calculation control of these filter outputs is realized by operating the CPUs in the plurality of address control units 170 to 174 in the transmission ROF control unit 157 by software.
Next, a calculation example of the ROM units 135 to 142 of the transmission ROF unit 102 illustrated in FIG. 13 will be described.

FIG. 19 is a diagram illustrating an example of values stored in the ROM unit of the transmission ROF unit.
The column 190 of the filter coefficient in FIG. 19 shows an example of the filter coefficient of the ROF when the 12-times interpolation is realized.
According to FIG. 3, the number of taps is 265 taps. However, the number of taps in the ROM portion is good, and the number of taps is expanded to a total of 288 taps from 0 to 287 taps.

A column 191 of tap_data (PH0 to PH11) indicates a case where tap data is shifted to 12 phases in units of 4.8 kHz, and is indicated by numerical values of PH0: 0 to ~ PH11: 11 in the table.
In the column 191, 1 indicates “signal point present” and 0 indicates “no signal point”.
According to the phase, the virtual tap data is shifted in the tap delay line, and the target filter coefficient is selected.

The ROM section output column 192 includes a 4gr (4 group: 4 group information) column, a phase column 193 (12 phase information), and a tap data information column 194 (64 bits because of 6 bits). , Operate in the ROM to obtain the filter output result.
As described above, the output of the transmission ROF unit 102 is obtained.
By the way, it is important to reduce the amount of transmission side filter calculation, but various parameters are optimized.
Specifically, in addition to the five patterns of the conventional example shown in FIG. 3, two pieces of information of group division information and phase information are newly added as parameters.
Therefore, optimization considering these parameters is performed.
Next, the processing amount reduction result by the transmission filter realized by the transmission ROF unit 102 will be described.

FIG. 20 is a diagram illustrating a result of reducing the processing amount of the transmission-side filter according to the embodiment.
FIG. 20 shows a processing result when the processing of the IPL unit 015 of the conventional example is cascade-connected to the transmission ROF unit 102 to which this embodiment is applied.
In the ROF column 195, the IPL rate of the ROF is set, and as shown in FIG. 3, there are five patterns of 2/3/3/4/6/6/12 interpolation.

The required address bit number column 196 includes a group division number (bit number: for example, 2 bits in 4 divisions) and phase number (bit number: for example, in 12 phases). (4 bits).
The total number of bits is shown in the total column.
The processing amount column 197 indicates the processing time length (μs) under the above-described conditions.
Since the IPL column 198 is the same as the prior art, the values shown in FIG. 3 are adopted.
A total column 199 indicates a processing time length (μs) in which the values in the processing column 197 and the values in the IPL column 198 are totaled.
Considering the balance between the reduction in the number of taps and the processing amount, the optimum value is the combination of the 36th term from the above results.
Specifically, only the transmission ROF unit 102 is processed without providing the IPL unit 015, 12-fold interpolation is performed, and D / A output is performed.
As specific parameters, the ROM sections 135 to 136 are accessed with data for 6 taps in 4 groups and 12 phases, and a filter output is obtained.

As described above, the processing time of 210 μs shown in FIG. 3 can be shortened to 56 μs in the present embodiment. This means that a processing amount reduction of about 73% can be realized.
(Reduction of receiving side filter processing amount)
<Focus on the invention: Reduction of filtering amount on the receiving side>
Unlike the transmitting side, the signal point is not limited on the receiving side, so the reduction technique on the transmitting side cannot be applied to the receiving side as it is.
As shown in FIG. 12, one of the points of the reception side filter is how to change multiplication to addition, like the transmission side.
Changing the linear multiplication (tap data A * filter coefficient B) to addition can be realized by logarithmic conversion of the signal.
That is,
log (A * B) = log (A) + log (B) (6)
However, the condition at this time is A> 0, B> 0, that is, A and B are positive numerical values.
However, both the tap data A and the filter coefficient B are numerical values having positive and negative values.
Therefore, first, a method for solving this point is considered.
The tap data A can be converted into a positive numerical value by adding a predetermined DC offset to a received signal having positive and negative polarities.
For example, by adding a DC offset of +3.00 to a received signal of ± 2.00, ± 2.00 can be converted to a positive numerical value in the range of +1.00 to +5.00.
The obtained DC offset may be obtained by subtracting the corresponding DC offset value from the output after obtaining the filter output result.
As described above, the tap data A can be logarithmically converted.
Similarly, the filter coefficient B is a numerical value having positive and negative polarities, but a DC offset cannot be added like the tap data A.
Therefore, for the filter coefficient B, the filter coefficient information is separated into absolute value information and sign bit information, and the absolute value information is logarithmically added.
The separated sign bit information is restored after the multiplication of the tap data A and the filter coefficient B (after logarithmic addition) and after the subsequent logarithmic inverse transformation.
Although the receiving side filter calculation amount can be reduced as described above, there is one problem. It is to secure the necessary number of bits accompanying logarithmic inverse transformation.

As shown in FIG. 12, the equivalent circuit of the reception side filter is composed of a large number of tap data A. In order to obtain a filter output, the adder 129 cumulatively adds the data after logarithmic inverse transformation.
Since the quantization noise is also cumulatively added by the cumulative addition, a minimum S / N for performing the filter output S / N is ensured at the time of logarithmic inverse conversion.
In general, the number of bits required at the time of cumulative addition needs to have sufficient bit accuracy depending on the number of taps, and the number of bits at the time of logarithmic inverse conversion needs to be sufficiently secured.
As a result, the ROM capacity accompanying the logarithmic inverse transformation becomes enormous and becomes an unrealistic value.
Therefore, it is preferable to reduce the ROM capacity at the time of logarithmic inverse conversion.
Compression of the number of bits of the filter coefficient itself is effective for compression of the number of bits before logarithmic inverse transformation.

For this reason, the filter coefficient is separated into absolute value information and sign bit information, the absolute value information is further decomposed into a mantissa part and an exponent part, and the mantissa part is logarithmically transformed to logarithmically add to the tap data A. Reduce the range of coefficient B.
Then, after logarithmically adding the filter coefficients, the output signal is logarithmically inverted, and the sign bit information and the exponent part information are reflected in the data after logarithmically inverse conversion to obtain the final filter output.
As described above, the number of bits at the time of logarithmic inverse conversion can be reduced. A specific number of bits of the equivalent circuit and details of the equivalent circuit will be described later.

FIG. 21 is a block diagram illustrating the reception filter unit according to the embodiment.
The reception filter unit 228 shown in FIG. 21 is an equivalent circuit of the DCM unit 105 and the reception ROF unit 106. The reception filter unit 228 shows only the Real unit, but Imag has a similar circuit configuration.

  The reception filter unit 228 virtually adds a DC offset to the received signal and performs logarithmic conversion, a logarithmic conversion ROM 1 unit 200, a tap delay line unit 205 that time-shifts the output signal of the logarithmic conversion ROM 1 unit 200, and a filter device The filter coefficient is virtually separated into a sign bit and absolute value information, and the absolute value information is separated into a mantissa part and an exponent part. Furthermore, the mantissa part is logarithmically converted, and the sign bit and logarithm conversion are performed. A logarithmic conversion ROM 2 206 for outputting the later mantissa information and exponent information, and a plurality of first data for adding each tap data of the tap delay line 205 and the mantissa information after logarithmic conversion corresponding to each tap data 201 to 204. Adders 210 to 213, logarithmic inverse conversion ROM 3 parts 215 to 218 for inversely transforming the results of the first adders 210 to 213, and logarithmic inverse conversion ROM 3 parts 215 to 21 A plurality of bit shifter / polarity control units 220 to 223 for obtaining linear information by exponent information and sign bits, an addition unit 225 for adding output signals of the plurality of bit shifter / polarity control units 220 to 223, and a virtual A second adder 226 that subtracts the value corresponding to the added DC offset from the output of the adder 225 is provided, and the result of the second adder 226 is used as the output of the filter to reduce the processing amount.

The A / D unit 036 converts the analog signal into a digital signal by analog / digital conversion, and outputs the digital signal to the DCM unit 105.
The DCM unit 105 performs a decimation operation, reduces the sampling rate, and outputs the result to the reception ROF unit 106.
Reception ROF unit 106 performs waveform shaping using ROF and outputs the result to AGC unit 039.
The point here is how to reduce the calculation amount of the DCM unit 105 and the reception ROF unit 106.
Details of the processing of the reception filter unit 228 will be described below.
The logarithmic conversion ROM 1 unit 200 adds a DC offset to 12-bit A / D conversion information, and converts ± 2.00 digital information into a positive numerical value.
Specifically, a DC offset of +3.00 is added and converted to a value of +1.00 to +5.00, and the addition result is logarithmically converted and output.
Note that the number of bits after logarithmic conversion is set to 16 bits and output to the tap delay line 201 so that there is no missing information after A / D conversion by DC offset addition.
FIG. 22 is a diagram illustrating an example of contents stored in the ROM of the logarithmic conversion ROM 1 unit according to the embodiment.
The ROM1 input column 230 shows the 12-bit hex output of the A / D unit 036.
The hex [800] to [000] to [7FF] are −2.00 to 0.00 to +1.99 as real values.
A DC offset of +3.00 is added to this and logarithmically converted.

In the column 231 of internal processing contents, A / D_numerical value (−2.00 to +1.99), DC addition (result after DC addition, 1.00 to 4.99), logarithmic conversion (result after DC addition) Logarithmic conversion: 0.00 to 0.699).
The ROM 1 output column 232 shows values obtained by converting the logarithmically converted numerical values into 16-bit hex information.
The tap delay lines 201 to 204 receive the logarithmic conversion ROM 1 output and shift the tap data with a predetermined sampling clock.

The logarithmic conversion ROM 2 206 separates the filter coefficient into sign bits and absolute value information. Further, the logarithmic conversion ROM 2 unit 206 decomposes the absolute value information into a mantissa part and an exponent part. Further, the logarithmic conversion ROM 2 unit 206 logarithmically converts the mantissa part and outputs a logarithmic conversion value, sign bit information, and exponent information.
FIG. 23 is a diagram illustrating an example of a time response waveform of the reception filter coefficient according to the embodiment.
As shown in FIG. 23, the filter coefficient includes a large number of minute coefficients with positive and negative polarities.
FIG. 24 is a diagram illustrating an example of contents stored in the ROM of the logarithmic conversion ROM 2 of the embodiment.
FIG. 24 illustrates an example in which a 41-tap filter is constructed with 9.6 kHz sampling in the reception ROF unit 106.
The ROM2 input column 235 shows the values of the mantissa part and the exponent part in the specific filter coefficients of all 41 taps.
The ROM2 output column 236 shows hex information of sign / mantissa (logarithm conversion value) / exponent for each filter coefficient.
Using the contents of this ROM table, the filter coefficient information is converted into a desired value.

FIG. 25 is a diagram showing an example of the contents of the ROM table of the logarithmic conversion ROM 2 section according to the embodiment (applied to digital timing phase synchronization).
This ROM table supports finer table contents of filter coefficients so that the filter phase can be changed.
Details will be described later.
The adders 210 to 213 logarithmically add each tap data A value of the tap delay line unit 205 and the filter coefficient B value (logarithm conversion value of the mantissa part of the filter coefficient), and logarithmic inverse conversion ROM3 parts 215 to 218 Output to.

The logarithmic inverse conversion ROM 3 sections 215 to 218 convert the input information into linear information using the ROM shown in FIG. 26 and output the converted information to the bit shifter / polarity control sections 220 to 223.
FIG. 26 is a diagram illustrating an example of contents stored in the ROM of the logarithmic inverse conversion ROM 3 in the embodiment.
The ROM3 input hex column 245 in FIG. 26 shows hex information [0000] to [3FFF] of the input signal.
The logarithmic inverse transformation / 8 column 246 is obtained by inversely transforming the input information and multiplying the result by 1/8.
The ROM3 output hex column 247 converts the value of inverse logarithmic conversion / 8_246 into hex information and outputs it as ROM output.
The output value is a value in the range of [0800] to [4FFD] in hex.

The bit shifter / polarity control unit 220 to 223 performs bit shift (arithmetic shift) on the output of the logarithmic inverse conversion ROM 3 unit 215 to 218 according to the exponent part and sign information of the logarithmic conversion ROM 2 unit 206 (ROM 2 output 236 in FIG. 24). And the polarity is given to obtain linear information after logarithmic inverse transformation.
These processes are realized by the CPU 113, and the result is output to the adder 225.
The adder 225 adds the output values of the plurality of bit shifter / polarity controllers 220 to 223, and outputs the result to the second adder 226.
The second adder 226 subtracts the DC offset value corresponding to the DC offset value added in the logarithmic conversion ROM 1 unit 200 to obtain a final filter output.
The above processing is performed by the CPU 113 by software installed in the reception filter control unit 227.
Here, the necessary number of bits in the logarithmic inverse conversion ROM 3 215 to 218 will be considered below.

First, the required specifications for the out-of-band noise with respect to the received signal are calculated from the required specifications of the ARIB standard specifications, because the out-of-band noise is 42 dB or more and the required S / N is 13.5 dB or more. In the example, 55.5 dB or more is necessary in addition.
When converted to the number of bits,
Number of bits≈ (55.5-1.8) /6.02≈8.92 bits (formula 07)

In the logarithmic conversion ROM 1 unit 200, a DC offset is added so as to enable logarithmic conversion of a signal having positive and negative polarities, but this DC offset addition increases the number of bits.
Specifically, since DC offset +3.00 is added to signal ± 2.0 (PAR6 dB, effective +1.00),
20 * log (3/1) = 9.54 dB (Equation 8)
When converted to the number of bits,
9.54 / 6.02 = 1.59 bits (Equation 9)
Therefore,
8.92 bits + 1.59 bits = 10.51 bits (Formula 10)
It becomes.
Since the logarithmic mantissa is added at the time of logarithmic addition, the added value is in the range of 0.00 to 0.30, that is, a real number in the range of 1.00 to 2.00.
Therefore, the number of bits to be considered is +1.00 bits.
From the above, the number of bits is
8.92 + 1.59 + 1.00 = min. 11.51 bits (11)
It becomes.
Since the required number of taps is DCM: 49 tap / ROF: 41 tap, the reverse calculation is 5.6 bits.
Therefore, the number of bits after logarithmic addition is
8.92 + 1.59 + 1.0 + 5.6 = 17.11 bit (Formula 12)
It becomes.
However, in practice, since the exponent control is performed by the bit shifter / polarity control units 220 to 223, it is necessary to consider the range of the exponent control.
The specific index control range is -1 bit to -11 bit, but the average is -7.5 bits.
In the first place, since the bit shift offset is −1 bit, the effective exponential average is −6.5 bits, which sufficiently satisfies the above 5.6 bits.
Therefore, the increase in the number of bits at the time of cumulative addition +5.6 bits need not be considered in the logarithmic inverse conversion ROM 3 215 to 218.
From the above, the minimum number of bits required for inverse logarithmic conversion in this example is
8.92 + 1.59 + 1.00 = 11.51 bit (Formula 13)
It can be said that a minimum of 12 bits is sufficient.

If the margin is expected to be +2 bits (12 dB), it becomes about 14 bits, which is a full support version of A / D 12 bits. FIG. 26 shows the contents of the conversion table when the logarithmic inverse conversion is 14 bits.
The number of bits is optimized for each system according to the required specifications.
FIG. 27 is a diagram illustrating a result of reducing the amount of filtering performed by the reception filter unit according to the embodiment.
The values shown in the DCM column 250 in FIG. 27 show examples of the processing amount of the DCM unit 105.
By increasing the DCM rate from 1.00 times (1/1 times) to 3.00 times (1/3 times), the processing t (processing time length) increases from 0 to 43 μs.
On the other hand, the value shown in the ROF column 251 shows an example of the processing amount of the receiving ROF unit 106.
By reducing the DCM rate from 3.00 times (1/3 times) to 1.00 times (1/1 times), the processing t (processing time length) is reduced to 159 to 54 μs.

  The value shown in the total column 252 is the total of the processing time lengths described above, but the final optimum value is obtained by performing 28.8 kHz sampling by 1/3 times decimation in the DCM section 105 of the fourth term. .6 kHz sampling is performed, and the reception ROF unit 106 maintains 9.6 kHz sampling by 1/1 decimation, and performs waveform shaping and digital control of a timing phase synchronization circuit described later by filtering.

  From the above, according to the present embodiment, the processing time of the filter that took 164 μs shown in FIG. 5 can be reduced to 97 μs (approximately 40% reduction in processing amount) as shown in FIG. This means that a processing amount reduction of about 40% can be realized.

(Realization of effective speed)
<Focus on invention: Realization of effective speed>
The realization of the effective speed is, first of all, reducing the overhead defined in the standard specifications as much as possible.
Further, since the transmission data is limited to data with start / stop, transmission is performed by deleting start bits and stop bits unnecessary for transmission at the time of transmission to minimize the transmission data itself.
On the other hand, since the transmission data is start / stop start data, the character speed does not match the transmission speed on the modem side.
Absorbs the speed deviation for this.

By deleting the start / stop bit on the modem side, for example, in the case of a total of 10 bits including a start bit of 1 bit, user data of 8 bits, and a stop bit of 1 bit, the effective speed can be expanded to 10/8 times. When the speed on the DTE side is faster than the transmission speed of the modem, the speed deviation can be absorbed.
Conversely, when the DTE side speed is slower than the transmission speed of the modem, the modem side notifies the receiving side in some way because there is no data to be transmitted.

In the present embodiment, when there is no data to be transmitted, the origin signal is transmitted, and the receiving side detects the origin signal to determine that there is no transmission data, and the DTE 050 has no start / stop bit. All Z signal (all 1: all mark signal) is output.
As described above, the effective speed can be realized. Detailed operation will be described later.
28 to 37 show related drawings.

  The modem 1 that transmits / receives start / stop bit-attached start-up data generates transmission data from which the start / stop bit is deleted, and, when there is no transmission data, an ST / SPbit deletion unit 300 that generates a no-transmission signal, and transmission data The transmission encoding unit 301 that encodes the signal, the signal point generation unit 101 that generates signal point information including the origin from the transmission encoding unit 301 and the signal without transmission, the signal point information is received, and the origin signal is detected Based on the output signal of the origin removal unit 322 and the origin removal unit 322 that removes the origin signal from the detection result of the origin detection unit 321, and the detection result of the origin detection unit 321. And the start / stop bit deleted on the transmission side is added to the output of the reception encoding unit 323 and the reception encoding unit 323, and the origin signal is detected. If the is provided with a ST / SPbit adding unit 324 to mark holds the output data of the received coding unit 323. Thereby, the effective speed of the start-stop data can be maintained.

<Allowable deviation of transmission UART unit>
The transmission UART unit 011 in FIG. 10 receives start-stop data with start / stop from the DTE 010.
The transmission speed of the modem 1 according to the present embodiment is 9600 bps. However, since it is asynchronous data of start / stop data, the effective speed transmitted from the DTE 010 and the transmission possessed by the CPU unit 110 shown in FIGS. As for the speed, even at the same 9600 bps, the communication speed is different.
For this reason, the transmission UART unit 011 absorbs this speed deviation.

  In the UART of the transmission UART unit 011, the input signal is generally sampled with a sampling clock 16 times the data communication speed, an internal trigger is generated by detecting the start bit, and the stop bit is 50% at a predetermined timing. When the bit width point is detected, the input data is fetched.

Since these are executed centering on the clock speed on the modem side, the allowable value of speed deviation absorption in the transmission UART unit 011 can be calculated from the above-described data capturing procedure.
Since these are well-known techniques, the details are omitted, but according to the calculation result, the allowable deviation on the modem side is about ± 4.375%.
Further, based on past experience, the allowable deviation specification for speed deviation absorption on the modem side is set to ± 3.00% in the present invention.
Similarly, the receiving side outputs the received data to DTE 050. However, when processing is performed at the same speed as the transmitting side, a phenomenon in which output is impossible occurs.

Therefore, in this embodiment, the transmission UART unit 011 receives input data at a rate of 9600 bps, and the reception UART unit 045 side outputs data to the DTE 050 at a rate of 19.2 kbps to absorb the speed deviation.
<Reduction of transmission overhead>
The transmission data is transmitted to the reception side by deleting the start bit and the stop bit from the 10-bit data.
For this reason, the effective speed required on the line side is as follows.
9600 bps * 1.03 * 8/10 = 7910.4 bps (Formula 14)
Therefore, it is essential to secure an effective speed of at least 7911 bps on the line side.
FIG. 28 is a diagram showing an example of a frame structure according to the conventional example and the embodiment.
According to the current ARIB standard specification T98, the frame format is as shown in FIG. 28 (a) and FIG. 28 (b).

According to this, even if SB0 (Synchronous Burst0: synchronous burst) is excluded, the effective speed on the line side is 6400 bps, and it is difficult to obtain a desired effective speed.

  On the other hand, among SC (Service Channel: communication channel), RICH (Radio Information Channel: radio information channel) is used in the standard specification T98 to “transfer user information as needed. It is considered that a part of this portion is used for a communication channel.

When this part is fully assigned to the communication channel, as shown in FIG. 28C, the effective speed can be realized up to 8300 bps, and therefore the target of 7911 bps or more can be realized.
The number of missing bits is calculated as follows.
9600 bps / 384 * X = 7911 bps (Equation 15)
X = 316.44 bits (Equation 16)
The number of missing bits Y is
Y = 316.44-96-160 = 60.44 bits (Equation 17)

It becomes. Therefore, in this embodiment, the effective speed can be realized by assigning 61 bits of the RICH 70 bits and the undefined 6 bits in total 76 bits to the transmission data in the communication channel. Plan.
FIG. 28 (c) shows a case where these are fully assigned to the transmission data, and the maximum is 8300 bps, that is,
8300 bps / 8 * 10 = 10375 bps (Equation 18)
10375 bps = about 9600 bps + 8% (Equation 19)
It is possible to support up to effective speed.
<Reduction of transmission side start / stop bits>
FIG. 29 is a diagram illustrating an example of a transmission-side speed deviation absorption circuit according to the embodiment.
The transmission UART unit 011 receives transmission data from the DTE 010 and outputs data with start / stop bits to the ST / SPbit deletion unit 300.

  The ST / SPbit deletion unit 300 stores the input transmission data 10 bits in the input buff unit 303 and outputs it to the output buff unit 305 in accordance with the input / output buff monitoring control unit 304.

  The input / output Buff monitoring control unit 304 outputs a no-transmission signal (1-bit information) to the transmission encoding unit 301 and the signal point generation unit 101 when the data with start / stop is not input.

The input / output Buff monitoring control unit 304 outputs a no-transmission signal for 4 symbols (8-bit time length) using a counter (not shown) when a no-transmission signal is output (when an origin signal is output).
This realizes transmission control in units of 8 bits so as to prevent erroneous detection due to noise or the like when detecting no transmission signal (origin signal) on the receiving side.
That is, transmission data is always transmitted in units of 8 bits even when there is no transmission signal.
The output Buff unit 305 outputs transmission data to the transmission encoding unit 301 in units of 2 bits / Bauds in accordance with the input / output Buff monitoring control unit 304.

The transmission encoding unit 301 performs processing such as scrambler / error correction / interleaver on the input transmission data 2 bits in accordance with the specifications stipulated in the ARIB standard specification T98, and signals 2-bit transmission data information. Output to the point generator 101.
Details of the scrambler / error correction / interleaver and the like are described in detail in the ARIB standard specification T98 and are well-known techniques, and thus the description thereof is omitted.
The transmission encoding unit 301 stops the above-described processing when a signal without transmission is received.
These are realized by operating the CPU 113 by software.
FIG. 30 is a diagram illustrating a time chart of the transmission-side speed deviation absorption circuit according to the embodiment.
FIG. 30 shows a case where there is no transmission data in the middle of input data, and transmission data is mark-held.
In this case, the input / output Buff monitoring control unit 304 monitors the input data and outputs a signal without transmission data.
FIG. 31 is a diagram illustrating signal points on the transmission side according to the embodiment.
FIG. 31A shows a specific signal point arrangement of signal point 3-bit information excluding the origin in the output 4-bit information of the signal point generator 101.
FIG. 31B shows a specific signal point arrangement of the origin information among the 4-bit information output from the signal point generator 101.
FIG. 31 (c) shows a specific signal point arrangement of the output 4-bit information (including the origin) of the signal point generator 101.
<Detection of no transmission signal (origin signal)>
FIG. 32 is a diagram illustrating a speed deviation absorbing circuit on the receiving side according to the embodiment.
The AGC unit 039 shown in FIG. 10 adjusts the reception level to a desired level, and then outputs the reception signal to the reception differential unit 107 (reception phase rotation unit 320).
FIG. 33 is a diagram illustrating an example of signal points on the reception side according to the embodiment.

The reception phase rotation unit 320 receives signal points of 9 values (8 values + origin signal) shown in FIG. 33A, and with respect to a 45 degree phase rotation due to the π / 4 shift performed on the transmission side, Inverse phase rotation of −45 degrees, that is, phase rotation of 0 degree, −45 degrees, −90 degrees, −135 degrees, −180 degrees, −225 degrees, −270 degrees, and −315 degrees is performed. Signal points of 5 values (4 values + origin signal) shown in (b) are obtained, and the result is output to the origin detection unit 321 and the origin removal unit 322.
FIG. 34 is a diagram illustrating a circuit example of the origin detection unit according to the embodiment.

  The origin detection unit 321 inputs the input signal (FIG. 33 (b)) to the tap delay lines 330 to 332, the PWR units 335 to 338 calculate PWR (power), and 4 in units of 4 symbols. The sum of PWRs between symbols is calculated by the adder 339.

Thereafter, the adder 340 adds the TH value (negative threshold value), and the polarity determination unit 341 determines whether the signal is within the dotted circle in FIG. 33B. The result is set as an origin detection signal and output to each part.
FIG. 35 is a diagram illustrating a circuit example of the origin removing unit according to the embodiment.
The origin removing unit 322 inputs the received signal to the tap delay line 352 and writes the received signal to the tap delay line 354 according to the origin detection unit output signal after a delay of 4 symbols.
Specifically, the WR control unit 353 performs WR control and writing by the WR control unit 353 (write control unit) in accordance with the output signal of the origin detection unit 321 as in the transmission side.
When the origin signal is not detected, the multiplier 355 calculates the phase difference from the past received signal point, and outputs the result as a differential output (four values shown in FIG. 33C).
As described above, the origin signal transmitted on the transmission side is removed, and the result is output to the signal point determination unit 043.
In the signal point determination unit 043, the input signal ((c) in FIG. 33) is phase-shifted by 45 degrees to generate the signal point shown in FIG. 33 (d).

  Thereby, the signal point determination unit 043 determines the reception signal point from the quadrant information, performs natural / gray conversion opposite to that on the transmission side, reproduces the transmission data, and outputs the result to the reception encoding unit 323 in FIG. Output.

The reception encoding unit 323 performs deinterleaver, error correction, and descrambler, which are known techniques opposite to those on the transmission side, and outputs the original transmission data to the ST / SPbit addition unit 324.
FIG. 36 is a diagram illustrating a circuit example of the ST / SPbit adding unit according to the embodiment.
The ST / SPbit adding unit 360 adds a start / stop bit to the input signal and outputs it to the selection unit 361.

The selection unit 361 also receives the mark signal, and selects the mark signal and outputs it to the reception UART unit 045 when receiving the origin signal according to the output result of the origin detection unit 321.
FIG. 37 is a time chart showing the operation of the circuit of the ST / SPbit adding unit of the present embodiment.
As shown in FIG. 37, when the origin detection signal is received, the received data signal is marked.
The reception UART unit 045 includes the reception signal that has been mark-held, and outputs the reception signal to the DTE 050 at a speed of, for example, 19.2 kbps.
As described above, the speed deviation between the DTE 010 and the modem is absorbed, and an effective speed of 9600 bps is realized.
(Digitalization of timing phase synchronization circuit)
<Focus on invention: Digitization of timing phase synchronization circuit>
The following two points are focused on the digitization of the timing phase synchronization circuit.
The first is to realize the sampling frequency of the receiving filter at half of the conventional example.

Second, the filter phase is not realized by hardware using an analog VCXO (voltage controlled crystal oscillator), but is realized by digital processing by moving the filter coefficient over time.
Hereinafter, points of digitization of the timing phase synchronization circuit will be described while explaining a conventional example.
FIG. 38 is a circuit block diagram of a TIM-PLL unit according to a conventional example.
As shown in FIG. 38, DCM section 105 outputs the received signal to receiving ROF section 402.
The quantization unit 443 outputs the phase information Δθ to the filter coefficient control unit 400.
The filter coefficient control unit 400 outputs the control result to the filter coefficient ROM unit 401.
The filter coefficient ROM unit 401 outputs a desired filter coefficient to the reception ROF unit 402.
Reception ROF unit 402 outputs a filter output to AGC unit 039 according to desired phase information.

The AGC unit 039 adjusts the received signal to a desired reception level, and outputs it to the BPF units 411 and 412. The BPF unit 411 is a 1/2 Nyquist frequency extracting BPF (Real side), and the BPF unit 412 is a 1/2 Nyquist frequency extracting BPF (Imag side).
FIG. 39 is an extraction diagram of 1/2 Nyquist frequency components according to a conventional example.
A dotted line 425 in the figure indicates a 1/2 Nyquist frequency. A solid line 426 indicates an example of a 1/2 Nyquist frequency extracting BPF characteristic.

The BPF units 411 and 412 extract a ½ Nyquist frequency component from the input received signal by using a BPF (indicated by reference numeral 426 in FIG. 39 is a BPF characteristic example), and the results are respectively extracted to the PWR units 413 and 413 on the Real side. And output to the PWR unit 414 on the Imag side.
FIG. 40 is a time waveform example after PWR synthesis according to the conventional example.
The received signal is basically input as a time response waveform of the transmission / reception filter.
The carrier phase of the received signal is a signal obtained by rotating the carrier phase according to the transmission path, and the carrier phase is basically indefinite.

In order to extract the timing signal from this received signal, the power is calculated by the PWR unit, and the Real side and the Imag side are added by the adder 415, so that the signal synchronized with the timing phase from the thick line information shown in FIG. Are extracted by the BPF unit 416.
Here, what is important is, for example, that the signal passing through the BPF unit 416 is the Nyquist frequency, and is, for example, 4800 Hz in the embodiment.
Therefore, in order to easily realize vector conversion by the vector conversion unit 420, it is necessary to realize the BPF unit 416 at four times the Nyquist frequency.

That is, when the A / D unit 036 to the BPF unit 416 are realized at a sampling rate four times the Nyquist frequency, the processing amount on the receiving side is a very heavy circuit block.
On the other hand, from the sampling theorem, the sampling frequency may be any sampling rate that is twice the Nyquist frequency.
For this reason, in this embodiment, by limiting the timing extraction to a sampling frequency that is twice the Nyquist frequency, the reception filtering process is realized in half of the conventional method.
This case will be described later.

The adder 415 adds the Real side and Imag side timing signals, removes the carrier phase component, and outputs the result to the BPF unit 416 to extract the Nyquist frequency component.
The BPF unit 416 extracts the Nyquist frequency component by BPF and outputs the result to the vector conversion unit 420.

  The vector conversion unit 420 converts a scalar signal into a vector signal by a signal shifted in time by ¼ of the Nyquist time length by the tap delay line 421 (that is, a signal having a phase difference of 90 degrees), and converts the result into θ conversion. To the unit 422.

  The θ conversion unit 422 converts the vector signal into phase information (scalar information indicating timing phase information) by processing using a function of tan−1 or a simple ROM, and the result is sent to the first integrator 430. Output.

  The first integrator 430 includes a multiplier 431, an adder 432, a tap delay line 433, a multiplier 434, and an adder 435. The first integrator 430 performs a calculation of a first integration circuit that is a well-known technique, and the result is a second integration. Output to the circuit 440.

  The second integration circuit includes an adder 441, a tap delay line 442, a quantization unit 443, and an adder 444, performs the operation of the second integration circuit that is a well-known technique, and outputs the result to the filter coefficient control unit 400.

Since the first integration circuit and the second integration circuit are well-known techniques, the detailed description is omitted, but the quantization unit 443 performs quantization in accordance with the phase resolution of the reception ROF unit 038. For example, in the case of 8-bit quantization, quantization is performed with 8 bits, the remaining component is calculated by the adder 444, and the result is fed back to the tap delay line 442.
Next, the circuit block of the TIM-PLL part of this embodiment will be described.
FIG. 41 is a diagram illustrating a circuit block of the TIM-PLL unit according to the embodiment.
In FIG. 41, the same reference numerals as those in FIG. 38 indicate the same contents as those in FIG.

41 are different from FIG. 38 in that the receiving ROF unit 500, the −22.5 degree phase rotating unit 501, the counter unit 502, the M22.5 degree phase rotating unit 503, the multiplier 504, the BPF units 511 and 512, vector conversion Parts 513 and 514, (a + jb) square parts 515 and 516, and an adder 517. The BPF unit 511, the vector conversion unit 513, and the (a + jb) square unit 515 process Real-side signals. The BPF unit 512, the vector conversion unit 514, and the (a + jb) square unit 516 process the signal on the Imag side.
42A and 42B are examples of timing phase extraction vectors according to the embodiment.
The reception ROF unit 106 performs a filter operation using the block diagram of the reception filter unit 228 shown in FIG.
Further, the filter coefficient shown in FIG. 25 is used as the filter coefficient.

The -22.5 degree phase rotation unit 501 has a sampling speed of 9600 Hz and a phase rotation opposite to that on the transmission side, that is, 0 degree / -22.5 degrees / -45 degrees / -67.5 degrees / -90 degrees / -112.5 degrees / -135 degrees / -157.5 degrees / -180 degrees / -202.5 degrees / -225 degrees / -247.5 degrees / -270 degrees / -292.5 degrees / -315 degrees / The rotation signal has a radius of 1.0 at −337.5 degrees / −360 degrees = 0 degrees /.
As a result, the π / 4 shift on the transmission side is restored and the timing phase extraction is facilitated.
The counter unit 502 is a 4-bit (16 phase) repetitive counter, and outputs the result to the M22.5 degree phase rotation unit 503.
The M22.5 degree phase rotation unit 503 outputs the phase information of the selected radius 1.0 to the multiplier 504 based on the result of the counter unit 502.
Multiplier 504 performs phase rotation of the signal of AGC unit 039 and outputs the result to BPF units 511 and 512.
The BPF units 511 and 512 have the same functions as the BPF units 411 and 412, but the sampling frequency is half that of the BPF units 411 and 412.
Specifically, the BPF units 511 and 512 have a sampling frequency of 9600 Hz, which is twice the Nyquist frequency of 4800 Hz.
FIG. 42 is an explanatory diagram for realizing timing phase extraction at a sampling rate that is twice the Nyquist frequency.
42A shows output signal images of the BPF units 511 and 512. FIG.

As shown in FIG. 39, the BPF units 511 and 512 extract ½ Nyquist frequency components. Therefore, in the vector space, as shown in FIG. It is signal point transition information.
This vector signal is accompanied by a carrier phase θc.

Since this carrier phase information is an unnecessary signal for timing phase synchronization, it is preferably removed in some form. For this reason, in the present embodiment, signals converted from the output signals of the bBPF units 511 and 512 by 90 degrees by the vector conversion units 513 and 514 (that is, T / 2 delay information) as in the vector conversion unit 420. Thus, the scalar signal is converted into a vector signal.
The (a + jb) square units 515 and 516 perform the square calculation of the vector signal on the vector-transformed information ((a) in FIG. 42).
In the vector square calculation, the phase information is added and the amplitude information is multiplied. Therefore, for the same signal, the phase information is doubled and the amplitude is squared information.
FIG. 42B is a diagram illustrating an example of input signals and output signals of the (a + jb) square units 515 and 516.
That is, the carrier phase θc is doubled 2θc, the amplitude is a square value, and the vector signal has a changed amplitude.

When this signal is separated from the Real component and the Imag component, the carrier phase information is Real side amplitude information (square value) and Imag side amplitude information (square value) of the timing phase information, By adding this with the adder 517,
[COS (2θc)] ** 2+ [SIN (2θc)] ** 2 = constant (Equation 20)
Thus, the carrier phase component θc disappears.
Since the remaining signal is only the timing phase information, the timing phase extraction unit 510 can extract the timing phase information.
Subsequent first integration circuit 430 and second integration circuit 440 are the same as those in the prior art, and thus description thereof is omitted.

  According to the modem 1 of the present embodiment, the sampling rate of the TIM unit 104 can be halved compared to the conventional rate. As a result, the sampling rate from the A / D unit 036 to the reception ROF unit 106 and the AGC unit 039 is also conventional. The processing amount on the receiving side can be greatly reduced.

  Furthermore, in the embodiment, since the embodiment of FIG. 21 is applied to both the DCM unit 105 and the reception ROF unit 106, the processing amount can be further reduced.

  The field of application of the digital simple radio of the present invention is, for example, a research report of the “Survey Study Group for Contributing to Effective Use of Frequency in Data Transmission of Digital Simple Radio” of March 2010 by the Ministry of Internal Affairs and Communications. According to the following application fields are envisaged.

Specifically, telemeter / telecontrol / valve control / meter reading system / article monitoring / unmanned rice mill management / vending machine management / environmental telemeter / agricultural water management telemeter, etc. Use of mobile systems such as news / daily goods delivery / product transportation, digital broadcast / agricultural / mountain community / wireless facsimile / use as a local broadcast radio regardless of fixed / moving such as sightseeing assistance, safety detection of going to / from school / animals Position detection such as detection / reporting system, positioning system use as reporting system, waterway / road monitoring / autumn leaves camera / illegal dumping / discovery of disaster situation / harmful animal monitoring / observation (use of disabled / elderly) , GPS in combination with local traffic situation / delivery service / providing information on regional traffic operation / industrial waste monitoring, etc. Use in production management systems such as skiing / manufacturing and sales office management, patrol system / patient care support / shopping support / IC tag detection system / disaster information display system / reliable system for hikers, etc. Use in the environment, use in environmental protection systems such as illegal dumping monitoring systems, sightseeing information provision system / tourism rental system / rental cycle management / tourist guidance rental IC cane / parking inn information guide / road guidance system / inside facilities The use of tourism support such as lost child monitoring and the use in weather environment systems such as field servers, regional weather monitoring, production weather management, greenhouse monitoring control, plant factory monitoring control, etc. are envisaged.
Needless to say, the present invention can be applied not only to wireless communication but also to wired transmission, optical communication, LED communication, and other transmission media.
The elemental technology in the present invention is roughly divided into four types.

  The first is a reduction in the amount of transmission filtering, the second is a reduction in the amount of reception filtering, the third is absorption of speed deviation between the terminal and the modem, and the fourth is the timing phase synchronization circuit. Digital technology.

  The first transmission filtering processing amount reduction technique is not limited to the π / 4 shift QPSK described above, but also includes BPSK (Binary Phase-Shift Keying), multi-phase PSK (Phase-Shift Keying), and multi-level QAM (Quadrature Amplitude Modulation). For example, the present invention can be applied to 256 QAM, 1024 QAM, and the like.

The second reception filtering processing amount reduction technology is not limited to a digital simple wireless modem, but also SC-FDMA (Single-Carrier Frequency-Division Multiple Access) for performing high-speed wideband filter processing, UWB (Ultra Wide Band), optical It can be applied in a wide range of fields such as communication modems.
It goes without saying that the third speed deviation absorption technique can be applied not only to the digital simple radio but also to other start-stop data systems with start / stop.
Similarly, the digitization technique of the fourth timing phase synchronization circuit is applicable not only to digital simple radio but also to other systems.
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims.
The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  In addition, the elemental technology described in the present specification or drawings exhibits technical usefulness alone or in various combinations, and is not limited to the combinations described in the claims at the time of filing.

  In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1 Modem 90 Modem 002, 003 Mobile station 004, 005 Satellite 010, 050 DTE
011 Transmission UART unit 012 Transmission encoding unit 013 Signal point generation unit 014 Transmission ROF unit 015 IPL unit 016 Transmission D / A unit 017 Transmission LPF unit 018 LO unit 019 MOD unit 020 Transmission BPF unit 021 PA unit 023 Transmission / reception switching unit 023 024 Transmission control unit 030 GSW unit 031 Reception BPF unit 032 LNA unit 033 VCXO unit 034 DEM unit 035 Reception LPF unit 036 A / D unit 037 DCM unit 038 Reception ROF unit 039 AGC unit 040 TIM unit 041 D / A unit 042 Moving unit 043 Signal point determination unit 044 Reception encoding unit 045 Reception UART unit 046 Reception control unit 047 Main baseband unit 060 Signal point generation unit 061 Tap delay line 100 Transmission encoding unit 101 Signal point generation unit 102 Transmission ROF unit 103 Shin controller 104 TIM portion 105 DCM 106 receives ROF unit 107 receives the differential unit 108 receives the coding unit 109 receives the control unit 110 CPU 111 transmitting side UART
112 Receiver UART
113 CPU
114 ROM
115 RAM
116 Other I / O
117 D / A
118 A / D
120 Transversal filter unit 121-123 Tap delay line 125-128 Multiplier 129 Adder unit 130 Signal point conversion unit 131-134 Tap delay line unit 135-142 ROM unit 145-148 First adder unit 150-153 Multiply unit 155 156 Second addition unit 157 Transmission ROF control unit 160 to 165 Tap delay line 166 to 169 Signal point filter unit 170 to 174 Address control unit 175 to 176 ROF unit 180 Signal point generation unit 181 WR control unit 182 Tap delay line 183 Signal point Conversion unit 184 Signal point conversion unit 200 Logarithmic conversion ROM1 unit 201-204 Tap delay line unit 205 Tap delay line unit 206 Logarithmic conversion ROM2 unit 210-213 Adder 215-218 Logarithmic inverse conversion ROM3 unit 220-223 bit shifter / polarity control Part 25 Adder 226 Adder 227 Reception filter control unit 228 Reception filter unit 300 ST / SPbit deletion unit 301 Transmission encoding unit 302 Transmission encoding unit + signal point generation unit 303 Input Buff unit 304 Input / output Buff monitoring control unit 305 Output Buff Part 310 Origin signal detection area (8 values + origin reception)
311 Origin signal detection area (4 values + origin reception)
320 reception phase rotation unit 321 origin detection unit 322 origin removal unit 323 reception encoding unit 324 ST / SPbit addition unit 330 to 332 tap delay line 335 to 338 PWR unit 339 addition unit 340 adder 341 polarity determination unit 350 to 351 tap delay Line 352 Tap delay line unit 353 WR control unit 354 Tap delay line 355 Multiplier (complex conjugate multiplier)
360 ST / SPbit addition unit 361 selection unit 400 filter coefficient control unit 401 filter coefficient ROM unit 402 reception ROF unit 410 timing phase extraction unit 411, 412 BPF unit 413, 414 PWR unit 415 adder 416 BPF unit (for timing frequency extraction)
420 Vector Conversion Unit 421 Tap Delay Line 422 θ Conversion Unit 430 First Integration Circuit Unit 431 Multiplier 432 Adder 433 Tap Delay Line 434 Multiplier 435 Adder 440 Second Integration Circuit Unit 441 Adder 442 Tap Delay Line 443 Quantization Part 444 Adder (subtractor)
500 reception ROF unit 501 -22.5 degree phase rotation unit 502 counter unit 503 M22.5 degree phase rotation unit 504 multiplier 510 timing phase extraction unit 511, 512 BPF unit 513, 514 vector conversion unit 515, 516 (a + jb) square Part 517 Adder 600 Known point

Claims (4)

In a communication device for filtering transmission signal point information,
A signal point converter for converting the transmission signal point information into bit information with or without a signal point; and
A plurality of tap delay line units including 1 for inputting the bit information;
A transmission ROF control unit that divides bit information of each tap of the tap delay line unit into a plurality of groups including 1 and generates and outputs the divided division information;
The transmission ROF control unit generates and outputs sampling phase information at the time of filtering, and accesses a plurality of ROM units including 1 based on the division information, the sampling phase information, and bit information of each tap, A plurality of first addition units including 1 for obtaining the output of the ROM unit and adding the output of the ROM unit, a multiplication unit for multiplying the output of the first addition unit by a predetermined coefficient, A second adder for adding;
A communication device characterized in that a reduction in the amount of filtering processing is realized. In a communication device for filtering received signals,
A logarithmic conversion ROM 1 section which virtually adds a DC offset to the received signal and performs logarithmic conversion;
A tap delay line section for time-shifting the output signal of the logarithmic conversion ROM 1 section;
The filter coefficient of the communication device is virtually separated into a sign bit and absolute value information, and the absolute value information is separated into a mantissa part and an exponent part, and the mantissa part is logarithmically transformed, A sign bit, a mantissa information after the logarithmic conversion, and a logarithmic conversion ROM 2 for outputting the exponent information;
A plurality of first adders for adding each tap data of the tap delay line and the logarithm converted mantissa information corresponding to each tap data;
A logarithmic inverse transformation ROM 3 for inversely transforming the result of the first adder; and a plurality of bit shifter / polarity control units for obtaining linear information from the exponent information and the sign bit by using the output of the logarithmic inverse transformation ROM 3 unit; ,
An adding unit for adding output signals of the plurality of bit shifters / polarity control units;
A second adder that subtracts a value corresponding to the virtually added DC offset from the output of the adder;
The communication apparatus according to claim 1, wherein the processing result is reduced by using the result of the second adder as an output of the filtering.   Extracts 1/2 Nyquist frequency components at a sampling frequency that is twice the Nyquist frequency, secures the data in the logarithmic conversion ROM 2 for a desired number of timing phases, and makes it possible to finely control the time phase of the filtering. The communication apparatus according to claim 2, wherein synchronization is realized. In a communication device that transmits and receives start-stop data with a start / stop bit,
An ST / SPbit deletion unit that generates transmission data from which the start / stop bit has been deleted and generates a no-transmission signal when there is no transmission data;
A transmission encoding unit for encoding the transmission data;
A signal point generator for generating signal point information including an origin by the transmission encoding unit and the non-transmission signal;
An origin detection unit that receives the signal point information and detects an origin signal;
An origin removing unit for removing the origin signal detected by the origin detecting unit;
Based on the output signal from the origin removing unit, a reception encoding unit that performs reception encoding opposite to the transmission encoding unit,
ST / SPbit addition for adding the start / stop bit deleted on the transmission side to the output of the reception encoding unit and mark-holding the output data of the reception encoding unit when the origin signal is detected And
The communication apparatus according to claim 1, wherein an effective speed of the start data is maintained.

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