JPH0715283A - Digital filter - Google Patents

Abstract

PURPOSE:To enlarge an applied range with simple configuration by providing a multiplier for the high-order bit of a coefficient, delay element and signal switching means for switching the connection of them, and providing an output signal for which the main part of the coefficient is calculated by the multiplier for high-order bit corresponding to the selection of the signal selecting means. CONSTITUTION:For example, the coefficient to be dealt with the low-order coefficient of 6 bits is set to multipliers ML1-MLn for low-order bit and when it can not be dealt with by the multiplier for 6 bits, the high-order coefficient is set to multipliers MH1-MHm for high-order bit and connected with a desired tap. When a number (n) of taps is 512 and a number (m) of multipliers for high-order bit is 64, concerning digit matching at an adder A, a final step output (a) of an adder for high-order bit is 19 bits adding 6 bits corresponding to the number of multipliers for high-order bit to 8 bits + 5 bits =13 bits outputted from the multiplier for high-order bit and a final step output (b) of an adder for low-order bit is 23 bits adding 9 bits to the 8 bits + 6 bits = 14 bits but a filter output C is 24 bits finally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a plurality of delay elements to obtain a digital signal for obtaining a combined output signal of a plurality of delay signals having different delay times by varying the signal levels of the respective delay signals. The present invention relates to a filter, and in particular, to a digital filter with a small hardware and a wide range of application.

[0002]

2. Description of the Related Art Finite Impulse Respons suitable for use in a ghost canceller.
(e, FIR) filter is disclosed by the applicant in JP-A-5-14.
At 130, an FIR filter as shown in FIG. 1 is proposed.

In FIG. 1, a total of n-1 delay elements D are provided.
1 to Dn-1 are connected in series, and a total of n taps T1 to T1 to obtain delay signals of various delay times are provided at each connection portion.
It has Tn.

On the other hand, on the output side of this filter, there are m (m <n) number of multipliers M1 to M smaller than the number n of taps.
m is provided. As the multipliers M1 to Mm,
For example, if the data is 8 bits and the coefficient is 10 bits,
× 10 bits are used. This multiplier M1
The outputs from .about.Mm are sequentially added by the adders A1 to Am-1 and become the output of the FIR filter.

A switch matrix S is provided between the taps and the multiplier so that the connection between each tap and the multiplier can be defined.

When this FIR filter is used in, for example, a ghost canceller or an echo canceller, among the coefficient values corresponding to the tap (delay time) as shown in FIG.
It was devised by paying attention to the fact that there are many zeros. Even with a smaller number of multipliers than the number of delay elements, a wide range of delay times and signal levels can be selected to synthesize output signals. It has characteristics.

In the case of a ghost canceller, for example, the FIR filter 10 is provided in a feedback loop as shown in FIG. 3, and has an infinite impulse response (Infinite I) as a whole.
mpulse Response (IIR) filter is often used.

[0008]

However, in general I
As shown in FIG. 4, when a small ghost (grandchild ghost) is newly generated by the FIR filter provided in the preceding stage of the IR filter, as shown in FIG. As shown in FIG. 5, when a coefficient is required or in general application such as waveform equalization or filtering, there is a problem that it may not be possible to cope with the case where the coefficient is required as a whole.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a digital filter having a wide range of application with a small amount of hardware.

[0010]

According to the present invention, a plurality of delay elements are used to obtain an output signal in which a plurality of delay signals having different delay times are combined with different signal levels of the respective delay signals. In the digital filter of, corresponding to all of the delay elements, a plurality of multipliers for coefficient lower-order bits capable of converting the input signal level to a desired signal level, and corresponding to a part of the delay elements, A plurality of multipliers for coefficient high-order bits capable of converting an input signal level to a desired signal level; signal selection means for switching and selecting connection between the partial delay elements and the high-order bit multipliers; A means for synthesizing an operation result by the lower-order bit multiplier and an operation result by the higher-order bit multiplier is provided, and the main part of the coefficient is multiplied by the upper-order bit by switching selection of the signal selecting means. In so as to obtain a computed output signal is obtained by achieving the above objects.

The plurality of delay elements are connected in series,
When each connection portion is provided with a tap for obtaining a delay signal of each delay time, each output of the lower-order bit multiplier is added by an adder to obtain an output signal of the digital filter, and the signal The selecting means switches and selects the connection between the plurality of taps and the input of the higher-order bit multiplier.

Whether the signal selecting means is provided between each of the plurality of taps and the input of the higher-order bit multiplier, and the corresponding tap is turned on to the input side of the corresponding higher-order bit multiplier. A switch for turning off or switching, and an adder for adding a signal on the side of the higher-order bit multiplier of the switch and an output of another signal selection means are provided, and an input for one higher-order bit multiplier is provided. When the switches of the plurality of signal selecting means are turned on, the signals from the taps corresponding to these signal selecting means are added and input to the high-order bit multiplier.

Further, an input signal of the digital filter is input to each of the upper-order bit multipliers, and the plurality of delay elements injects the lower-order bit multiplier outputs and synthesizes the plurality of adders. In addition, the signal selecting means switches and selects between the output of the higher-order bit multiplier and one input of the adder when they are alternately connected in series. is there.

Further, a plurality of multipliers for medium-order coefficient bits, which are smaller in number than the multipliers for lower bits and capable of converting the input signal level to a desired signal level, corresponding to some of the delay elements. , A signal selecting means for the middle order bit, which switches and selects a connection between the partial delay element and the middle order bit multiplier, the lower order bit multiplier, the middle order bit multiplier and the upper order bit The above-mentioned object is also achieved by including means for synthesizing the calculation result by the multiplier.

[0015]

According to the present invention, in any application of the digital filter, the number of taps requiring a large coefficient is small, and in many applications, the power of the output signal is larger than the power of the input signal. It will never happen, so
Assuming that each coefficient is Ci and the maximum value is 1, as shown in the following equation,
This is done by paying attention to the fact that the sum of the coefficients or the sum of the absolute values of the coefficients is 1 or less.

[0016]

[Equation 1]

That is, according to the present invention, the multiplier is divided into, for example, two stages for upper bits and lower bits, the lower bit multipliers are connected to all taps, and only the upper bit multipliers and the switch matrix are connected. Connect to the required taps by signal selection means such as.

It should be noted that, compared with the conventional example shown in FIG. 1, the hardware is increased by the amount of the lower bit multiplier, but the upper bit multiplier is about half the number of bits. The number of hardware for each bit is halved, and most of the coefficient calculations are performed by the multiplier for the lower bit, so that the number of multipliers for the upper bit is smaller than that of the prior art. Furthermore, the hardware of the switch matrix is reduced because it is necessary to connect only the multiplier for the high-order bit.

The number of divisions of the multiplier is not limited to two stages, one for upper bits and the other for lower bits. One or more stages of multipliers for middle bits are provided between the upper bits and the lower bits to perform multiplication. The vessel may be divided into three or more stages.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings.

The first embodiment of the present invention is as shown in FIG.
N in series with each other, delaying the input signal
-1 delay elements D1 to Dn-1 and n taps T1 to extract signals with different delay times before and after each delay element
Tn, lower bit multipliers ML1 to MLn connected to all taps for calculating the filter output for the lower bit of the coefficient, and lower bit adder AL1 for sequentially adding the output of each lower bit multiplier ~ ALn-1 and the filter output for the upper bits of the coefficient,
A smaller number of upper bit multipliers MH1 to MHm (m <n) than the lower bit multipliers, a switch matrix SM for connecting each upper bit multiplier to a desired tap, and an upper bit multiplier High-order bit adders AH1 to AHm-1 for sequentially adding the outputs, the final-stage (AHm-1) output a of the high-order bit adder, and the last-stage (ALn-1) of the low-order bit adder. ) Adder A for synthesizing output b into filter output c.

For example, the data is 8 bits and the original coefficient is 1.
In the case of 0 bit, as shown in FIG. 7, the upper coefficient including the sign bit S is divided into 5 bits, the lower coefficient is divided into 6 bits, the upper bit multiplier is 8 × 5 bits, and the lower bit multiplier is It can be 8 × 6 bits. Here, the sign bit is provided to the lower coefficient because the coefficient is represented by a two's complement.

As a concrete structure of the switch matrix SM, for example, the structure proposed by the applicant in JP-A-5-14130 can be used.

The operation of the first embodiment will be described below.

In using the filter, according to the coefficient distribution as shown in FIG. 4 or 5, the lower bit multiplier ML1 is used for the coefficient that can be handled only by the lower coefficient of 6 bits, for example. To MLn, respectively. On the other hand, when the coefficient value is relatively large and cannot be handled by the 6-bit lower bit multiplier, for example, 5
The high-order coefficient that has been made into bits is the multiplier MH for the high-order bits.
It is set to 1 to MHm and is connected to a desired tap by the switch matrix SM so that a desired delay time can be obtained.

The digit alignment at the time of addition in the adder A is
For example, it is performed as shown in FIG. That is, for example, when the number of taps n = 512 and the number of multipliers for upper bits m = 64,
The output a of the final stage (AHm-1) of the high-order bit adder is 8 bits + 5 of the high-order bit multiplier output, as shown in FIG.
Bit = 13 bits, the number of multipliers for upper bits (64
Since it becomes 19 bits by adding 6 bits corresponding to (number), it is shifted to the left by 5 bits in order to correspond to the higher order. On the other hand, the final stage of the low-order bit adder (ALn-1)
The output b is 23 bits obtained by adding 9 bits corresponding to the number of lower bit multipliers (= 512 taps) to the 8 bits + 6 bits = 14 bits of the lower bit multiplier output, To extend. Finally, the filter output c of the output of the adder A is 24 bits including the sign bit S.

Next, the second embodiment of the present invention will be described in detail.

In the second embodiment, as shown in FIG. 9, the switch matrix SM of the first embodiment is provided with an adder matrix A in which an adder a is provided at each intersection of each switch.
It is replaced with M.

According to this embodiment, different taps T1 ...
Since the output of Tn can be added by the adder a in the adder matrix AM and output to the corresponding high-order bit multipliers MH1 to MHm, if there are multiple taps to which the same coefficient is assigned, It is possible to reduce the number of high-order bit multipliers used for the coefficients, and it is possible to reduce the number of high-order bit multipliers as a whole.

Since the other points are the same as those of the first embodiment, the description thereof will be omitted.

In each of the above-mentioned embodiments, the output of the high-order bit multiplier and the output of the low-order bit multiplier are added together at the end, so that only one digit alignment is required at the time of addition. The calculation is relatively simple.

Next, a third embodiment of the present invention will be described in detail with reference to FIG.

The third embodiment corresponds to the transposed type of the first embodiment. In this embodiment, the upper bit multipliers MH1 to MHm and the lower bit multipliers ML1 to MLn are used.
Are both directly connected to the input, and the lower bit multiplier ML
The outputs of 1 to MLn and the outputs of the high-order bit multipliers MH1 to MHm via the switch matrix SM are added by the adders A1 to An, and then the delay elements D1 to Dn- are added.
The output of each delay element D1 to Dn-1 input to 1 is sequentially added to produce an output.

Since the setting method of the switch matrix SM and the like are the same as those in the first embodiment, the description thereof will be omitted.

In this embodiment, as shown in FIG.
Digit matching is performed by the adder of each stage, and the number of bits is sequentially increased as the addition is performed, and the sign bit S is also expanded accordingly.

That is, in the first-stage adder A1, an upper signal of 8 bits + 5 bits = 13 bits output from the output terminal 1 of the switch matrix SM and an 8 bit + 6 output from the lower bit multiplier ML1. The lower signal of bit = 14 bits is added, and the sum signal of 18 bits is output to the delay element D1.

Next, in the second-stage adder A2, the 13-bit upper signal output from the output terminal 2 of the switch matrix SM, the 14-bit lower signal output from the lower bit multiplier ML2, The output of the delay element D1 is added and the sum signal of 19 bits is output to the delay element D2 of the next stage.

After that, this digit alignment is repeated until finally, for example, n = 512, m = from the adder An at the final stage.
When it is 64, a 24-bit signal is output.

According to this embodiment, the number of adders may be small.

In each of the above embodiments, the multiplier is divided into two stages, one for the upper bits and the other for the lower bits. However, the number of divisions of the multiplier is not limited to this, for example, as shown in FIG. As in the fourth embodiment shown, one stage (in the case of the fourth embodiment) or two or more stages of intermediate-order bit multipliers MM1 to MMp (p <n) are provided between the upper bits and the lower bits. , Can be further divided.

In FIG. 12, SMm is a switch matrix for medium bits, AM1 to AMp-1 are adders for medium bits, and am is the final stage (A of the adders for medium bits).
Mp-1) output.

In the above embodiments, the present invention was applied to the ghost canceller, but the scope of application of the present invention is not limited to this, and other general applications such as echo canceller, waveform equalization filtering, etc. It is clear that it can also be applied to.

[0043]

As described above, according to the present invention,
A digital filter having a wide range of application can be configured with a small amount of hardware, which has an excellent effect of cost reduction and power consumption reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional digital filter proposed by the applicant in JP-A-5-14130.

FIG. 2 is a diagram showing a distribution of tap coefficients suitable for using the conventional example.

FIG. 3 is a block diagram for explaining a usage state of the conventional ghost canceller.

FIG. 4 is a diagram showing an example of tap coefficients with noise on the whole.

FIG. 5 is a diagram showing an example of tap coefficients in the case of a general application in which all coefficients are attached.

FIG. 6 is a block diagram showing the configuration of the first embodiment of the present invention.

FIG. 7 is a diagram showing a coefficient dividing method in the first embodiment.

FIG. 8 is a diagram showing a method of aligning digits during addition as well.

FIG. 9 is a diagram showing an example of an adder matrix used in the second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 11 is a diagram showing digit alignment in an adder of each stage in the third embodiment.

FIG. 12 is a block diagram showing a configuration of a fourth embodiment of the present invention.

[Explanation of symbols]

 D1 to Dn-1 ... Delay element T1 to Tn ... Tap SM, SMm ... Switch matrix ML1 to MLn ... Lower bit multiplier AL1 to ALn-1 ... Lower bit adder MH1 to MHm ... Upper bit multiplier AH1 to AHm-1 ... Adder for upper bits A, a, A1 to An ... Adder AM ... Adder matrix MM1 to MMp ... Multiplier for middle order bits AM1 to AMp-1 ... Adder for middle order bits

Claims (5)

[Claims] 1. A digital filter for using a plurality of delay elements, wherein a plurality of delay signals having different delay times are combined by varying the signal levels of the respective delay signals to obtain an output signal. Corresponding to all of the above, a plurality of multipliers for lower coefficient bits capable of converting the input signal level to a desired signal level, and corresponding to a part of the delay element, the input signal level to a desired signal level. A plurality of multipliers for coefficient high-order bits, signal selection means for switching and selecting connection between the some delay elements and the high-order bit multipliers, operation results by the low-order bit multipliers And a means for synthesizing the operation result by the high-order bit multiplier, the output signal in which the main part of the coefficient is operated by the high-order bit multiplier by switching selection of the signal selecting means. Digital filter, characterized in that to obtain. 2. The plurality of delay elements are connected in series, each connection portion is provided with a tap for obtaining a delay signal of each delay time, and each output of the lower bit multiplier is A digital filter, which is added by an adder to be an output signal of a digital filter, and wherein the signal selecting means switches and selects a connection between the plurality of taps and an input of the multiplier for upper bits. 3. The signal selection means according to claim 2, wherein the signal selection means is provided between each of the plurality of taps and the input of the higher-order bit multiplier, and the corresponding tap is input to the corresponding higher-order bit multiplier. A switch for turning on or off to the side, and an adder for adding the signal on the higher bit multiplier side of the switch and the output of another signal selection means, and for one high bit When the switches of the plurality of signal selecting means are turned on with respect to the input of the multiplier, the signals from the taps corresponding to these signal selecting means are added,
A digital filter which is input to the multiplier for upper bits. 4. The input signal of a digital filter is input to each of the higher-order bit multipliers, and the plurality of delay elements injects and combines the lower-order bit multiplier outputs. And a plurality of adders of the same are alternately connected in series, and the signal selection means switches and selects between an output of the higher-order bit multiplier and one input of the adder. Digital filter that does. 5. The coefficient medium-order bit according to claim 1, further comprising, corresponding to a part of the delay element, a smaller number of coefficient medium-order bits than the lower-bit multiplier capable of converting an input signal level to a desired signal level. A plurality of multipliers for use, a signal selecting means for the middle-order bits for switching and selecting the connection between the partial delay element and the multiplier for the middle-order bits, the multiplier for the lower-order bits, the middle-order bits Filter and a means for synthesizing operation results by the high-order bit multiplier.