JPH05315892A - Digital filter - Google Patents

Abstract

PURPOSE:To obtain a digital filter whose circuit scale is remarkably reduced while securing the same characteristic as that of a conventional filter. CONSTITUTION:Input data are inputted to mXn-stages of shift registers 210, 220, 230, 240 and a tap is extracted for each of n-stages from an output of the shift registers and all tap data are added via multipliers 212, 222, 224, 232 whose sign is changed at an interval and whose coefficients are binomial coefficients. The order of the addition takes precedence of data of taps having the same coefficient over others and then the addition of data of same degree and having required word length is implemented. The result of addition is inputted to an m-degree of integration devices 250, 260, 270, 280 and output data are extracted from outputs of the integration devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used in the field of digital audio, for example.

[0002]

2. Description of the Related Art A conventional digital filter has m n-stage shift registers, and each n-stage shift register constitutes a comb filter for subtracting output data from respective input data. There has been a configuration in which the output data of the m-th comb filter is connected in series, input to an m-th order integrator, and the output is taken out from this integrator.

A description will be given below with reference to the drawings. FIG. 4 is a block diagram of a conventional digital filter, where m = 4.
It is what In FIG. 4, 401 is a data input terminal, 402 is a data output terminal, 410 is a first comb filter, 411 is a first shift register that constitutes the first comb filter 410, and 412 is a first comb filter. A first subtractor constituting 410, similarly 420 is a second comb filter, 421 is a second shift register, 4
22 is a second subtractor, 430 is a third comb filter, 4
31 is a third shift register, 432 is a third subtractor,
440 is a fourth comb filter, 441 is a fourth shift register, and 442 is a fourth subtractor. Reference numeral 450 is a first integrator, 451 is a first register forming the first integrator 450, and 452 is a first register forming the first integrator 450.
, 460 is a second integrator, 461 is a second register, 462 is a second adder, 470 is a third integrator, 471 is a third register, and 472 is a third register. An adder, 480 is a fourth integrator, 481 is a fourth register,
482 is a fourth adder. First comb filter 41
The 0 input is connected to the input of the first shift register 411 and is connected to the positive side input of the first subtractor 412. The output of the first shift register 411 is connected to the negative side input of the first subtractor 412, and the output of the first subtractor 412 is taken out as the output of the first comb filter 410. Second comb filter 420 to fourth comb filter 4
40 is similarly constructed. The input of the first integrator 450 is connected to one input terminal of the first adder 452,
The output of the first register 451 is input to the other input terminal of the first adder 452. The output of the first adder 452 is connected to the input of the first register 451 and is taken out as the output of the first integrator 450. The second integrator 460 to the fourth integrator 480 are similarly configured.
The first comb filter 410 to the fourth integrator 480 are connected in series to form a digital filter.

[0004] Each transfer function Hc of the first comb filter 410 to a fourth comb filter 440 (Z), expressed one sample time delay between ^Z-1,

[0005]

[Equation 1]

[0006] Similarly, the first integrator 450 to the fourth
The transfer function Hi (Z) of each integrator 480 of

[0007]

[Equation 2]

[0008] Therefore, the transfer function H (Z) of the whole digital filter is

[0009]

[Equation 3]

And has a low-pass characteristic.

[0011]

However, in the conventional configuration, since a plurality of comb filters are connected in series, the word length of the shift register increases toward the latter stage, and the total number of registers is increased. Will increase. In addition, the word length of the subtractor forming the comb filter also increases toward the subsequent stage. For example, when the input word length of the filter is 2 bits, the word length of each shift register and subtractor increases as shown in (Table 1) (however, when the LSB of all output patterns is 0, the LSB is omitted. , Redundant bits are omitted.).

[0012]

[Table 1]

For example, when the number of stages n of the shift register is 32, the total number of registers N _R is (Equation 4) and the total number of subtractors N _S is (Equation 5).

[0014]

[Equation 4]

[0015]

[Equation 5]

The present invention has been made in view of the above problems, and an object of the present invention is to provide a digital filter which can obtain the same characteristics with a smaller number of registers and subtractors.

[0017]

In order to achieve this object, the digital filter of the present invention has m × n stages of shift registers and m + 1 extracted from the input of the shift register and the register output of every n stages. M + 1 multipliers that multiply the tap data by a coefficient whose magnitude changes to a binomial coefficient, an adder that adds all the output data of the multipliers, and the addition And an m-th order integrator that receives the output data of the integrator, inputs the input data from the input terminal of the shift register, and extracts the output data from the output terminal of the integrator (first Constitution).

Further, the multiplier and the adder are composed of a bit shifter and an adder / subtractor (second structure).

Further, the adder is constructed so as to give priority to the addition / subtraction operation of tap data having the same coefficient size (third configuration).

Further, the adder is configured so that the addition / subtraction calculation of the absolute values of the addition / subtraction calculation results of the tap data having the same coefficient size and the ones having a required word length are preferentially performed next. ing. (Fourth configuration).

[0021]

The present invention has the above-described structure. (1) In the first structure, since the word length of the shift register is the same as the word length of the input data, the number of shift registers can be reduced and the circuit scale can be reduced. Can be planned.

(2) In the second configuration, since the multiplier is realized by bit shifting, the filter can be configured without adding physical hardware.

(3) In the third and fourth configurations,
Redundant word lengths are configured because priority is given to taps that perform multiplication by the same coefficient, and then addition and subtraction operations are performed with priority on those that are close in absolute value and the required word length of the operation result. Can be prevented, and the number of adders / subtractors can be reduced.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a digital filter according to the first embodiment of the present invention, in which m is the same as in the conventional example.
= 4.

In FIG. 1, 101 is a data input terminal, 102 is a data output terminal, 110 is a first shift register, 111 is a fifth subtractor, 112 is a first multiplier, and 120 is a second. Shift register, 121 is a fifth adder, 122 is a second multiplier, 123 is a sixth adder,
124 is a third multiplier, 130 is a third shift register, 131 is a sixth subtractor, 132 is a fourth multiplier, 1
40 is a fourth shift register, 141 is a seventh adder,
Reference numeral 150 is a first integrator, 151 is a first register that constitutes the first integrator 150, and 152 is a first integrator 150.
, 160 is a second integrator, 161 is a second register, 162 is a second adder,
170 is a third integrator, 171 is a third register, 17
Reference numeral 2 is a third adder, 180 is a fourth integrator, 181 is a fourth register, and 182 is a fourth adder.

The input terminal 101 is the first shift register 1
10 and the positive side input of the fifth subtractor 111. The output data of the first shift register 110 is input to the second shift register 120 and the negative side input of the fifth subtractor 111 via the first multiplier 112. The output of the fifth subtractor 111 is connected to one input terminal of the fifth adder 121, and the other input terminal of the fifth adder 121 has the second multiplier 122.
The output data of the second shift register 120 is input via the. The output of the second shift register 120 is connected to one input terminal of the sixth adder 123 via the third multiplier 124, and is also connected to the input of the third shift register 130 at the same time. The output of the fifth adder 121 is connected to the other input terminal of the sixth adder 123. Sixth
To the positive input terminal of the subtractor 131 of
Of the fourth multiplier 13 is connected to the negative side input terminal.
The output of the third shift register 130 is connected via 2. The output of the third shift register 130 is simultaneously output to the fourth
Of the shift register 140. The sixth subtractor 131 is connected to one input terminal of the seventh adder 141.
Of the fourth shift register 140 is connected to the other input.

First integrator 150 to fourth integrator 180
Are the same as those of the first to fourth integrators 450 to 480 of the conventional example, and the description thereof will be omitted. The output of the seventh adder 141 is connected to the input of the first integrator 150,
The first to fourth integrators 150 to 180 are connected in series as in the conventional example. An output as a digital filter is taken out from the output terminal 102 from the output of the fourth integrator 180.

The first multiplier 112 to the fourth multiplier 132
The multiplication coefficient of is as shown in (Table 2).

[0030]

[Table 2]

The second multiplier 122 and the third multiplier 124
Originally, one coefficient is multiplied by the same input data, and the coefficient is "6", but it is decomposed into a power of 2 because the multiplier performs bit shift.

The transfer function H (Z) of the digital filter is (Equation 6), which is the same as the transfer function (Equation 3) of the conventional digital filter.

[0033]

[Equation 6]

Since the word length of the register is the same as the input word length, the total number of registers N _R becomes (Equation 7) under the same conditions as in the conventional example, and it can be seen that the number is significantly reduced from the conventional example. ..

[0035]

[Equation 7]

On the other hand, the number N _{S of} adder / subtractors becomes as shown in (Equation 8), which is larger than that of the conventional example. However, when the number of registers is reduced, the circuit scale can be considerably reduced as a whole.

[0037]

[Equation 8]

FIG. 2 is a block diagram of a digital filter according to the second embodiment of the present invention.
= 4.

In FIG. 2, 201 is a data input terminal, 202 is a data output terminal, 210 is a first shift register, 211 is a fifth adder, 212 is a first multiplier, and 220 is a second multiplier. The shift register, 221 is a sixth adder, 222 is a second multiplier, 223 is a seventh adder,
224 is a third multiplier, 230 is a third shift register, 231 is a subtractor, 232 is a fourth multiplier, 240 is a fourth shift register, 241 is an eighth adder, 250
Is a first integrator, 251 is a first register that constitutes the first integrator 250, 252 is a first adder that constitutes the first integrator 250, and similarly 260 is a second integrator. Two
61 is a second register, 262 is a second adder, 270
Is a third integrator, 271 is a third register, 272 is a third adder, 280 is a fourth integrator, 281 is a fourth register, and 282 is a fourth adder.

The input terminal 201 is the first shift register 2
It is connected to 10 inputs and also connected to one input of the eighth adder 241. The output data of the first shift register 210 is input to the second shift register 220 and at the same time passes through the first multiplier 212 to the fifth adder 211.
Is input to one of the input terminals. The output of the fifth adder 211 is connected to the negative side input terminal of the subtractor 231. Second
The output of the shift register 220 is input to one input terminal of the sixth adder 221 via the second multiplier 222, and the eighth adder 241 is input to the other input terminal of the sixth adder 221. The output of is connected. The output of the second shift register 220 is connected to one input terminal of the seventh adder 223 via the third multiplier 224, and the seventh adder 2
The output of the sixth adder 221 is connected to the other input terminal of 23. Further, the output of the second shift register 220 is also connected to the input terminal of the third shift register 230. The output of the third shift register 230 is connected to the fifth adder 211 via the fourth multiplier 232, and is also supplied to the fourth shift register 240. The output of the fourth shift register 240 is the eighth adder 241.
Is connected to the other input terminal of. The output of the seventh adder 223 is input to the positive side input terminal of the subtractor 231, and the output of the subtractor 231 is input to the first integrator 250. First
The integrator 250 to the fourth integrator 280 are configured and connected in the same manner as the first integrator 150 to the fourth integrator 180 in the first embodiment, and the description thereof will be omitted. As the output as the digital filter, the output of the fourth integrator 280 is taken out from the output terminal 202.

FIG. 3 shows a detailed block diagram of the configuration of the multiplication / addition / subtraction unit of the digital filter. Note that the input word length of the filter is 2 bits, and the data is expressed in 2's complement.

In FIG. 3, 301 is the first 3-bit adder, 302 is the second 3-bit adder, 303 is the third 3-bit adder, 304 is the fourth 3-bit adder, and 30.
Reference numeral 5 is a 4-bit subtractor, which corresponds to the fifth adder 211, the eighth adder 241, the sixth adder 221, the seventh adder 223, and the subtractor 231 in FIG. 2, respectively. .. Further, a combination symbol (A0 to S5) of the alphabet and the numbers attached to the input and output of each adder / subtractor corresponds to the signals A to S with the alphabet attached in FIG. 2, and the number is the bit weight 2 ^X ( Power of two). For example, the input B3 is the first signal of the higher-order signal B1 of the 2-bit input signal B.
4 multiplied by the multiplier 212, that is, shifted to the upper side by 2 bits.

Since the data is represented by 2's complement,
When the addition / subtraction result of X bits becomes X + 1 bit,
The most significant bit of the input data is expanded and input to the most significant bit of the adder / subtractor. The signal A and the signal F are input to the eighth adder 302. Sixth adder 303
The output and the 1-bit shift (multiply 2) signal C of the adder 302 of the eighth is input to, since the signal C is not present a bit of weight 2 ^0, the addition calculation of the bits required Is. The seventh adder 304 has a sixth adder 3
The output of 03 and the signal D that has been shifted by 2 bits (multiplied by 4) are input, but since there is no bit with a weight of 2 ¹ or less in the signal D, the addition operation of the bits is unnecessary.

A signal B and a signal E that have been shifted by 2 bits (multiplied by 4) are input to the fifth adder 301. The output of the fifth adder 301 is connected to the negative input terminal of the subtractor 305, and the output of the seventh adder 304 is supplied to the positive input terminal. Since neither the output signal of the fifth adder 301 nor the output signal of the seventh adder 304 has a bit having a weight of 2 ¹ or less, the calculation of the bit is unnecessary.

[0045] Therefore, the output bit S0 of the weights of the 2 ⁰ 8
Fetched least significant bit of the adder 302, the output bits S1 of the weight of 2 ¹ least significant bits of the sixth adder 303 is taken out, the upper bit S2~S5 are taken from the subtractor 305.

In FIG. 3, the number of full adders constituting each adder / subtractor is 16 in total, which is slightly (2
It can be seen that the number is decreasing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital filter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a digital filter according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a detailed configuration of a multiplication / addition / subtraction unit according to the second embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional digital filter.

[Explanation of symbols]

 101, 201 input terminal 102, 202 output terminal 110, 210 first shift register 111 fifth subtractor 112, 212 first multiplier 120, 220 second shift register 121, 211 fifth adder 122, 222 second multiplier 123,221 sixth adder 124,224 third multiplier 130,230 third shift register 131 sixth subtractor 132,232 fourth multiplier 140,240 fourth Shift register 141,223 seventh adder 150,250 first integrator 151,251 first register 152,252 first adder 160,260 second integrator 161,261 second register 162, 262 Second adder 170,270 Third integrator 171,273 Third register 172,272 Third adder Vessels 180 and 280 a fourth integrator 181,281 fourth register 182,282 fourth adder 231 subtractor

Claims (4)

[Claims] 1. A shift register of m × n stages, and m + 1 tap data extracted from the input of the shift register and the register output of each n stages, the code changes for each one, and the magnitude is 2. Multiply the coefficient by m +
An input terminal of the shift register, which includes one multiplier, an adder that adds all output data of the multiplier, and an m-th order integrator that receives the output data of the adder A digital filter characterized in that data is inputted and output data is taken out from an output terminal of the integrator. 2. The digital filter according to claim 1, wherein the multiplier and the adder are constituted by a bit shift and an adder / subtractor. 3. The digital filter according to claim 1, wherein the adder is configured to preferentially perform addition / subtraction calculation of tap data having equal coefficient magnitudes. 4. The adder is configured to perform the addition / subtraction operation by prioritizing those having similar absolute values of the addition / subtraction operation results of tap data having the same coefficient size and the required word length next to each other. The digital filter according to claim 3, wherein: