JPH06152330A - Digital filter - Google Patents

Abstract

PURPOSE:To execute much calculation within a fixed time and to improve the order of filters by providing a digital filter with a switching function for switching the upper and lower bits of an accumulator and a timing generating circuit for generating the timing of the switching function. CONSTITUTION:The digital filter having 16 bits for data and 16 bits for coefficients, for example, is provided with a RAM 1 having 16-bit width, 16-bit register 2 for storing data for a fixed time, an 8-bit width ROM 3 for storing the coefficient of a filter, an 8-bit register 4 for storing data for a fixed time, and a multiplier 5 consisting of 16 bits X 8 bits. The input/output of an accumulator show whether the lower 25 bits of the accumulator are to be selected or upper 8 to 32 bits are to be selected and show whether the output of an adder 7 is to be inputted to the lower 24 bits or upper 8 to 32 bits of the accumulator 9 in a switching circuit 8. When all upper bits are '0' or '1', processing can be completed only by one multiplication.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter, and more particularly to a digital filter having a FIR filter circuit.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, a digital filter of this type has a delay RAM 20 for delaying input data, a register 21 for receiving output data of the delay RAM 20, and a coefficient for outputting a coefficient. ROM22
And a register 23 that receives the output data of the coefficient ROM 22, a multiplier 24 that receives the output of the register 21 and an output of the register 23, and an adder 25 that receives the output of the multiplier 24 and the output of the accumulator 26. And adder 2
It has an accumulator 26 which receives the output of 5 as an input, an output circuit 27 which receives the output of the accumulator 26 as an input, and a timing generation circuit 28 which creates the timing of the registers 21 and 23.

Next, the operation of the digital filter when the data is 16 bits and the coefficient is 16 bits as shown in Table 1 will be described. First, 16-bit data is sequentially read from the delay RAM 20 as D (12), D (11) ... And held in the register 21. On the other hand, from the coefficient ROM, the 16-bit coefficients in Table 1 are C (12) and C (11).
Are sequentially read and stored in the register 23. The timings are adjusted by the registers 21 and 23 and input to the 16-bit × 16-bit multiplier 24. The output of the multiplier 14 is D (12) × C (12), D (11) × C (1
1) ... D (-12) * C (-12). Multiplier 24
Is output to the 32-bit adder 25 and added to the output of the accumulator 26. First, if the contents of the accumulator 26 are cleared, the adder 2
The output of 5 is Σ {D (k) × C (k)}. In this way, the cumulative addition result is finally stored in the accumulator 26 and output by the output circuit.

[0004]

[Table 1]

[0005]

In the conventional digital filter, when the data is 16 bits and the coefficient is 16 bits, the multiplier is 16 bits × 16 bits and the coefficient ROM is 1 bit.
A capacity of 6 × (number of taps + 1) / 2 is required, and there is a problem that the circuit scale becomes large.

[0006]

A digital filter according to the present invention comprises a data input circuit for inputting digital data at regular time intervals and a delay RA for delaying the input data.
M, a first delay circuit for delaying and outputting the output of the delay RAM for a fixed time, and a coefficient RO having a bit width of (1/2 of coefficient bit number) to (coefficient bit number -1)
M, a second delay circuit that delays and outputs the output of the coefficient ROM for a fixed time, a multiplier, a first switching circuit, a second switching circuit, an adder, an accumulator, and timing generation. A circuit and an output circuit, the output of the input circuit is input to the RAM, the output of the RAM is input to the first delay circuit, and the output of the ROM is input to the second delay circuit, Outputs of the first delay circuit and the second delay circuit are input to the multiplier, outputs of the first adder are input to the multiplier,
The output of the coefficient ROM is input to the multiplier, the output of the multiplier is input to one of the adders, and the output of the adder is input to the first switching circuit.
The output of the switching circuit is input to the accumulator, the output of the accumulator is input to the second switching circuit, the output of the second switching circuit is input to one of the adders, and the output of the timing generation circuit. Is a configuration input to the first delay circuit, the second delay circuit, the first switching circuit, and the second switching circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a digital filter according to a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a block diagram of the digital filter of the first embodiment of the present invention, the digital filter of this embodiment has 16 bits of data, 16 bits of coefficient, and a bit for storing a digital data input. A 16-bit wide RAM 1, a 16-bit register 2 that receives the output of the RAM 1 and holds it for a certain period of time, an 8-bit wide ROM 3 that stores filter coefficients,
An 8-bit register 4 that receives the output of the ROM 3 and holds it for a certain period of time, a 16-bit × 8-bit multiplier 5, an accumulator 9 that accumulates addition results, and a switching circuit 6 that switches the lower bits of the upper bits of the accumulator 9 , A 25-bit adder 7 that receives the output of the multiplier 5 and the output of the switching circuit 6, and whether the output of the adder 7 is input to the lower 25 bits of the accumulator 9 or the 9th to 32nd bits. It is composed of a switching circuit 8, a switching circuit 6 for switching between the registers 2 and 4, and a timing generation circuit 11 for timing the timing of the alarm circuit 8.
The operation of the digital filter of this embodiment will be described with reference to FIG.

The output DO to be calculated is DO = Σ {D (k) × C (k)} (k = -12, -1
1, -10 ... 10, 11, 12).

First, FIG. 3 will be described. Register 4 (R
OM output) is the contents of register 4 in FIG.
Represents the coefficient data output of. Register 2 (data) is shown in Figure 1.
The content of the register 2 indicates the data read from the RAM. The multiplier represents the output of the multiplier 5 of FIG. The next accumulator input / output indicates whether the lower 25 bits of the accumulator 9 or the upper bits of 8 to 32 are selected by the switching circuit 6, and the output of the adder 7 is switched to the lower 24 bits of the accumulator 9 by the switching circuit 8. It indicates whether to input or to input to upper bits of 8 to 32.
The 1st, 3rd and 4th rows are the case of the lower 24 bits and are 2, 6, 8
The row is for the upper bits of 8 to 32.

[0011]

[Table 2]

First, 16-bit data D (12) is read from the RAM 1. This data is temporarily held in the register 2. On the other hand, the ROM 3 holds the data as shown in Table 2. First, the lower 8 bits of C (12) are read and temporarily stored in the register 4. In this embodiment, the coefficient data is D4.

The lower 8 bits of this C (12) are set to C (12
L) and the upper 8 bits are represented as C (12U).
Since the outputs of the registers 2 and 4 are multiplied by the multiplier 5, the multiplication result is D (12) × C (12L). This output is input to the adder 8 and added together with the lower 24 bits of the accumulator 9. Here, if the contents of the accumulator 9 are cleared first, the output of the adder 8 is the multiplication result itself, and D (12) × C (12L) is also stored in the lower order of the accumulator 9.
Next, the contents of the register 2 are held and the contents of the ROM 3 to the C
(12U) is read and temporarily stored in the register 4. The multiplication result is D (12) × C (12U). This multiplication result is added by the adder 8 together with the upper bits (9 bits to 32 bits) of the accumulator 9 selected by the switching circuit. The output of the adder 8 is D (1
2) × C (12) 9 bits to 32 bits, and the switching circuit 8 causes the accumulator 9 to 9 bits to 32 bits.
It becomes a bit and is held by the switching circuit 8 in the 9th bit to the 32nd bit of the accumulator 9.

Next, the lower 8 bits of C (11) are read from the ROM 3 at the same time when the RAM 1 is read from the RAM 11) and held in the register 2 and the register 4, respectively. The outputs of the registers 2 and 4 are multiplied by the multiplier 5, and the output result is D (11) × C (11L). This output is input to the adder 7 together with the lower 24 bits of the accumulator 9, and the output of the adder 8 is D (12) × C (12) −D (11) × C (11L). Since the coefficient C (11) is (007F) H and the upper 8 bits are all 0, D (11) × C (11L) = D (11) × C (11), and the output of the adder 7 is D (12) × C (12) + D (11) × C (11). Thus, for coefficients whose upper 8 bits are all 0s or 1s, cumulative addition of only lower bits is performed, and for other coefficients, by continuing cumulative addition of lower multiplication results and upper multiplication results. DO = Σ {D (k) × C (k)} (k = -12, -1
1, -10 ... 10, 11, 12) can be obtained.

Next, a digital filter according to a second embodiment of the present invention will be described with reference to the drawings. The digital filter of this embodiment has 16 bits of data and 16 coefficients.
Although it has bits, the number of bits of each of the multiplier 3 coefficient ROM and the adder is different from that of the first embodiment. The digital filter according to the second embodiment is a ROM 53 having a bit width of 10 bits which stores filter coefficients.
, A 16-bit × 10-bit multiplier 55, a reference numeral 7 has an output of the multiplier 5, a switching circuit, and a 27-bit adder 77 having the output as an input. Other than that, the configuration is the same as that of the first embodiment. Yes Same components are referenced first.

[0016]

[Table 3]

Using such ROM data, the output DO is DO = Σ {D (k) × C (k)} (k = -12, -1) as in the first embodiment.
1, -10 ... 10, 11, 12) can be obtained. In the case of the second embodiment, the number of bits of the multiplier, the coefficient ROM, and the adder is larger than that of the first embodiment, but there is an advantage that the number of operations can be increased.

[0018]

As described above, since the digital filter of the present invention performs multiplication in two times, the number of bits of the multiplier and the adder can be reduced as compared with the conventional one, and the upper bits and lower bits of the accumulator can be reduced. Since it has a switching function for switching and a timing generation circuit that creates its timing, when the upper bits are all 0s or 1s, the multiplication can be completed once and many calculations can be performed within the same time, that is, the filter. Has the advantage that the order of can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital filter according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a filter using FIG.

FIG. 3 is a calculation routine of a filter of the present invention.

FIG. 4 is a block diagram of a conventional digital filter.

FIG. 5 is a block diagram of a digital filter according to a second embodiment of the present invention.

[Explanation of symbols]

 1,20 Delay RAM 2,21 Register 3,22,53 Coefficient ROM 4,23 Register 5,24,55 Multiplier 6 Switching circuit 7,25,77 Adder 8 Switching circuit 9,26 Accumulator 10,27 Output circuit 11, 28 Timing generation circuit

Claims (1)

[Claims] 1. A data input circuit for inputting digital data at fixed time intervals, a delay RAM for delaying input data, and a first delay circuit for delaying and outputting the output of the delay RAM for a fixed time. , (1 / the number of coefficient bits
2) to (coefficient bit number-1), a coefficient ROM, a second delay circuit that delays the output of the coefficient ROM for a predetermined time, and outputs the multiplier, a multiplier, and a first switching circuit. , A second switching circuit, an adder, an accumulator, a timing generation circuit, and an output circuit,
The output of the input circuit is input to the RAM and the RA
The output of M is input to the first delay circuit, and the ROM
Is input to the second delay circuit, outputs of the first delay circuit and the second delay circuit are input to the multiplier, and outputs of the first adder are input to the multiplier. The output of the coefficient ROM is input to the multiplier, the output of the multiplier is input to one of the adders, and the output of the adder is input to the first switching circuit. The output of the switching circuit is input to the accumulator, the output of the accumulator is input to the second switching circuit, the output of the second switching circuit is input to one of the adders, and the output of the timing generation circuit is A digital filter which is inputted to the first delay circuit, the second delay circuit, the first switching circuit and the second switching circuit.