JPS6113707A - Digital filter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a digital filter by selecting output signals of plural bit shift circuits and using the product of the number of taps of the shift registers and the mean value of the number of significant bits of each tap coefficient of the shift registers as the number of inputs of an adder. CONSTITUTION:The input data is supplied to an input terminal 1, and a shift register 2 is formed by the cascade connection of registers of five stages. The taps of the register 2 are connected to the input terminals of shift circuits 3-7 respectively. The circuit groups 3 and 7 consist of two-bit shifters together with circuit groups 4 and 6 consisting of four-bit shifters and a circuit group 5 consisting of six-bit shifters respectively. Each shifter is multiplied by a coefficient of the power square of 2 or one-to-power square of 2. The total I pieces of output lines of circuit groups 3-7 are connected to the horizontal input signal lines of a switch matrix 8. While J pieces of vertical signal lines are connected to an adder 9, and the product of the number of significant bits of the coefficient of each tap of the register 2 and the number of taps is defined as the number of inputs of the adder 9. In such a way, the circuit scale can be reduced for a digital filter.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a FIR type digital filter.

[Background technology and its problems]

In the case of N taps, the FIR digital filter has y, l-
It performs the calculation Σ(Xl, y.×h,) t1. In the above equation, x and l are input samples, Yn is an output sample, and h is an impulse response (referred to as a coefficient). When constructing this FIR digital filter, a multiplier is used for multiplication of coefficients, but the multiplier has a problem of large circuit scale and cost.

Therefore, we used a power of 2 structure or a simple number of 1 divided by a power of 2 as coefficients, realized the hardware of a digital filter by using a bit shift circuit (no parts required, just wiring) and addition, and used a multiplier. The use of such materials is being avoided.

Such digital filters are circuits designed for each filter characteristic, and are not versatile.

In particular, when converting into an IC, an IC board must be created for each filter characteristic, which is troublesome in terms of maintenance as each circuit is different.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a highly versatile digital filter that does not require expensive and large-circuit multipliers and can realize multiple filter characteristics with a single piece of hardware. It is about providing. The digital filter according to the present invention has the above-mentioned versatility and is therefore suitable for integration into an IC circuit.

[Summary of the invention]

The present invention provides a shift register to which an input digital signal is supplied, and two outputs of a plurality of taps of the shift register.
This digital filter includes a plurality of bit shift circuits for multiplying by a power structure or a coefficient of 1/2 and an addition circuit for adding the outputs of the plurality of bit shift circuits and generating an output.

In the present invention, each of the plurality of bit shift circuits is configured as a shift circuit group including a plurality of bit shifters, and output signals of the plurality of bit shifters are selected by a selection circuit and supplied to the adder as an output of the shift circuit group, This digital filter is characterized in that the product of the average value of the significant number of bits of the coefficients of each tap of the shift register and the number of taps is used as the manual number of the adder.

〔Example〕

An example of this excavation will be described with reference to FIG. In FIG. 1, ``■'' is an input terminal to which human data such as a digital video signal is supplied, and 2 is a shift register. In this example, the shift register 2 is configured by cascading five stages of registers, and five taps are derived from the shift register 2. Each tap of shift register 2 is connected to each input terminal of shift circuit groups 3, 4, 5, 6.7.

As an example, shift circuit groups 3.7 each include two bit shifters, shift circuit groups 4.6 each include four bit shifters, and shift circuit group 5 includes six bit shifters. The bit shifters included in these shift circuit groups 3 to 7 respectively convert the 8-bit signal taken out from each tap of the shift register 2 to a power of 2 or 2.
This is a circuit that multiplies by a coefficient of 1 to the power of . Such a bit shifter shifts the signal from each tap by a predetermined number of bits.

Shift circuit group 3 to 7, total 1 (in this example, ■=18)
The output signal line of is connected to the horizontal input signal line of the switch matrix 8. There are five vertical signal lines of the switch matrix 8 as output signal lines (in this example, J
=9) is derived, and the output signals of this switch matrix 8 are added by an adder 9. The output signal of adder 9 is taken out to output terminal 10 as the output of a digital filter.

The circuit configuration shown in FIG. 1 is as shown in FIG.
1, R2, . 14. 1'5. 16.17, hLh2. h3. h4. The F I and R digital filters are multiplied by a coefficient of h5, and the outputs of these multipliers 13 to 17 are added by an adder 19 and taken out to an output terminal 20. As these coefficients h1 to h5, desired coefficients can be set by multiplying the power of 2 or by 8 to the power of 2.

By the way, the multiplier 1 of the digital filter shown in FIG.
3 to 17 perform the calculations shown in FIG.

In other words, convert the code of binary data into straight binary code.
If we limit the code to positive numbers only, the multiplier P of bp bits and the multiplier Q of bq bits can be multiplied by the multiplicand P and multiplier Q.
While sequentially shifting the bits from the LSB (least significant bit) of the partial products, arrange them up to the MSB (most significant bit) partial products of the multiplicand P and multiplier Q, and add all partial products to obtain the multiplication output (PXQ). It is done by

A multiplier is basically constructed by arranging (bp x bq) arithmetic unit circuits each consisting of one AND gate and one full adder. Therefore, in the digital filter having the configuration shown in FIG.
bq) full adders are used, and in the adder 19, the word length is (bp+bq) bits, so approximately (Nx (bp+b
q) ) full adders are required, totaling approximately N・(
bp − bq + bp + bq).

In reality, the data (bp bits) that is the multiplicand input and the coefficient (bq, bits) that is the multiplier input also have signs, so
The partial product of the MSB of the multiplier Q requires correction for the sign, and the multiplication output is also 1 bit less due to the sign (
The word length is bp+bq-1) bits. However, the number of full adders mentioned above will not differ significantly. Furthermore,
The multiplicand P and the multiplier Q may not be integers, but may be considered fixed-point data with a decimal point immediately below the MSB, that is, the sign bit.・In that case, the multiplication output is (bp+bq-1
-) The decimal point is immediately below the MSB or sign bit of the bit.

In the following explanation, the circuit scale will be compared with Full Age's 9
Comparing by number. This is because, when comparing FIG. 1 and FIG. 2, the shift registers are common, and the circuit scale is mostly determined by the number of full adders, except for the switch matrix 8 among the remaining parts.

In this invention, the coefficient is limited to a power of 2 or 1/2 to a power of 2, thereby eliminating the need for a multiplier and reducing the scale of the hardware, that is, the number of full adders described above (in addition to Redundant parts of the hardware are removed by focusing on the characteristics of the coefficients of the digital filter.

This characteristic is that the significant bits of the digital filter's coefficients become fewer and fewer as they move away from the center tap. Here, a "significant bit" means a bit that is "1" when the binary absolute value of the coefficient is taken. When the coefficients (bq bits) are arranged in order from those related to the first tap to those related to the seventh tap, the range of distribution of significant bits is shown in Figure 5A or □Figure 5B. 5A and 5B, the boundary between the shaded area and the non-shaded area corresponds to the most significant bit of the significant bits.Therefore, the partial product regarding the non-significant bits in this shaded area No adder circuit is required.

Furthermore, as shown by the broken line in FIG. 5, when the word length of the coefficient is longer, the ratio of the shaded area to the whole decreases.

The shift circuit groups 3 to 7 in one embodiment of the present invention should each include bq bit shifters equal to the word length of the coefficient, but since it is necessary to add only the above-mentioned significant bit distribution range, As the distance from the tap increases, bit shifters corresponding to coefficients whose number of bits to shift is smaller or larger are omitted, and the number of bit shifters is reduced.

Now, it is assumed that the number of outputs of the shift circuit groups 3 to 7, that is, the number of bits in the distribution range of significant bits of the coefficients is 1.

This is the number of squares other than the shaded area in FIG. 5, and is the number of inputs to the switch matrix 8. Since the number of bits of all coefficients is (N ) becomes. Therefore, if each bit shifter were constructed with a multiplier, the number of full adders required would be approximately N.
It is reduced to [α·bp−bq+ (bp+bq)).

Further, in the present invention, the scale of the hardware is further reduced by eliminating the redundancy of the adder that adds the partial products shifted by each bit. That is, the number of significant bits of the coefficient is
Since the coefficient is a binary number "0" or "1", the number of "1" points in the absolute value of the coefficient is considered to be 1/2 on average, and the circuit for addition is , the scale can be reduced to 1/2.

Furthermore, when calculating filter coefficients from the desired characteristics of a digital filter, the binary number of the coefficient can be limited to a simple combination of powers of 2, so the binary number of the absolute value of the coefficient at that time can be set to 1. It is also possible to limit the number to a small number.

The adder 9 in one embodiment of the present invention only needs to be able to add all the partial products for the significant number of bits of the coefficients, and the scale of the adder 9 has no direct relation to the number N of taps of the filter or the word length bQ of the coefficients. can be determined. For example, assuming that the average value of the number of significant bits of coefficients per tap is S bits, the number of inputs to the adder 9 is (SXN),
Since the word length of this addition input is the maximum (bp+bq) bits, the total number of full adders in adder 9 is approximately S−N・(
bp+I)q).

In other words, the relationship (1>J) holds and β(-J/I
) means the ratio of the number of significant bits within the distribution range of significant bits, and J=SN=β・■=β・α・(N−bq),
The reduction rate of the circuit scale is β and α. In this case, the number of full adders is approximately α·β·N−bq·(bp+bq).

As described above, the embodiment of the present invention can achieve the circuit reduction ratio γ shown by the following equation, compared to the conventional digital filter, from the above two points.

γ-(bp+α・β・bq (bp 10 bq)) /
(N・(bp・bq + bp + 1lq) )
−(bp+α・β・(bp −bq+bq2) )
/(b,p·bq+bq+l)q) Furthermore, as will be described later, if the coefficients are symmetrical with respect to the center tap, the reduction rate T in the above equation can be reduced to 172.

Furthermore, digital filters that are actually used are often phase linear filters whose coefficients are symmetrical about a central tap. For example, the coefficients of the digital filter shown in FIG. 2 are set as hl, h2, h3, etc. in order from the input side. h4. h5
Then, the relationship is (hl,=h5) (h2=h4).

In the case of a digital filter with symmetrical coefficients, the configuration shown in FIG. 3 can be used. The adder 26 adds the outputs of the first tap and the fifth tap of the shift register 2.2 connected to the input terminal 21 in FIG. The outputs of the taps are added by an adder 27, and each output of the adders 26 and 27 is multiplied by a coefficient by the multipliers 23 and 24, and the result is supplied to an adder 29. The output of the third dasobu, that is, the central tap, is multiplied by a coefficient by a multiplier 25 and is supplied to an adder 29 . An output terminal 30 is derived from this adder 29. This third
As is clear from the figure, the number of multipliers can be approximately 172. Therefore, if this invention is applied to a digital filter with symmetrical coefficients, the number of bit shifters can be reduced to about 17.
It can be reduced to 2.

FIG. 6 shows an example of the switch matrix 8. Three selectors S1 that connect any one of the input signal lines from the shift circuit groups 3 to 7 to each of the five output signal lines.
．． S2. 'S3. ... constitutes the switch matrix 8. By controlling the states of the selectors of this switch matrix 8, coefficients can be set and filter characteristics can be changed. In other words, it is possible to provide versatility.

In the configuration of FIG. 6, there are (IXJ) contacts, and in principle, <■XJXbp) gates are required. FIG. 7 shows an example of an improved switch matrix in which the number of gates is reduced by limiting the number of input signal lines to a portion of the five output signal line receivers.

In the example shown in FIG. 7, for each of the five output signal lines, Sll, SL2', S13. S14,515. S
As shown at 16, a selector is provided not for all of one input signal line but only for a part of it. In this example, for each input signal line, there is always an intersection with three output signal lines. Therefore, the intersection where the selector is placed is 1/2 of all the intersections. The gate scale of the switch matrix can be halved.

Even with the switch matrix having the configuration shown in FIG. 7, almost no trouble occurs when setting coefficients.

The switch matrix is not limited to selectors, but can be constructed from ROM or PLA (programmable logic array).

Another embodiment in which the present invention is applied to a digital filter with symmetrical coefficients will be described with reference to FIG. In FIG. 8, 41 indicates an input terminal, and the input terminal 41 is connected to the first stage register R1, six stages of registers R2 to R7 are connected in cascade to this register R1, and a terminal 42 is led out from the register R7. In addition, 7 stages of registers R8 to R1
4 is provided, and a terminal 43 is led out from the resistor R14. A terminal 47 where the input terminal of the resistor R8 is connected to the ground side terminal 46 or the terminal 44 by the switch circuit 45.
connected to either. Register R8 and register R9
A switch circuit 48 is inserted between the terminal 4 and the terminal 4 in which the input terminal of the register R9 is connected to the output terminal of the register R7.
9 or a terminal 50 connected to the output terminal of resistor R8.

In this way, in addition to the input terminal 41, the terminal 42°43.4
4 is provided because the number of taps of the digital filter can be easily expanded by parallelization.

Further, the reason why the switch circuits 45 and 48 are provided is to cope with the case where the number of taps of the digital filter is an even number and when the number of taps is an odd number. If the number of knobs is even, the switch circuit 45 selects the terminal 47 and register R8
The output terminal of the register R8 is connected to the terminal 44, and at the same time, the switch circuit 48 selects the terminal 50, and connects the output terminal of the register R8 and the input terminal of the register R9. Then, if terminals 42 and 44 are shorted, 14 stages of resistors R1 to
Fourteen taps can be derived from each stage of R14.

When doubling the number of taps, prepare another circuit with the same circuit configuration as shown in FIG. 8, connect terminal 42 to the terminal corresponding to terminal 41 of the other circuit, and connect terminal 44 to the other circuit. It is connected to the terminal corresponding to the terminal 43 of the circuit, and the two terminals corresponding to the terminals 42 and 44 of the other circuit are short-circuited. In this way, the number of taps can be easily expanded.

In this example, in order to realize a 13th-order digital filter, the switch circuit 45 is connected to the ground terminal 4 as shown in the figure.
6 is selected, the switch circuit 48 selects the terminal 49 (output terminal of the register R7), and taps are derived from between each stage of the 13 registers except for the register R8.

The respective outputs of registers R1 to R7 are sent to adders 51, 52 .
53, 54, 55, 56.
It is said to be the other human power of 57. Addition outputs of the outputs of two taps having the same coefficient are obtained from each of the adders 51 to 57, and the addition outputs are added to the code conversion circuits 61, 62,
63, 64, 65, 66, 67. These code conversion circuits 61 to 67 are circuits that convert two's complement codes into sign absolute value codes.

Taking 4 bits as an example, the sign absolute value code is shown in the table below.

Such a sign-magnitude code is known as a code convenient for multiplication circuits. Here, in order to make the explanation easier to understand, code conversion is simply performed.

A shift circuit group 71 for each of the code conversion circuits 61 to 67,
72, 73, 74, 75, and 76.77 are connected, and the absolute value of the data is multiplied by a coefficient of a power of 2, that is, the data is shifted.

The output of the code conversion circuit 61 is the output of the center tap, and the shift circuit group 71 connected to this code conversion circuit 61 and the shift circuit group 72 connected to the code conversion circuit 62 corresponding to the tap next to it are 4, respectively. contains bit shifters. These 4 bit shifters shift 3 bits to the left (8 times).

Shift 2 bits to the left (x4), shift 1 bit to the left (2x)
times) and unshifted (1 times) coefficients. Each of the shift circuit groups 73 and 74 includes three bit-sicks excluding the 8x bit shifter, and each of the shift circuit groups 75. Each of 76.77 includes two bit shifters except for the 8x and 4x bit shifters. In this way, coefficients with smaller values remain as the distance from the center tap increases.

Output signal lines derived from a total of 20 bit shifters in shift circuit groups 71 to 77 are input signal lines to switch matrix 80. This switch matrix 8008
In order to output data to the main output signal line, selector S
21,522. S23. S24. S25°S26. S
27. S28 is provided. Selector 521 is 3
Human power, selector 528 is 5 man power, selector S22 is 6 man power, selector S27 is 8 man power, selectors S23 to S26
The configuration is such that each of the input signal lines of the switch matrix 80 is input to three selectors except for the taps at the less frequently used end, that is, the two output signal lines of the shift circuit group 77. has been done. These selectors S21
.about.328 selects and outputs the input corresponding to the desired filter characteristic.

The output data of each of the selectors 321 to S28 of the switch matrix 80 is transmitted to the code conversion circuits 81, 82, 83 .
Supplied on 84.85.86, 87.88. These code conversion circuits 81 to 88 are code conversion circuits 61 to 6.
7, the code absolute value code is converted back to the two's complement code. The outputs of the code conversion circuits 81 to 88 are sent to the adder 90.
supplied to This adder 90 is made up of full adders connected in a tree shape, and an output terminal 92 is led out from the final stage full adder. Further, an input terminal 91 is provided for supplying the addition output from the previous stage to the final stage full adder when expanding the number of taps.

In the other embodiment of the invention described above, assuming that the word length of the input data is (bp=8), the parameters described above are as follows.

Number of taps: 14. Coefficient word length bq: 4° Total number of coefficient bits: NXbq = 56° Therefore, in a digital filter with a conventional configuration,
(bp-bq+bp+bq) =14(8X4+8+
4)=616 full adders are required.

Since the total number of points in the distribution range of significant bits of coefficients in this example is 20, the reduction rate α of the circuit scale by limiting the distribution range of significant bits is α-I/C(N/ 2)・bq)-0,714 adder 9
Since the input number J of 0 is 8, the assumed ratio β of the number of significant bits within the distribution range of significant bits is β-J / I = 0.4 Therefore, the total number of full adders in this example is: (N/2)
・(bp+α・β・bq (bp+bq)) #15
2. Therefore, the overall circuit scale reduction rate T is γ=152/
616 = 0.247, that is, approximately 1/4.

FIG. 9 shows the representation of the two's complement code and the sign absolute value code of the coefficients of the 13th order digital filter used in the TBC (time base corrector). This digital filter has symmetrical coefficients, has bandpass characteristics as shown in FIG. 10, and has the following system function.

H= (1/16)(-1+2Z-"-3Z-'+
4Z -'-3Z -8+22-"-Z-") When realizing such a coefficient, selectors 7'S21 to 528 (however, selectors S22, S23, and S28 are does not select any input) is connected to the output terminal of the predetermined bit shifter.
t will be done. The selector may be selected as follows, considering that each data is a sign-absolute value code and the signs of the coefficients and their absolute values shown in FIG. 9.

First, select a bit shifter corresponding to the absolute value of the coefficient "1" from the shift circuit group, and then At home, choose an intersection where the selector circuit is located and select that point. In this case, if the sign of the coefficient is negative, although not shown in FIG. 8, the sign of the data is inverted. This series of operations may be performed for each 1'' bit of the absolute value of the coefficient.

In addition to the configuration of the embodiments described above, the gist of the invention is as follows.

Various modifications are possible without departing from the above.

For example, when reducing redundancy by focusing on the distribution range of significant bits of a coefficient, the shaded area (redundant part) in Figure 5A and the non-shaded area (significant bits) in Figure 5B Regarding the area corresponding to the area (area), the number of manually guided selectors of the switch matrix may be smaller than the area of other significant bits. In this way, it is possible to reduce the number of significant pitch limits and reduce the amount of hardware required.

Furthermore, in the above description, a significant bit was defined as a bit that becomes "1" in the absolute value of the coefficient.

However, this definition is for a code absolute value code, and for two's complement codes and other binary codes, definitions corresponding to each code are possible. [Effects of the Invention] According to the present invention, an expensive and large-scale multiplication circuit can be eliminated, and by eliminating redundant parts of the circuit, the circuit scale can be further reduced.

Further, the present invention is a versatile configuration in which the coefficients of the digital filter can be changed, and is not a dedicated configuration for each filter characteristic. Therefore, when creating an IC circuit, the design man-hours,
It is possible to reduce maintenance man-hours.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are block diagrams of one example and another example of a digital filter to which this invention can be applied, and FIG. 4 is a block diagram of an example of a digital filter to which this invention can be applied. FIG. 5 is a route map used to explain the multiplication procedure; FIG. 5 is a route map used to explain the significant bit range of the coefficients of the digital filter; FIGS. Figure 8 is a block diagram of another embodiment of this invention, Figure 9 is a route diagram used to explain filter coefficients of another embodiment of this invention, and Figure 10 shows frequency characteristics of another embodiment of this invention. This is a graph showing. 1.14F input terminal, 2: Shift register, 3 to 7.7
1 to 77: shift circuit group, s, go: switch selector, 9.90: adder, 10.92: output terminal.

Claims (1)

[Claims] A shift register to which an input digital signal is supplied, and a plurality of bit shift circuits for multiplying each output of a plurality of taps of the shift register by a coefficient of a power of two or a power of two. and an adder circuit that adds the outputs of the plurality of bit shift circuits and generates an output, wherein each of the plurality of bit shift circuits is configured as a shift circuit group including a plurality of bit shifters; The output signals of the plurality of bit shifters are selected by the selection circuit and supplied to the adder as the output of the shift circuit group, and the product of the average value of the number of significant bits of the coefficient of each tap of the shift register and the number of taps is calculated. A digital filter characterized in that the number of inputs of the adder is equal to the number of inputs of the adder.