JPS62118630A - Digital filter - Google Patents

Abstract

PURPOSE:To allow the titled filter to cope with a high speed data change with the operation delay time independently of the order number (n) by using m-set of ROMs having (n+1)-bit address input and k-bit data output. CONSTITUTION:The titled filter is provided with m-column of delay element groups 11 where n-set of delay elements of the unit bit in one column inputting m(natural number)-bit of parallel input data and holding the said input data at each prescribed point of time one by one bit are connected in cascade, m-set ROMs 12-1-12-m each using a tap data of each column of each delay element group as an address input at each column and whose address is written with a data as the total sum of products between l(natural number)-bit of multiplication coefficient multiplied with each tap of the delay element and the input data held as above or a data of 2's complement of the former data and an adder circuit 13 adding outputs of the m-set of the ROMs. Thus, the operation delay time is independent of the order number (n) and the FIR type digital filter operated at a high speed is obtained even when the order number (n) is large.

Description

[Detailed Description of the Invention] [Industrial Application Field] Among digital filters used for various digital signal processing, the present invention relates to a coefficient filter that is particularly excellent in that linear phase characteristics can be easily realized. Invariant/IFR (Finite Impulse Response, Finite Impulse R
e5ponse) type digital filter.

〔overview〕

The present invention provides a time-invariant, finite-length impulse response digital filter with m read-only memories in which calculation results multiplied by predetermined multiplication coefficients and predetermined additions are written in advance, and the addresses of the m read-only memories are written. Given by each tap output of a 1-bit delay element group to which an n-th order m-bit parallel input is input,
By adding all the outputs of the read-only memory, the calculation delay time is made independent of the order n, and the operation speed is increased.

[Conventional technology]

Conventionally, this type of n-order FIR type digital filter generally has an n-stage delay element Z-1 as shown in FIG.
a delay element group 1 consisting of fi+1 multipliers L0 to L
It is composed of a multiplier group 2 consisting of 7 multipliers and an addition circuit 3 consisting of n adders.

Here, delay element 7. -1 shifts m-bit parallel input data sequentially to the cloth taps in parallel every unit time T, and the m-bit parallel data of each tap is transferred to each multiplier L.
It is multiplied by a multiplication coefficient β bit by 0 to Lfi and rounded to m bits. Then, the adder circuit 3 sums up the multiplication results for all the taps to obtain m-bit parallel output data. When actually converting this into hardware, in order to reduce the hardware scale of multiplier group 2 and adder circuit 3, the calculation process of "adding the next multiplication result to the current addition result" is repeated n+1 times. There is a way.

[Problem that the invention seeks to solve]

In such a FIR type digital filter,
Compared to an IIR (infinite impulse response) type digital filter, the order n of the filter needs to be set to a certain degree in order to achieve a desired steep cutoff characteristic. However, almost in proportion to the demand for increasing the order n,
The calculation delay time accumulated in the process of repeating the above multiplication and addition increases. Therefore, as the order n increases,
There is a drawback that it becomes difficult to follow high-speed information changes of m bits of parallel input data.

SUMMARY OF THE INVENTION An object of the present invention is to provide an FIR type digital filter that eliminates the above drawbacks and operates at high speed even when the order n is large, with the calculation delay time being independent of the order n.

[Means for solving problems]

The present invention provides an m-column delay system in which n unit-bit delay elements are cascaded in a row to receive m (m is a natural number) bits of parallel input data and hold the input data bit by bit at each predetermined point in time. The element group and the tap data of each column of each delay element group are input as addresses for each column, and each address contains the bit multiplication coefficient (It < 1 is a natural number) applied to each tap of the delay element and the above-mentioned retention. m ROMs in which data as the sum of products with input data or data as the two's complement of that data is written.
and an adder circuit that performs addition for each output of the m ROMs.

[For production]

In the present invention, bit data or its two's complement data as a calculation result of the following equation is written in advance in a ROM (read-only memory) corresponding to each address input.

, Σ ((1 bit of input data at −iT)×[β
The bit multiplication factor is 5]) where n is the order and T is the pulse interval of the impulse response.

Then, this data is read out using the data of all the taps of the delay element group which inputs the m-bit parallel input data as the address input of the ROM, and is added by an adder circuit to obtain an m-bit parallel output. Therefore, in the present invention, a conventional multiplication circuit is not necessary, and the number of additions may be m-1 times regardless of the order n. In this way, a high-speed FIR type digital filter whose calculation delay time is independent of the order n is obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention, and shows the case of an acyclic type. In this example, the order is nth, all output data are parallel m bits, the multiplication coefficient is β bits, the impulse response pulse interval is T, all data and coefficients to be handled are expressed in two's complement, and the data and the MSB (most significant bit) of the coefficient
shall represent the positive or negative sign. In this embodiment, for each bit of m bits of parallel input data, the finite past −nT, −(n −1)T, −・−・−1
m columns of delay element groups 11 in which n unit bit delay elements are connected in cascade in order to hold input data at each time point of -27 and -17 one bit at a time; The data of all the taps in the column is input as an address for each column, and each address is given a multiplication coefficient L of ×[β bits.
i ) ) calculation result (multiplying coefficient L to avoid overflow!
Assume that has been normalized. ) as a bit (
m ROMs (1) 12-1 to ROM (m
) M R
It includes an adder circuit 13 that performs addition for all the outputs of the OM (k bit data x m pieces). In the figure, IN.

~IN, is m-bit parallel input data, OUT,
~OUT, is m-bit output data, A, ~A n
* I is ROM address input, D (1”' D
k is its data output.゛The feature of the present invention is that in Fig. 1, ROM (1) 12
-1 to ROM (m) 12-m, and a delay element group 11 and an adder circuit 13 are provided therefor.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. In this example, in the circuit shown in FIG. 1, the order of the filter is n=4, the number of bits of output data m=5, and the multiplication coefficient is 5 bits (actually 1=4, 4 bits). It is. In this embodiment, there are four unit bit delay elements.
(1)' 22-1 to ROM (1)' 22-1 to ROM (1)' 22-1 to ROM (1)' 22-1 to ROM (1)' 22-1 to ROM (1)' 22-1 to ROM (
5)' 22-5 and an adder circuit 23.

Next, the operation of this embodiment will be explained with reference to explanatory diagrams shown in FIGS. 3 and 4. The pulse interval of the impulse response is T, and all data and coefficients handled are expressed in two's complement and fixed point numbers, and the MSH "0" and "1" of the data and coefficients have "positive" and "negative" signs. shall be expressed.

Referring to FIG. 2, first, 5 bits of parallel input data are input in parallel from input terminals IN, (MSB) to IN5 (LSB). These 5 bits of input data are shifted one bit to the right in parallel by the delay element group 21 every unit time T.

The data of all the taps (5-bit information) of this delay element group 21 are stored in the ROM (1
)' 22-1 to ROM (5)' This information specifies each address of 22-5.

The table shows the correspondence between addresses and data in this ROM. ROM (2)22-2~ROM (5)22
The contents of -5 are exactly the same, and 5-bit data D0-D# as the calculation result of ×[5-bit multiplication coefficient Li)) is written to each address specified by 5-bits A0-A9. ing. In addition, for ROM (1) 22-1, the two's complement data of the 5-bit data as the calculation result of ×[5-bit multiplication coefficient correction]) is written to each address specified by A0 to A4. .

FIG. 3 is an explanatory diagram showing the multiplication coefficient LL used at this time and the waveform of the impulse response.

That is, the multiplication coefficients 1,1 are given as follows.

L, =t,, = 11111 (=-0,062
5) L, =L, = 00010 (=+0.12
5) Lz = 00100 (=+0.25) However,
The multiplication coefficients are normalized to satisfy the following conditions.

ΣL, ≦01000 (=+0.5) ΣL, ≧110
00 (=-0,5) Figure 4 shows 5 ROMs (1
)' 22-1 to ROM(5)' 22-5 is an explanatory diagram of the addition process performed by the addition circuit 23 for each output of 22-5. First, input from ROM (5) '22-5, ESI, IEsz, Ess, E, E55, and ROM
(4)' Input from 22-4 E4□, E43,
Add Eaa and E4. However, in this case, as shown in the figure, sign extension is performed (the same applies hereafter). Next, the addition result of addition ■ is S4, S4□, S43.344, S4
S and ROM (3)' Input E from 22-3. ,
Perform addition (2) with E'12, ES4, and E3S. Similarly, addition ■, addition ■ and sequential ROM (2)' 22-2,
ROM (1)' Add the inputs from 22-1,
We obtained the results F, , Ft , Fs , Fs , Fs , and OUT I(M S B ) and OUT !, respectively.
, 0UT1.0UT4, OUT, (LSB) 5-bit parallel output data is obtained. As mentioned above, in this calculation, the output of each ROM is converted into 5 bits by preserving the MSB-LSB digit relationship of the input data used for addressing each ROM, and adding them while taking sign extension into account. Output is rounded.

In addition, in the above embodiment, the contents of any ROM are replaced with two's complement numbers, and at the same time, the output of that ROM is added;
The same effect can be obtained even if the subtraction process is reversed.

Note that the present invention is also applicable to an acyclic digital filter obtained by cascading the acyclic digital filters shown in the above embodiments as unit components.

Furthermore, the present invention is also applicable to a cyclic digital filter obtained by combining the acyclic filters shown in the above embodiments.

[Effects of the Invention] As explained above, the present invention has n+1 multipliers and n
When realizing the functions of adders, the calculation delay time is of order n
n+1 bit address input, k
m bit data output ROMs (m is the number of input data bits) are used to prevent the addition processing time from increasing as the order n increases, and the number of additions is always m-1 times (generally By configuring it so that fi > rll ), when the order n becomes high, the calculation delay time is independent of the order n and has the effect of being able to cope with faster data changes than in the past.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. FIGS. 3 and 4 are explanatory diagrams of the operation of another embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of a conventional example. 1. 1.21... Delay element group, 2... Multiplier group,
3.13.23... Addition circuit, 12-1 to 12-m.
・・ROM (1) ~ ROM (m), 22-1 ~ 22
-5-ROM (1)' ~ ROM (5)', Ao
~A7...address input, D0~Dk...data output, IN, ~IN,...parallel input data, OUT
, ~OUT,...Parallel output data. Example of general intention 33 Figure 'pr issue wide and narrow Example of intention 7i4 Figure

Claims (1)

[Claims] (1) m-column delay elements in which n unit-bit delay elements are cascaded in a row and receive m (m is a natural number) bits of parallel input data and hold the input data bit by bit at each predetermined point in time. and the tap data of each column of each delay element group are input as an address for each column, and each address contains an l (l is a natural number) bit multiplication coefficient applied to each tap of the delay element and the above-mentioned data. It is characterized by comprising m ROMs in which data as the sum of products with input data or data as a two's complement of the data is written, and an adder circuit that performs addition for each output of the m ROMs. Digital filter.