JPH0514130A - Digital filter - Google Patents

Abstract

PURPOSE:To realize the digital filter which selects a delay time and a signal level widely from plural delay signals each having a different delay time and is able to synthesize output signals only with comparatively a few multipliers. CONSTITUTION:Plural delay elements D1-Dn are connected in series and taps to obtain delay signal with respective delay times are provided to each connection part. Moreover, outputs of plural multipliers M0-M3 are added by an adder A and the result is outputted to an output of the digital filter. Through the configuration above, signal selection means S00-S3n select plural taps and inputs of plural multipliers through selection. Thus, the multipliers M0-M3 are connected to an optional tap and utilized effectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit for obtaining an output signal by using a plurality of delay elements and combining a plurality of delay signals having different delay times with different signal levels of the respective delay signals. The present invention relates to a filter, and more particularly, to an improvement in a digital filter that can reduce the number of multipliers used in the digital filter and reduce the cost.

[0002]

2. Description of the Related Art It is conventionally known that a transfer function having a predetermined frequency response can be realized by a certain kind of impulse response. In addition, various theories are known for obtaining an impulse response of a transfer function having such a predetermined frequency response and using it in an electronic device or the like.

According to such a theory, in order to obtain a predetermined frequency response, a plurality of delay elements are used and a plurality of delay signals having different delay times are combined with different signal levels of the respective delay signals. There is a digital filter for obtaining an output signal, which realizes a corresponding impulse response filter.

A digital filter using such a plurality of delay elements has a finite impulse response (finite impul)
se response (FIR) filter (hereinafter called FIR filter) and infinite impulse response (infinite impulse r)
Esponse, IIR) filters (hereinafter referred to as IIR filters) are known.

The difference between the FIR filter and the IIR filter will be described later with reference to FIGS. 17 and 18.

FIG. 13 is a block diagram of a conventional FIR filter.

In FIG. 13, a total of n delay elements D1 to Dn are connected in series, and each connection portion is provided with a total of n + 1 taps for obtaining delay signals of various delay times. Further, the filter input signal inputted from the input terminal IN is inputted to the respective inputs of the delay element D1 and the multiplier M0. Further, a total of n + 1 multipliers M0 to Mn capable of inputting these n + 1 delayed signals having different delay times and respectively obtaining delayed output signals of arbitrary signal levels are arranged for each tap. ing. The delayed output signals from the n + 1 multipliers in total are added by the adder A and output to the output terminal OUT as a filter output signal.

In such an FIR filter, the delay signal is obtained from the tap on the output side of the delay element at the predetermined position (predetermined delay time) from the input terminal IN, and the predetermined delay signal is arranged for each tap. A multiplier outputs a delayed output signal having a desired signal level, and all the delayed output signals are added by an adder to obtain a final filter output.
As a result, in such an FIR filter, a filter output signal having a desired impulse response of the filter input signal input to the input terminal IN can be obtained.

In FIG. 13, the filter input signal input from the input terminal IN is continuous data for each predetermined sampling time Ts. Also, the FI of FIG.
The R filter performs digital processing in accordance with a clock whose one cycle is the above-described sampling time Ts. The data, which is the filter input signal input from the input terminal IN, is input to the delay element D1 and sequentially in each clock.
The delay elements are shifted to D2 ... Dn.

The FIR filter of FIG. 13 is NT
When used in SC (national television system committee) image processing, the subcarrier frequency fs
In accordance with c (= 3.58 MHz), 4fsc (= 14.
3MHz) is often used.

Each of the delay elements D1 to Dn is a register for storing data of a word having a predetermined number of bits, for example, an 8-bit word, and has a fixed delay of one clock time (sampling time Ts). To do.

From the taps between the delay elements D1 to Dn, delay time data corresponding to the number of passed delay elements D1 to Dn can be obtained. That is, the n-th delay element Dn
A signal (data) delayed by (n × Ts) time is obtained from the tap on the output side of.

Corresponding multipliers M0 to Mn are connected to the respective taps, and the respective multipliers M0 to Mn are connected.
The signals (data) from the taps are multiplied by the coefficients a ₀ to a _n set for each n.

The coefficients a ₀ to a _n are 8 to 1
It is a coefficient of the number of digits of about 0 bits. Also, the multipliers M0 to M
A parallel multiplier is usually used for n to achieve high-speed processing. For example, if the clock frequency of the above-mentioned clock is 14.3 MHz, the clock period (sampling time Ts) becomes (1 / 14.3 MHz = 70 ns), so the operation speed of the multipliers M0 to Mn must be faster than 70 ns. I won't.

Note that such a parallel multiplier is for substantially parallel operation of each digit of the multiplier and each digit of the multiplicand, requires many logic gates, and has 8 × 8 bits. A parallel multiplier of 8 × 10 bit class requires about 1000 gates.

In FIG. 13, the outputs of the multipliers M0 to Mn are all added by the adder A, and the result is output terminal OU.
It is output from T. The multiplication result output from the multipliers M0 to Mn is 16 to 18-bit data, and the adder A can execute the addition of such a bit number, and the addition result from the output terminal OUT is Is output.

In the calculation performed by the FIR filter of FIG. 13, the k-th input for each sampling time Ts is X _k , the output is Y _k, and the coefficients multiplied by the multipliers M0 to Mn are a _{0. Let} ~ a _n be expressed by the following equation.

[0018]

[Equation 1]

Note that such an operation is performed by convolution integral (co
nvolution), which allows the digital filter to have some frequency characteristics. Further, this frequency characteristic is determined by how to give the coefficient a _i .

Further, conventionally, there has been disclosed a technique of improving a ghost screen by removing a ghost signal from a received signal of a television by using various filters.

FIG. 14 is an explanatory diagram of a ghost screen based on a ghost signal which is superimposed on the received signal together with the main signal.

In FIG. 14, an image I0 is a real image by the main signal, and an image I1 is a ghost by the ghost signal that is superimposed on the main signal in the received signal.

A screen shift amount between the real image and the ghost
ta is determined by the delay time or the advance time of the ghost signal that is superimposed on the original signal. A ghost that is shifted to the right like the image I1 for the image I0 in FIG. 14 is called a rear ghost. On the other hand, a ghost that shifts to the left on the screen is called a front ghost. Such a front ghost is a case where the propagation of the radio wave is advanced in the ghost signal with respect to the original signal, but among the radio waves propagated with different delay times, the strongest signal is the main signal, Such a front ghost may appear.

Note that FIG. 14 assumes the NTSC system, and horizontal scanning from left to right is performed in order from top to bottom. The horizontal scanning period Th is 63.5 μs, and about 80% of the horizontal scanning is displayed on the screen. The left and right parts of the horizontal scanning that are not displayed on the screen are called horizontal blanking.

FIG. 15 is a radio wave propagation diagram for explaining the ghost generation process.

In FIG. 15, the direct wave B of the broadcast radio wave radiated from the broadcasting station 20 reaches the receiving antenna 24 with the shortest distance. On the other hand, part of the broadcast radio waves radiated from the broadcasting station 20 is reinforced concrete building 22.
The reflected waves C and D reflected by a and 22b arrive at the receiving antenna 24. These reflected waves C and D are direct waves B
Therefore, the propagation time is longer than that of the direct wave B, because it propagates a distance longer than the propagation distance of. Moreover, since the reflection surfaces of the broadcast radio waves of the reinforced concrete buildings 22a and 22b have a certain width, the propagation times of the reflection waves C and D are wide, and the reflection waves C and D are respectively. Is like a composite signal of many reflected waves with close propagation times.

Therefore, the reception signal generated at the reception antenna 24 becomes a reception signal in which, in addition to the main signal, a ghost signal with a time delay is superimposed.

FIG. 16 is a waveform diagram of the original signal and the received signal in which the ghost signal is superimposed on the main signal corresponding to the original signal.

In FIG. 16, the original signal x (t) is
It is represented by a square wave of height 1. In addition, this FIG.
In the received signal y (t) at, the square wave g ₀ of height 1 due to the main signal, which is generally a direct wave, and the square waves g _{1 to} g ₅ of the ghost signal due to multiple reflected waves are superimposed. There is.

Further, the square waves g ₁ , g ₂ , g ₃ , g ₄ , of the ghost signal due to the reflected waves superimposed on each other,
g ₅ is a delay time Δ t ₁ , Δ t ₂ , Δ t ₃ , Δ t ₄ , and Δ t that is smaller than that of the square wave g ₀ of the original signal due to the direct wave.
It has been delayed to ₅ . The signal levels of the square waves g ₁ , g ₂ , g ₃ , g ₄ , g ₅ of these ghost signals are a ₁ , a ₂ , a ₃ , a ₄ , a ₅ respectively.

The received signal y (t) shown in FIG. 16 is expressed as follows.

[0032] y (t) = x (t ) + a 1 x (t-Δ t 1) + a 2 x (t-Δ t 2) + a 3 x (t-Δ t 3) + a 4 x ( t−Δ t ₄ ) + a ₅ x (t−Δ t ₅ ) …… (2)

The equation (2) is modified to obtain x (t) as follows.

X (t) = y (t) −a ₁ x (t−Δt ₁ ) −a ₂ x (t−Δt ₂ ) −a ₃ x (t−Δt ₃ ) −a ₄ x ( t−Δ t ₄ ) − a ₅ x (t−Δ t ₅ ) …… (3)

That is, the ghost signal superimposed on the received signal y (t) can be removed by the calculation of the equation (3).

Further, the calculation of the equation (3) is as follows when described on the premise of digital processing, that is, on the premise of the discrete time system.

[0037]

[Equation 2]

Conventionally, the above-mentioned FIR filter has been used to effectively remove the ghost signal from the received signal by performing the calculation of the equation (3) or (4).

This FIR filter can be realized by a digital filter. In recent years, however, various ghost cancellers using the FIR filter configured by the digital filter have been developed along with the price reduction of the digital filter.

FIG. 17 is a block diagram showing a first example of a ghost canceller using a digital filter.

In FIG. 17, the calculation represented by the above equation (4) is performed. That is, in this FIG. 17, x (t) and y (t) are respectively the above (3)
Corresponds to the expression. Reference numeral 12a is an FIR filter as shown in FIG. The digital filter shown in FIG. 17 has a feedback path to the FIR filter 12a and is an IIR filter as a whole.

FIG. 19 is a block diagram showing a second example of a ghost canceller using a digital filter.

In FIG. 19, an input signal (received signal) input from the input terminal IN passes through an FIR filter which is a digital filter composed of 64 stages of delay elements, and the two inputs of the adder A Input to one of the inputs. The output of the adder A has a delay element of 57.
FI which is a digital filter composed of 6 stages
The FIR filter 12 is input to the R filter 12b.
The output of b is the other one of the two inputs of the adder A.
Entered in one input. That is, this FIR filter 12
b and adder A constitute an IIR filter, and the output of this adder A is the output terminal O of this ghost canceller.
It is also connected to the UT.

The second example of the ghost canceller has an FIR filter 10 used particularly as an equalizer section as compared with the first example described above. This FIR filter 10 corrects waveform distortion in the transmission system from the receiving antenna to the television, plus or minus 2 with respect to the main signal.
It is used to remove near-field ghosts in the range of μs.

The IIR filter composed of the adder A and the FIR filter 12b is operated by the equation (3) or the equation (4), that is, a plurality of delay signals having different delay times are provided to the respective delay signals. The ghost removing section is configured to remove the ghost signal by changing the signal levels of and adding them.

FIG. 20 is a block diagram of a third example of a ghost canceller using a digital filter.

In FIG. 20, the FIR filter 10
Is the same as the FIR filter with the same reference numeral in FIG. 19 and similarly constitutes an equalizer section.

In FIG. 20, the ghost removing section is
10 to 16 sets of signal delay units by the variable delay unit 14 and the FIR filter 12c of 7 to 16 stages of delay elements are arranged in parallel, and the output of each signal delay unit, that is, the output of each variable delay unit 14 Are added by the adder A.

In the third example of the ghost canceller of FIG. 20, attention is paid to the fact that the number of the multipliers M0 to Mn of FIG. 18 in which the value is “0” is large in the first example of the ghost canceller described above. Thus, the total number of taps of the FIR filter is reduced.

In the variable delay device 14 of FIG. 20,
As shown in FIG. 21, fixed delay elements DF1 to DFn are connected in series. Further, the variable delay device 14 switches the output terminal OUT to which tap output from between the fixed delay elements DF1 to DFn,
The delay time can be set.

FIG. 2 according to a third example of a ghost canceller.
As shown in 2, removal of ghost signals g ₁₁ to g ₁₃ that had been superimposed on the main signal g ₁₀ is performed in a total of three variable delays 14 total and three FIR filters 12c.

That is, as indicated by the symbol F1 in FIG. 22, the ghost signal g ₁₁ having the delay time Δt ₁₁ can be removed by the variable delay device VD1 and the FIR filter FIR1.
As indicated at F2, the ghost signal g ₁₂ of the delay time delta t _12, the variable delay device VD2 and FIR filter FIR2
It can be removed with. As indicated by the symbol F3, the ghost signal g _{13 with} the delay time Δ t ₁₃ is generated by the variable delay units VD3 and F
It can be removed by the IR filter FIR3. That is, these ghost signals g _{11 to} g ₁₃ are summed (7 × 3 to 16 × 3).
= 48) FIR filter taps can be removed.

In principle, one tap is sufficient for removing one ghost, but in reality, since there is a spread of the ghost, 7 to 16 taps (fixed) are assigned.

As described above, according to the third example of the ghost canceller, the ghost signal can be removed with a relatively small total number of FIR filter taps, and the total number of multipliers used can be reduced. The cost can be reduced.

[0055]

However, in the above-mentioned first and second examples of the ghost canceller, a plurality of delay signals having different delay times are selected widely in the delay time and the signal level and the output signal is synthesized. However, while there is a feature that ghost signals with various delay times and signal levels can be effectively removed, there is a problem that a multistage FIR filter must be used.

Conventionally, such a multi-stage FIR filter requires a large number of multipliers, which raises a problem of increasing the cost of the ghost canceller as a whole.

On the other hand, the third example of the ghost canceller shown in FIG. 20 has an advantage that the number of stages of the FIR filter used may be small and the cost of the entire ghost canceller can be reduced. However, since the number of FIR filters used and the number of taps of each FIR filter are limited, the number and spread of ghosts that can be removed are limited, and many ghost signals with different delay times and signal levels are superimposed on the received signal. In such a case, there is a problem that it is not possible to remove all ghosts or a ghost signal having a large spread cannot be removed sufficiently. Also, with a small number of taps, even a narrow ghost that is sufficiently narrowed to 7
There is a problem that ~ 16 taps are assigned.

The present invention has been made to solve the above-mentioned conventional problems, and a digital signal which can synthesize a plurality of delayed signals having different delay times by widely selecting the delay time and the signal level and synthesizing an output signal. The purpose of the present invention is to realize a filter with a relatively small number of multipliers and to reduce the cost.

[0059]

According to the present invention, a plurality of delay elements are used to obtain an output signal in which a plurality of delay signals having different delay times are combined with different signal levels of the respective delay signals. In the digital filter of (1), a plurality of multipliers that output the input signal level as a desired signal level, and a signal selection unit that performs switching selection between the plurality of delay elements and the plurality of multipliers are provided, By obtaining a combined output signal of a plurality of delay signals having different delay times by switching selection of the signal selection means,
The above-mentioned problems have been achieved.

Further, the plurality of delay elements are connected in series, each connection portion is provided with a tap for obtaining a delay signal of each delay time, and the outputs of the plurality of multipliers are added by an adder. The signal is output to the output of the digital filter, and the signal selection means switches and selects between the plurality of taps and the inputs of the plurality of multipliers to achieve the above object.

Further, the signal selecting means is provided for each of the plurality of taps and the inputs of the plurality of multipliers, and the corresponding taps are turned on or off between the corresponding taps and the inputs of the corresponding multipliers. By doing or switching, the above-mentioned problem is achieved.

Further, the signal selecting means is provided between each of the plurality of taps and the inputs of the plurality of multipliers, and whether the corresponding tap is turned on or off to the input side of the corresponding multiplier. A switch for switching and an adder for adding a signal on the multiplier side of the switch and an output of another signal selecting means are provided, and the switches of the plurality of signal selecting means are turned on with respect to the input of one multiplier. In this case, the signals from the taps corresponding to these signal selecting means are added and input to the multiplier, thereby achieving the above object.

Further, the signals input to the digital filter are input to each of the plurality of multipliers, and the plurality of delay elements are alternately connected in series with the plurality of adders for injecting the delayed input signal. By being connected, the signal selection means switches and selects between the outputs of the plurality of multipliers and the input of one of the plurality of adders,
The above-mentioned problems have been achieved.

The signal selecting means is provided between the outputs of the plurality of multipliers and the inputs of the plurality of adders, and the output of the corresponding multiplier and the input of the corresponding adder are provided. The above object is achieved by switching between turning on and turning off.

Further, the adder is a multi-input adder, and the signal selecting means is provided between the outputs of the plurality of multipliers and the inputs of the plurality of adders, and the outputs of the corresponding multipliers are provided. The above object is achieved by switching between ON and OFF between the input and the corresponding one of the multi-inputs of the corresponding adder.

Further, a multi-input adder is provided at each input of the plurality of multipliers, the signal selecting means is provided between each of the plurality of taps and the plurality of adders, and a corresponding tap is provided. The above object is achieved by switching between turning on and off between the corresponding input of the multi-inputs of the corresponding adder.

The above object is achieved by providing the signal selecting means with an adder for adding the selection result of the signal selecting means and the selection result of the other signal selecting means.

[0068]

According to the present invention, in a digital filter using a plurality of delay elements, a plurality of multipliers for outputting the signal level of an input signal as a desired signal level are provided, and in particular, these delay elements and A signal selecting means for switching and selecting between the plurality of multipliers is provided. Therefore, even if a large number of delay elements are used side by side,
Even with a smaller number of multipliers than the number of these delay elements, it is possible to widely select the delay time and the signal level and combine the output signals.

That is, according to the present invention, for example, it is sufficient for the multiplier to have at least the number of signal levels of the delay signals of the respective delay times to be combined (however, as in the embodiments described later, It is possible to further reduce the multiplier). Therefore, conventionally, in a digital filter having, for example, 500 delay elements, almost 500 multipliers (much more than the number of signal levels of delay signals of respective delay times to be combined) have been used. Therefore, according to the present invention, the number of multipliers used in the digital filter can be significantly reduced.

In the present invention, for example, a switching element or an adder can be used as the signal selecting means for switching and selecting a relatively small number of multipliers so that they can be effectively used. The switching elements, adders, and the like that are frequently used in the present invention use far fewer elements such as transistors than the multipliers.

Therefore, by reducing the number of multipliers used in the digital filter, the cost of the digital filter as a whole can be reduced even if a new signal selecting means is required.

Further, according to the present invention, the delay elements used can be efficiently used, and the number of delay elements, variable delay elements, etc. can be reduced, thereby reducing the cost.

It should be noted that the present invention does not limit the connection relationship or configuration among the plurality of delay elements, the plurality of multipliers, and the signal selecting means.

That is, the signal selection means used is for switching and selecting between the plurality of delay elements and the plurality of multipliers, whereby the plurality of delay elements and the plurality of multipliers are selected. It suffices that and are organically switched and selected, and that the delay time and the signal level are effectively selected in a wide range as well as the multiplication coefficient of each multiplier is changed.

Further, the signal selecting means of the present invention is not limited to the switching element, the adder and the like, and the plurality of delay elements and the plurality of multipliers forming the digital filter are organically arranged as described above. If it can be switched and selected, the effect of the present invention can be obtained.

[0076]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of an FIR filter to which the present invention is applied.

In FIG. 1, the filter input signal input to the input terminal IN is input to the delay element D1 and the four signal selecting means S00 to S30, respectively.

A total of n delay elements D1 to Dn having the same delay time are connected in series, and a tap for obtaining a delay signal is provided at each connection portion of these delay elements.

For example, the output of the delay element D1 and the delay element D
Four signal selecting means S01 to S31 are connected to the tap portion to which the input of 2 is connected. Also, the delay element D
Four signal selecting means S02 to S32 are connected to the tap portion where the output of 2 and the input of the delay element D3 are connected. In addition, at the tap portion where the output of the delay element D3 and the input of the delay element D4 are connected, four signal selecting means S03 ...
S33 is connected. As described above, four signal selecting means are connected to the tap portions of the connection portions of the plurality of delay elements connected in series. That is, a total of 4.times. (N + 1) signal selecting means S00 to S3n are connected to a total of n delay elements D1 to Dn.

Further, these signal selecting means S00 to S3n are
The whole is divided into four groups, each connected in cascade and connected to any one of the multipliers M0 to M3. That is, a total of n + 1 signal selecting means S00-
S0n is connected in cascade, and the signal selecting means S0n at the final stage is connected.
Is connected to the input of the multiplier M0. Also, total n + 1
The signal selecting means S10 to S1n are connected in cascade, and the signal selecting means S1n at the final stage is connected to the input of the multiplier M1. Further, a total of n + 1 signal selecting means S20 to S2n are cascade-connected, and the final-stage signal selecting means S2n is connected to the input of the multiplier M2. Further, a total of n + 1 signal selecting means S30 to S3n are cascade-connected, and the final-stage signal selecting means S3n is connected to the input of the multiplier M3.

The outputs of these four multipliers M0 to M3 are input to the adder A, and the output of this adder A is output to the output terminal OUT as a filter output signal.

FIG. 2 is a block diagram of the signal selecting means used in the first embodiment.

In FIG. 2, the signal selecting means S (corresponding to one of the signal selecting means S00 to S3n in FIG. 1).
Is composed of one switching element SW.

The positions of the three terminals of the signal selecting means S of FIG. 2 are plotted so as to correspond to the positions of the three terminals of the signal selecting means S00 to S3n of FIG. That is, for example, the lower terminal a of the signal selecting means S of FIG. 2 is connected to the tap portion of each connecting portion of the serially connected delay elements of FIG. Corresponds to the terminal.

According to the first embodiment of the present invention shown in FIGS. 1 and 2, four multipliers are effectively used to synthesize at least four delayed signals having different signal levels and different delay times. It is possible to realize a digital filter that can be used. For example, by turning on any of the (n + 1) signal selecting means corresponding to each of the multipliers M0 to M3, only four multipliers M0 to M3 are
Which tap part (output of delay elements D1 to Dn) respectively
Can also be connected to.

The number of delay elements and the number of multipliers are not limited to those in the first embodiment. For example, the inventor actually made several prototypes of FIR filters of the first embodiment in which the number of delay elements was 500 to 600 and the number of multipliers was about 100, and the ghost canceller described above with reference to FIG. Tested using the first example. The prototype FIR filter of the first embodiment has a multiplier of 400 to 5 as compared with a conventional FIR filter using delay elements of 500 to 600 stages.
The cost has been reduced by 00, which is a significant cost reduction.

Further, as compared with the third example of the conventional ghost canceller described above with reference to FIG. 20, for example, when the same number of multipliers is used, this embodiment freely allocates the multipliers to the optimum taps. Therefore, it is possible to effectively and more completely remove ghosts with a wide delay time, narrow ghosts, and more ghosts.

FIG. 3 is a block diagram of the signal selecting means used in the second embodiment of the present invention.

In FIG. 3, the signal selecting means S is composed of one switching element SW and one adder A.

The positions of the three terminals of the signal selecting means S in FIG. 3 are the same as those of the signal selecting means S00 to S3n in FIG.
It is drawn corresponding to the positions of the three terminals. That is, for example, the terminal b on the lower side of the signal selecting means S in FIG. 3 is the lower side of the signal selecting means S00 to S3n connected to the tap portions of the connecting portions of the delay elements connected in series in FIG. Corresponds to the terminal.

According to the second embodiment of the present invention shown in FIGS. 1 and 3, when it is desired to multiply several tap outputs by the same coefficient, one multiplier is sufficient because of the adder. Therefore, the multiplier can be used more efficiently. On the other hand, when only the switching element SW is used as in the first embodiment, the multipliers for the number of taps are required.

For example, the main signal g ₂₀ as shown in FIG.
A total of (3 + 20 + 5 = 28) taps are used in removing the ghost signals g ₂₁ -g ₂₃ for
Of the taps, there may be taps that are assigned the same coefficient. For example, the signals x _i , x _j , x _k
In the case of multiplying each of the above by the same coefficient a ₀ , the following equation holds, and in the present embodiment, as shown in FIG. 5, the number of multipliers used can be reduced from three to one.

[0094]

[Equation 3]

FIG. 6 is a block diagram of a third embodiment of the FIR filter to which the present invention is applied.

The structure of the third embodiment is a transposed structure, with the structure of the embodiment of FIG. 1 described above as the basic type. Therefore, the third embodiment can obtain substantially the same effect as the first embodiment using the signal selecting means of FIG.

In FIG. 6, a filter input signal is input to the input terminal IN, and the filter input signal is input to a total of five multipliers M0 to M4.

The output of the multiplier M0 is input to a total of n + 1 signal selecting means S00 to S0n. The output of the multiplier M1 is a total of n + 1 signal selecting means S10 to S1n.
Are input respectively. The output of the multiplier M2 is the sum
It is input to each of n + 1 signal selecting means S20 to S2n. The output of the multiplier M3 is input to a total of n + 1 signal selecting means S30 to S3n. Also, the multiplier M4
The outputs of the above are respectively input to n + 1 signal selecting means S40 to S4n.

A total of n delay elements D1 to Dn are alternately connected in series with a total of n adders A1 to An for injecting the delayed input signal. Signal selecting means S4n to S40 are sequentially connected to the inputs of the leftmost delay element Dn and the inputs of these n total adders An to A1, respectively.

The outputs of the five multipliers M0 to M4, the inputs of the delay elements Dn and the inputs of the n adders An to A1 are a total of 5 × (n + 1) signals arranged in a matrix. Selecting means S0n to S00, S1n to S10, S2n to S20,
It is possible to switch and select and connect by S3n to S30 and S4n to S40. As a result, the five multipliers M0 ...
Any of the outputs of M4 can be selected and input to the input of the delay element Dn or the inputs of the adders An to A1, and the signal levels are made different to synthesize a plurality of delayed signals having different delay times. You can do it. The adder A1 at the final stage outputs the filter output signal to the output terminal OUT.

FIG. 7 is a block diagram showing the signal selecting means used in the third embodiment.

In FIG. 7, the signal selecting means S is 1
It is composed of two switching elements SW.

The positions of the three terminals of the signal selecting means S shown in FIG. 7 are the same as those of the signal selecting means S shown in FIG.
It is drawn corresponding to the positions of the three input terminals 00 to S4n. That is, for example, the terminal c on the left side of the signal selecting means S in FIG. 7 corresponds to the left side terminal of the signal selecting means S00 to S4n connected to any one of the outputs of the multipliers M0 to M4 in FIG. is doing.

The third aspect of the present invention shown in FIGS. 6 and 7.
According to the embodiment, using only five multipliers M0 to M4 while using n delay elements D1 to Dn, for example, at least five delay signals of different signal levels with different delay times are combined to output a filter. It can be obtained as a signal.

The present invention is not limited to the number of multipliers and the number of delay elements shown in the embodiments. For example, the inventor prototyped the FIR filter of the third embodiment of the present invention, which has 500 to 600 delay elements and 100 multipliers and is used in the first example of the ghost canceller described above with reference to FIG. ing. According to the ghost canceller FIR filter of the third embodiment, the conventional 500-600 is used.
The number of multipliers can be reduced by 400 to 500, and the cost can be reduced, as compared with the ghost canceller FIR filter using the delay elements.

As a modified example of the third embodiment, the signal selecting means S00 to S4n may be the signal selecting means S having the adder A shown in FIG. 3 and used in the first embodiment. . According to such a modification, it is also possible to add any one of the outputs of the multipliers M0 to M4 and then input the outputs to each of the adders A1 to An.

Therefore, according to such a modification, by using the multipliers M0 to M4 whose use number is limited, the signals of more various signal levels are obtained and input to the respective adders A1 to An. You can

FIG. 8 shows a fourth embodiment of the FIR filter to which the present invention is applied.

The construction of the fourth embodiment is a transposition construction, with the construction of the embodiment of FIG. 1 described above as the basic construction. Therefore, the fourth embodiment can obtain substantially the same effect as the second embodiment using the signal selecting means of FIG.

In FIG. 8, symbols M0 to M4 and Dn
.About.D1, IN and OUT are the same as those having the same reference numerals shown in FIG.

In FIG. 8, adders An to A0 are added.
Is a multi-input, and it is possible to add and output the outputs of all the signal selecting means S0i-S4i in the vertical direction and the fixed delay D _{i +1 in} the preceding stage.

FIG. 9 is a circuit diagram of the signal selecting means used in the fourth embodiment.

In FIG. 9, the signal selecting means S is 1
It is composed of two switching elements SW.

The positions of the two terminals of the signal selecting means S shown in FIG. 9 correspond to the positions of the two terminals of the signal selecting means S00 to S4n shown in FIG. That is, for example, the terminal e on the left side of the signal selecting means S of FIG. 9 is one of the multipliers M0 to Mn of the signal selecting means S00 to S4n of FIG.
It corresponds to the left terminal connected to one output.

FIG. 10 is a block diagram showing a fifth embodiment of the FIR filter to which the present invention is applied.

In the fifth embodiment, a total of four adders A0 are used.
~ A3 only, the second using the signal selection means of FIG.
Almost the same effect as the embodiment can be obtained. That is, in the fifth embodiment, instead of performing the addition at each horizontal stage, the adders A0 to A3 collectively perform the addition.

In FIG. 10, delay elements D1 to Dn are provided.
The multipliers M0 to M3, the adder A, the input terminal IN, and the output terminal OUT are the same as those having the same reference numerals in FIG. 1 described above, and have the same configuration. The signal selecting means S00 to S3n shown in FIG. 10 are arranged at the same positions as those of the signal selecting means S00 to S3n shown in FIG.

FIG. 11 is a circuit diagram of the signal selecting means used in the fifth embodiment.

In FIG. 11, the signal selecting means S is
It is composed of one switching element SW.

The positions of the two terminals of the signal selecting means S of FIG. 11 are the same as those of the signal selecting means S00 to S00 of FIG.
It is plotted corresponding to the positions of the two terminals of S3n. That is, for example, the lower terminal of the signal selecting means S of FIG.
f corresponds to the lower terminal connected to each tap portion of each connection portion of the delay elements among the terminals of each signal selection means S00 to S3n in FIG.

FIG. 12 is a block diagram of an adder used in the fifth embodiment.

That is, the adder Ai shown in FIG.
Represents one of each of the adders A0 to A3 of FIG.

The adder Ai shown in FIG. 12 has n +
It is a multi-input adder that adds the signals input to each input of one input in _{0 to} in _n and outputs the added signals.

According to the fifth embodiment of the present invention shown in FIGS. 10, 11 and 12, a total of 4 × (n + 1) signal selecting means S00 to S3n are provided as in the second embodiment.
It is possible to select a wide range of signal levels of a plurality of delayed signals having different delay times even if one adder is not provided inside.

The number of delay elements, multipliers, and signal selecting means used in the present invention is not limited to the number used in each of the first to fifth embodiments of the present invention described above. . Further, each of the FIR filters of the first to fifth embodiments of the present invention has substantially the same function as the conventional FIR filter described with reference to FIG. 13, and the first FIR filter of the ghost canceller shown in FIG. Example F
It goes without saying that it can be used as an IR filter or an FIR filter of the second example of the ghost canceller shown in FIG.

[0126]

As described above, according to the present invention, a digital filter capable of synthesizing output signals by selecting a wide range of delay times and signal levels from a plurality of delay signals having different delay times is provided. It is possible to obtain an excellent effect that the cost can be reduced by realizing with only a small number of multipliers.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of an FIR filter to which the present invention is applied.

FIG. 2 is a block diagram of a signal selecting means used in the first embodiment.

FIG. 3 is a block diagram of a signal selection means used in the second embodiment of the present invention.

FIG. 4 is a waveform diagram of a reception signal in which a ghost signal is superimposed on a main signal.

FIG. 5 is a circuit diagram showing a connection example of the second embodiment.

FIG. 6 is a block diagram of a third embodiment of an FIR filter to which the present invention is applied.

FIG. 7 is a block diagram of a signal selecting means used in the third embodiment.

FIG. 8 is a block diagram of a fourth embodiment of an FIR filter to which the present invention is applied.

FIG. 9 is a circuit diagram of signal selecting means used in the fourth embodiment.

FIG. 10 is a block diagram of a fifth embodiment of the FIR filter to which the present invention is applied.

FIG. 11 is a circuit diagram of a signal selecting means used in the fifth embodiment.

FIG. 12 is a circuit diagram of an adder used in the fifth embodiment.

FIG. 13 is a block diagram of a conventional FIR filter.

FIG. 14 is an explanatory diagram of a ghost screen based on a ghost signal that is superimposed on a received signal together with a main signal.

FIG. 15 is a radio wave propagation diagram for explaining a ghost generation process.

FIG. 16 is a waveform diagram of an original signal and a received signal in which a ghost signal is superimposed on a main signal corresponding to the original signal.

FIG. 17 is a block diagram showing a first example of a conventional ghost canceller using a digital filter.

FIG. 18 is a block diagram of an FIR filter used in the first example of the conventional ghost canceller.

FIG. 19 is a block diagram showing a second example of a conventional ghost canceller using a digital filter.

FIG. 20 is a block diagram showing a third example of a conventional ghost canceller using a digital filter.

FIG. 21 is a circuit diagram of a variable delay line used in a third example of the conventional ghost canceller.

FIG. 22 is a diagram showing the removal of a ghost signal in the third example of the conventional ghost canceller.

[Explanation of symbols]

10, 12 ... Finite impulse response filter (FIR filter), 14 ... Variable delay line, A, A1 to An ... Adder, D, D1 to Dn ... Delay element, M0 to Mn ... Multiplier, S, S00 to S4n ... Signal selecting means, SW ... Switching element.

Claims (9)

[Claims] 1. A plurality of delay signals having different delay times are input using a plurality of delay elements in a digital filter for obtaining a combined output signal by varying the signal levels of the respective delay signals. A plurality of multipliers that output a signal level as a desired signal level, and a signal selection unit that performs switching selection between the plurality of delay elements and the plurality of multipliers are provided. , A digital filter characterized by obtaining an output signal obtained by combining a plurality of delayed signals having different delay times. 2. The multiple delay elements according to claim 1, wherein the plurality of delay elements are connected in series, each connection portion is provided with a tap for obtaining a delay signal of each delay time, and respective outputs of the plurality of multipliers are added. And the signal is added to the output of the digital filter, and the signal selection means switches and selects between the plurality of taps and the inputs of the plurality of multipliers. 3. The signal selection means according to claim 2, wherein the signal selecting means is provided between each of the plurality of taps and each of the inputs of the plurality of multipliers, and between the corresponding tap and an input of the corresponding multiplier. A digital filter characterized by being switched on or off. 4. The signal selection means according to claim 2, wherein the signal selection means is provided between the plurality of taps and the inputs of the plurality of multipliers, and turns on the corresponding tap to the input side of the corresponding multiplier. A switch for switching between ON and OFF, and an adder for adding a signal on the multiplier side of the switch and an output of another signal selecting means, and a plurality of signals for an input of one multiplier A digital filter characterized in that, when the switch of the selecting means is turned on, signals from taps corresponding to these signal selecting means are added and input to the multiplier. 5. The signal according to claim 1, wherein a signal input to the digital filter is input to each of the plurality of multipliers, and the plurality of delay elements include a plurality of adders for injecting a delayed input signal. A digital filter, wherein the digital filters are alternately connected in series, and the signal selection means selectively switches between the outputs of the plurality of multipliers and one input of the plurality of adders. 6. The adder according to claim 5, wherein the signal selection means is provided between the outputs of the plurality of multipliers and the inputs of the plurality of adders and corresponds to the outputs of the corresponding multipliers. A digital filter characterized by switching between turning on and off between the input and. 7. The adder according to claim 5, wherein the adder is a multi-input adder, and the signal selection means is provided between the outputs of the plurality of multipliers and the inputs of the plurality of adders. The digital filter is characterized in that the output of the corresponding multiplier and the corresponding input of the multi-inputs of the corresponding adder are switched on or off. 8. The multi-input adder according to claim 2, wherein a multi-input adder is provided at each input of the plurality of multipliers, and the signal selecting means is provided between each of the plurality of taps and the plurality of adders. The digital filter is characterized in that the corresponding tap and the corresponding one of the multi-inputs of the corresponding adder are switched on or off. 9. The signal selection means according to claim 1, wherein the selection result of the signal selection means,
A digital filter having an adder for adding the selection results of other signal selecting means.