JPS62284512A - Digital filter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a digital filter and to constitute the circuit suitable to IC-implementation by reading previously stored arithmetic data out of a multiport memory, and multiplying the read arithmetic data by a constant respectively and calculating the sum of the resulting values. CONSTITUTION:A digital input signal AIN is inputted to a shift register 1 and delayed in order, and bits of the same digit, e.g. MSB, 2nd MSB-LSB are extracted by an address generating circuit 3 in what is called a bit slice form from the delayed signal to generate plural address signals, which are inputted to the multiport memory 4 to read the previously stored arithmetic data. The read arithmetic data are inputted to a sum calculating circuit 5 and filtered as desired to output the result, so that the circuit scale is decreased and the circuit constitution suitable to IC-implementation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter that performs filter processing of a digital input signal using a small circuit configuration.

〔overview〕

This invention reads pre-stored arithmetic data from a multi-dye memory using the same digits of digital input signals delayed in bit parallel in a batch manner using a shift register as address signals, and By calculating the sum of the values obtained by multiplying the calculated data by a constant, it is possible to reduce the circuit scale and construct a circuit that can be integrated into an IC. is constructed using a multiplier circuit, a delay circuit, an adder circuit, etc., among which the following methods are known as methods for implementing the multiplier circuit.

(A serial multiplication method consisting of 11 logical operation circuits.

This method is used in the fields of low-speed communication and voice processing, and although the circuit scale is small, it is not suitable for high-speed processing because the addition of partial products is performed in a time-sharing manner.

(2) A parallel multiplication method consisting of multiplier circuits installed in parallel;
This method has been adopted in the field of digital audio, etc., and although high-speed processing is possible, the circuit size is large.

(3) A method consisting of a bit shift circuit and performing only multiplication to the power of 2. This method is used in the field of digital image processing, etc., and can be used when the filter specifications are fixed. However, since it is a completely dedicated circuit and lacks versatility, it can only be used in circuits that can be mass-produced and are cost-effective.

(4) Instead of a multiplier, the multiplication results are stored in ROM or RA.
A memory multiplication method in which a table map is stored in M and a desired multiplication result is obtained from the table map using a multiplier as an address signal. This method is often used for high-speed multiplication along with the parallel multiplication method (2). When a ROM is used as the memory, the filter specifications are fixed, but the circuit configuration itself does not change even if the filter specifications are changed, which is different from the method (3). Also, RA in memory
When using M, the contents of the RAM can be rewritten and filter specifications can be changed, although at a low speed, so real-time processing is possible except when power is turned on or when filter characteristics are switched. Particularly in the case of image processing, it is practical because the RAM can be rewritten during blanking time.

[Problem that the invention seeks to solve]

The memory multiplication method has the disadvantage that, assuming the multiplication input word length is B, the required memory capacity is 2 m words for one multiplier, and the memory capacity increases rapidly as the word length increases.

[Means for solving problems]

The digital filter according to the present invention includes a shift register 1 that sequentially delays a digital input signal AIN in parallel bits in a batch manner, and a bit of the same digit in the signal that is sequentially delayed by using this shift register 1. an address generation circuit 3 that extracts address signals in a bit-slicing manner and generates address signals; and an address generation circuit 3 that stores pre-computed filter operation results as operation data, and duplicates each operation data corresponding to a plurality of input address signals. A multi-port memory 4 configured to be readable by PJE, and a sum calculation circuit 5 that receives the calculated data read from the multi-port memory 4 and calculates the sum of the results of multiplying the calculated data by a predetermined constant or bit-shifting the data. It consists of

[Effect]

The digital input signal AID is input to the shift register 1 and sequentially delayed, and from this delayed signal, the address generation circuit 3 generates bits of the same digit, for example, MSB, 2nd
MSB...LSB is extracted in a so-called bit slicing manner to generate a plurality of address signals, and the plurality of address signals are input to the multi-port memory 4, and pre-stored calculation data is read out respectively. By inputting the read calculation data to the summation circuit 5 and outputting the result of desired filter processing, it is possible to reduce the circuit scale and create a circuit configuration that can be integrated into an IC.

〔Example〕

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, the shift register l is, for example, a register R to R1 each having parallel input/output terminals of B bits.
It is arranged so as to be convenient for adding delay tuffs multiplied by symmetric coefficients of a linear phase FIR type digital filter, and the B-bit input signal AIH input to register R1 is sequentially delayed. B-bit parallel tap output signals sequentially delayed by, for example, one clock cycle are output from the output terminals of this register R5 and the registers Rt to R6 connected thereto.

Each of the 9-bit digital signals output from these registers R3 to R8, as shown in the figure, the output signals of registers R1 and R6, Rt and R1, R3 and R&, and R4 and R2, each has a calculation capacity of B+1 bits. Adder 2-1
to 2-4 and calculate the sum. As a result, the number of signals to be multiplied can be reduced by half.

The address generation circuit 3 extracts bits of the same digit from the addition outputs from the adders 2-1 to 2-4 in a bit slicing manner to generate a plurality of address signals.

The multi-port memory 4 is configured so that the filter operation results for each bit digit, which are stored in advance as operation data in association with the address signals, can be read out in an independent manner using a plurality of address signals manually. The memory has address inputs of 1 and a plurality of output ports, and the sum outputs of each of the adders 2-1 to 2-4 extracted by bit slicing the bits of the same digit in the address generation circuit 3 are It is input as the address of .

The sum calculation circuit 5 inputs the calculation data read from the multi-port memory 4, multiplies the calculation data by a predetermined constant or bit-shifts the data, calculates the sum of the results, and obtains a filter output.

This is based on the fact that multiplication can be constructed by adding the partial products of the multiplier with the multiplicand bitwise. F I R (Finite Impuls)
In the eRe5ponse) type digital filter, input data is guided to a delay circuit (for example, shift register 1), the data at each tap of this delay circuit is multiplied by a filter coefficient, and all of the multiplication results are added to form the filter. The calculation output is obtained by first calculating the partial products of the filter coefficients for the upper digits of each bin of the data output from each tap of the delay circuit, and then considering the bit digit weighting of all these partial products. At this time, of course, the order of addition does not matter, so you can obtain the same calculation result by dividing the input word length or number of taps arbitrarily, and adding the outputs. .

A more detailed embodiment of the present invention and its operation will be described using FIG. Elements similar to those in FIG. 1 are given the same numbers and their explanations will be omitted.

In FIG. 2, shift register l is, for example, registers R to R4 each having 9-bit parallel input/output terminals.
A shift register 1-1 consisting of a shift register 1-1 and a shift register 1-2 consisting of registers R2 to R1 are arranged in parallel, and an output signal A is obtained by sequentially delaying an input signal AI and an input signal BIN, respectively. uT and output signal B. uT
It is configured to obtain a 9-bit parallel tap output from the output terminals of each register R to R8. Therefore, when input signal AH)1 is input from this register R1, this register RI and the signals connected thereto are For example, 9-bit parallel tap output signals sequentially delayed by one clock cycle are output from the registers R2 to R4, and similarly, the output signal A output from the register R4 is output from the registers R2 to R4.
. By inputting LIT to register R2 as input signal B1o, 9-bit parallel tap output signals sequentially delayed by, for example, one clock cycle are output from register R3 and registers R8 to R6 connected thereto. Note that a switch is provided between registers R3 and R4 to switch the number of taps to an even number or an odd number. You can switch to .

The 10-bit signal obtained by adding the 9-bit parallel tap output signals output from registers R1 to R8 by adders 2-1 to 2-4 is sent to a flip-flop (FF).
) 3-1 to 3-40 to 1--1El −/3 to T1
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...LSB is extracted in a so-called bit-sliced manner. This flip-flop (FF) 3-1 or 3
-40 is not necessarily required originally, but is required when high-speed processing is performed by pipeline processing.

The extracted signal is inputted to the multiport memory 4-1.4-2 as an address signal, and the filter calculation results for each bit digit, which are stored in advance as calculation data in association with the address signal, are independently stored. output in the following format. The multiport memories 4-1, 4-2 each have, for example, 16 words and 5 ports. The number of taps in shift register 1 is halved to 4, so the memory capacity only needs to be 2'-16 (hood).The input word length is 9 bits, but becomes 10 bits by addition. Therefore, we prepared for 10 boats. In this embodiment, the word length is divided into two by providing two multiport memories. For each of the multi-port memories 4-1, 4-2, an input port (not shown) is separately prepared for writing predetermined calculation results and the like. On the other hand, in the case of reading, it is possible to read from all the ports at the same time, and even if the exact same address is input to each address terminal, the calculation results corresponding to the addresses are in a so-called independent manner. It can be read from each boat.

The sum calculation circuit 5 is composed of an adder in register R1, and multipliers (e.g., "x2", "x4", etc.). Since it weights each bit digit based on the principle of bit slicing when a signal is generated, it is simple and requires only bit shift wiring.

Further, based on the address signal generated by extracting the MSB, the operation data read from the multiport memory 4-1 is subtracted. This is because this circuit assumes that data is handled in two's complement representation.

Further, the adder 5-1 is for tap expansion, and is for expanding the number of taps by vertically connecting digital filters having the configuration shown in FIG. In this case, in order to expand the number of shift registers R5 (i is from 8 to 8), it is sufficient to prepare a plurality of shift registers identical to those shown in FIG. 2 and connect them vertically. . uT is input to the input signal AIN of the next stage, and the output signal B of the previous stage is input to the input signal BI of a certain stage. Enter u7.

In the final stage shift register, an odd tap filter or
Alternatively, the above-mentioned switch SW is switched depending on whether the filter is an even tap filter or not. In cases other than the final stage, this SW connects shift register R5 and shift register R&. Further, the filter calculation output signal cour is inputted to the filter calculation input signal CIN of the next stage. At the time of expansion, the filter calculation input signal C0 becomes an input signal from the outside, and the filter calculation output signal C0u1 becomes an output signal to the outside.

Note that since the multiport memory 4 is configured using RAM, the memory contents cannot be rewritten.
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A! - For example, when used to separate Y (luminance signal) and C (color signal) on a TV, the filter specifications can be easily changed to the desired contents by rewriting the contents during blanking time. It is possible to change to .

As explained above, an address signal is generated by extracting bits of the same digit of each delayed input signal in a so-called bit slicing manner, and this generated address signal is sent to the multiport memory 4-1.4- 2, the desired calculation results are read out, and filter processing is performed, making it possible to construct a digital filter with an extremely small circuit scale.

〔Effect of the invention〕

As explained above, according to the present invention, large signals are generated at the same digits of input signals that are delayed in parallel using a shift register in a so-called bit-sliced manner. This is because a configuration is adopted in which the pre-stored filter calculation results for each bisoto digit are read out using each address signal, and the sum of the values obtained by multiplying each of the read out calculation results by a constant is used. ,
It is possible to configure a digital filter that has a small circuit scale and is suitable for IC implementation. Further, by performing pipeline processing, filter calculation processing can be performed even faster.

[Brief explanation of the drawing]

FIG. 1 shows the basic configuration of the present invention, and FIG. 2 shows the configuration of one embodiment of the present invention. In the figure, 1 is a shift register, 2-1 to 2-4.5-
1 is an adder, 3 is an address generation circuit, 4.4-1.4-
2 represents a multiport memory, and 5 represents a summation circuit.

Claims (1)

[Claims] A shift register for sequentially delaying digital input signals in parallel bits in a batch manner; and bit slicing of bits of the same digit in a signal obtained by sequentially delaying the digital input signal using the shift register. an address generation circuit that extracts and generates an address signal in a certain manner; and an address generation circuit that stores pre-calculated filter operation results as operation data, and can read out the above operation data in an overlapping manner in response to a plurality of input address signals; a multi-port memory configured as such, and a sum calculation circuit that calculates the sum of the results of multiplying or bit-shifting the arithmetic data read from the multi-port memory by a predetermined constant; A digital filter characterized by being configured to output an output result.