JPS6155689B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital multiplication circuit, in which a multiplication coefficient is expressed as the sum or difference of an integer and a decimal number, and the integer part is subjected to, for example, a bit shift, and the decimal part is multiplied by a multiplier, and then both are calculated. It is an object of the present invention to provide a digital multiplication circuit that has almost no calculation error due to multiplication even in a multiplier with a small number of bits, and can significantly reduce coefficient quantization errors. Generally, in systems that record and reproduce discrete digital signal sequences such as pulse code modulation (PCM) signals, digital filters, level attenuators, attenuation, etc. are used to change the level and frequency characteristics of the discrete digital signal sequence. However, these digital signal processing circuits especially require an extremely important basic operation called digital multiplication processing. The digital multiplication circuit that performs this digital multiplication process requires a digital multiplier (hereinafter simply referred to as a multiplier) using a large-scale integrated circuit (LSI), but since the number of bits in this multiplier is limited, Finite word length operations are required. FIG. 1 shows a block diagram of an example of a conventional digital multiplication circuit. In the figure, a discrete digital signal sequence input to an input terminal 1 is supplied to a multiplier 2, where it is multiplied by a coefficient from a coefficient multiplier 3 and then output to an output terminal 4. Now, the input discrete digital signal sequence at time nT is x _o and time nT
The output discrete digital signal sequence at y _o ,
Furthermore, when the coefficient is a, y _o is expressed by the following equation.
However, T is a discrete digital signal sequence x _o , y _o
indicates the sampling time of y _o =a·x _o (1) In equation (1), the coefficient a is expressed by the complement of the following equation, for example, where N is the word length. However, in equation (2), β _p indicates the value of the sign bit (polarity bit) of the most significant bit (MSB), and β _j indicates the value of each bit other than the MSB, both of which are 0 or 1. be. Here, the coefficient a is a decimal number expressed as a digital value (usually a value in two's complement representation), and since the number of words is limited as shown by N, there are cases where the decimal number cannot be expressed accurately. be. That is, a quantization error occurs because the coefficients are quantized with a finite word length. To explain this concretely, for example, if the coefficient a ₁ is
1.03125, a ₂ is 1.25, and these are expressed in two's complement notation as becomes. However, equation (3) and others are expressed in fixed-point numbers, and the maximum normalization value when converted to a bit pattern is 2. Therefore, the word length N of coefficient a is 7
There is no problem if N is 4 bits, but if N is 4 bits, then When formula (4) is expressed in decimal notation, a ₁ is 1.0, a ₂ is 1.25, and the value of a ₁ is the original value.
It will be represented as something different from 1.03125. Therefore, conventionally, in order to suppress this coefficient quantization error within a predetermined range, it is necessary to increase the word length N of the coefficients, and for this reason, when the multiplication word length of the multiplier is limited, The disadvantage is that the scale of the digital multiplication circuit must be increased, making it large and expensive. The present invention eliminates the above-mentioned drawbacks, and embodiments thereof will be described below with reference to FIGS. 2 and 3. FIG. 2 shows a block diagram of a first embodiment of the digital multiplication circuit according to the present invention. In the figure, a discrete digital signal sequence inputted to an input terminal 5 is supplied to a multiplier 6, where a coefficient α from a coefficient multiplier 7 is input.
While multiplied by ⁱ , shift register 9 described later
supplied to The coefficient α ⁱ is determined according to the following calculation algorithm. Assuming that the coefficient to be multiplied by the input discrete digital signal sequence x _o is a as shown in equation (2), this is expressed as the sum or difference of an integer and a decimal. a=±L±α (5) However, in formula (5), L is an integer and α is a decimal. (Five)
Rewrite the equation further to obtain the following equation. a=±L±(2 ⁱ・α)・2 ^-i (6) As can be seen from equation (6), when multiplying the coefficient a by the discrete digital signal sequence x _o , for the integer L, the bit shift It can be achieved by selection, and 2
Multiplying by ^-i requires shifting i bits to the right, so
The multiplication operation can be considered to be a problem of only 2 ⁱ ·α, and this 2 ⁱ ·α is the above-mentioned α ⁱ . This will be further explained with specific examples.
Now, the coefficient a ₁ of equation (3) is expressed as the discrete digital signal sequence x
Considering the case where the output digital signal sequence y _o is obtained by multiplying o as shown in equation (1), equation (3 ₎ can be rewritten as follows. a ₁ = 01.00001 = 01.00000 + 00.00001 Expressing this in decimal notation, a ₁ = 1 + α ₁ = 1 + (2 ⁱ・α ₁ )・2 ^-i (7) Here, if i is 5, equation (7) is obtained. 2 ⁱ・ on the right side of
α ₁ becomes 2 ⁵ · α ₁ , which is defined as α ₁ ⁵ . That is, if the coefficient word length is 4 bits, α ₁ ⁵ becomes α ₁ ⁵ =01.00 (8). Therefore, applying equations (7) and (8) to equation (1), y _o = a ₁・x _o = x _o + α ₁ x _o = x _o + α ₁ ⁵・2 ^-5・x _o
(9) becomes. As mentioned above, the output coefficient α ⁱ of the coefficient unit 7 is expressed as (5)
This is the value obtained by shifting the value of the decimal α in the equation to the left by i bits, and when performing the multiplication in equation (9), the value obtained by shifting the value of the decimal decimal α in equation (8) to the left by 5 bits is α ₁ ⁵ , Therefore, the output signal of the multiplier 6 is represented by x _o ·α ₁ ⁵ . The output signal x _o · α ₁ ⁵ of this multiplier 6 is supplied to the next stage shift register 8, where it is shifted to the right by 5 bits to become α ₁ ⁵ · 2 ^-5 · x _o , and then the arithmetic unit 10 is supplied to However, these bit shifts are
This is not done for the MSB since it is a sign bit. On the other hand, here, it is normalized by 2, and since the integer 1 in equation (7) is 1/2 of 2, the input digital signal sequence _xo is shifted to the right by 1 bit by the shift register 9, and then sent to the arithmetic unit Here, it is added to the signal from the shift register 8. As a result, the digital signal series y _o expressed by equation (9) is taken out from the arithmetic unit 10, and the output terminal 1
Output to 1. As is clear from the above explanation, when multiplying the coefficient a ₁ expressed by equation (3) by the input digital signal sequence x _o , even if the coefficient word length of the coefficient unit 7 is a 4-bit shift, the coefficient is Since coefficient information is not lost by setting ⁱ , coefficient quantization errors can be significantly reduced compared to the conventional method, and calculation errors due to multiplication can also be reduced. Next, the second embodiment of the circuit of the present invention will be explained with reference to FIG. 3. FIG. 3 is a block system diagram of the second embodiment of the circuit of the present invention, and the same components as in FIG. 2 are given the same numbers. The explanation will be omitted. When performing the multiplication in equation (9), the shift register 12 shifts the input discrete digital signal sequence x _o to the right by 5 bits (excluding the MSB) and supplies the signal to the multiplier 13 . The multiplier 13 multiplies the output signal of the shift register 12 by the coefficient α ^j (here α ₁ ⁵ in equation (8)) from the coefficient unit 14 and supplies the obtained signal to the arithmetic unit 10, where the shift register Add it to the signal from 9. That is, in this embodiment, the digital signal supplied to the multiplier 13 is bit-shifted in advance and then supplied to the multiplier 13, and has the same features as the first embodiment. In the above embodiment, L was explained as one integer, but if the maximum value of normalization when converted to a bit pattern is MAX, then ±MAX, ±1/
2 (MAX), ±1/4 (MAX), ......, as 0 (6)
Express according to the formula, i.e.,

It may also be expressed as the sum of [Formula] and multiple integers (M represents the number of separations). Also, when the coefficient value is converted into a decimal number, for example, if it is between 1 and 1.5, the coefficient is set to 1 + α, and when it is between 1.5 and 2, the coefficient is set to 2 -
It is preferable to perform multiplication as α according to the arithmetic algorithm described above because the number of quantization bits is small. Note that the shift register 9 may be unnecessary depending on the value of the integer L of the coefficient (for example, if the coefficient is expressed as 2-α, the value of the integer L is equal to the maximum normalization value 2). Since they are equal, x _o is a direct operator 10
is supplied to ). It is also possible to heavily shift the value α of the decimal part to the right. As described above, the digital multiplication circuit according to the present invention divides the coefficient to be multiplied into the sum or difference of an integer part and a decimal part, and bit-shifts the value of the decimal part to the left or right to obtain a coefficient. is output from the coefficient unit to the multiplier and shifted to the right or left by the input or output bit shift of the multiplier, and the input discrete digital signal sequence is bit-shifted or This is because the digital signal sequence taken out without bit shifting is calculated by the arithmetic unit on the digital signal sequence which has been multiplied by the multiplier and bit shifted by the shift register, respectively, and the multiplied output signal is output from the arithmetic unit. ,
Even if the word length of the output coefficients of the coefficient unit is short, the coefficient information is not lost, and as a result, coefficient quantization errors can be significantly reduced compared to conventional methods, and calculation errors due to multiplication are also reduced. Moreover, since the coefficient error length can be shortened, the multiplier can be constructed easily, inexpensively, and compactly.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an example of a conventional circuit, and FIGS. 2 and 3 are block system diagrams showing respective embodiments of the circuit of the present invention. 1, 5... Discrete digital signal sequence input terminal, 2, 6, 13... Multiplier, 3, 7, 14...
Coefficient unit, 4, 11... Discrete digital signal sequence output terminal, 8, 9, 12... Shift register, 1
0...Arithmetic unit.

Claims (1)

[Claims] 1. In a digital multiplication circuit that obtains a multiplier output signal by supplying a coefficient of a certain finite word length from a coefficient unit and an input discrete digital signal sequence to a multiplier, the coefficient to be multiplied is calculated by calculating the sum of an integer part and a decimal part. The coefficient of the value obtained by bit-shifting the value of the decimal part to the left or right is output from the coefficient unit to the multiplier, and the input or output digital signal sequence of the multiplier is transferred to a shift register. The input discrete digital signal sequence is shifted to the right or left by the above bit shift amount, and the input discrete digital signal sequence is bit-shifted or extracted without bit-shifting in relation to the value of the integer part of the coefficient to be multiplied. 1. A digital multiplication circuit characterized in that a digital signal sequence subjected to multiplication by a multiplier and a bit shift by a shift register is operated on by an arithmetic unit, and a multiplication output signal is output from the arithmetic unit.