JPH0689300A - Data processing method for lti system - Google Patents

Abstract

PURPOSE:To improve a system characteristic, to reduce the circuit configuration, and to speed up the data processing by representing each system constant in floating-point by limiting the range of the size of an exponential part. CONSTITUTION:Input data x[n] represented in fixed point is written in a RAM 4 by a write-in address Aw from a first address generator 5. On the other hand, the input data x[n] stored in the RAM 4 is read out by a read-out address Ar from the first address generator 5, and is given to a multiplying function part 8. Namely, in concrete terms, the input data x[n] for which a prescribed arithmetic operation is exculable and which is multiplied by a mantissa hm to be exponential part pm=-Q, is read successively out of the RAM 4, after that, the input data x[m] to be multiplied by the mantissa hm to be exponential part pm=-Q+1, is read out successively, and after that, the input data x[n] to be multiplied by the mantissa hm to be exponential part=-Q+2 is read out successively, and all the input data x[n] are read out by turns in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing method for an LTI (linear time invariant) system suitable for digital signal processing such as FIR digital filters and cross-correlators.

[0002]

2. Description of the Related Art Generally, input data is x [n] and a system constant representing an impulse response is h [m] (m = 0, 1,
2 ... N-1), the LTI system that can obtain the output data y [n] from the following [Equation 1] formula that performs the convolution operation of the input data x [n] and the system constant h [m] is It is known that if the system constant h [m] is a tap coefficient (filter coefficient) representing an impulse response,
This LTI system is a FIR digital filter.

[0003]

[Equation 1] Since the equation (1) can find the cross (auto) correlation between the input data x [n] and the system constant h [m], this LTI system can be regarded as a cross (auto) correlator.

By the way, this type of LTI system is used for FI.
When configured as an R digital filter, since the input data x [n] and the output data y [n] are usually expressed in fixed point, the tap coefficient (system constant) h [m] is also downsized and calculated. The fixed-point expression is used for the purpose of ensuring high-speed processing, and the equation [1] has been subjected to arithmetic processing (data processing) by the fixed-point.

FIG. 2 shows a block configuration circuit of an FIR digital filter capable of executing such data processing.
According to this FIR digital filter, [Formula 1]
The arithmetic processing of the equation is faithfully executed by the fixed point, and one output data (output value) y [n] is obtained. Less than,
An outline of the FIR digital filter 50 shown in FIG. 2 will be described.

First, the input data x expressed in fixed point
[N] is the write address A from the first address generator 52.
W is written in the RAM 51. In this case, the write address Aw is 0000 _H ... FFFF _H , 0000 _H ...
It is generated cyclically like FFFF _H , and the number of taps is required to be the minimum number of taps. Input data x
The reason why [n] is once written in the RAM 51 is that when the data processing is implemented by hardware, the circuit scale increases as the number of taps increases, and pipeline processing becomes difficult.

On the other hand, the input data x [n] stored in the RAM 51 is read in the written order by the read address Aor from the first address generator 52 and given to the multiplication function unit 53. In this case, if the number of tap coefficients is 256, for example, the read address Aor is
0000 _H ... 00FF _H , 0001 _H ... 0100 _H , 000
2 _H ... 0101 _H , 0003 _H ... 0102 _H are sequentially generated.

On the other hand, tap coefficient h expressed in fixed point
[M] is stored in the ROM 54 in advance, is sequentially read by the read address Aof from the second address generator 55, and is given to the multiplication function unit 53. Then, the multiplication function unit 53 executes the multiplication of the tap coefficient and the input data, that is, the multiplication processing of h [m] · x [nm]. In addition, the obtained multiplication result is given to the addition function unit 56, and the sum of the multiplication results, that is, the above-mentioned [Equation 1] is obtained.

Numeral 57 is a selector for initializing the addition function unit 56 every time the summation by the Σ symbol of the equation [1], that is, output data (output value) y [n] is obtained, and 58 is an addition function. A rounding function unit that rounds the addition result obtained from the unit 56 to a required number of bits, and 59 is a timing signal generator that gives a timing signal to each block.

[0010]

However, the above-mentioned FI
In the conventional data processing method in the R digital filter 50, since the input data x [n] and the tap coefficient (system constant) h [m] are both processed by the fixed-point representation, the quantization error and the calculation error increase. There is a problem that the filter characteristics are deteriorated.

On the other hand, in order to reduce the quantization error, the tap coefficient h [m] is expressed as a floating point, and the input data x [n] is expanded and interpreted as a floating point expression to float the above equation [1]. It is possible to calculate the output data y [n] by converting it to a fixed-point expression after performing calculation by the decimal point expression. However, if such a simple conversion process is performed,
A new problem arises that the circuit scale becomes large and the data processing time becomes long.

The present invention solves the problems existing in the prior art as described above, and improves the system characteristics by eliminating the quantization error and the calculation error. In addition, the circuit configuration is reduced and the data processing is performed. It is an object of the present invention to provide a data processing method of an LTI system capable of realizing high speed.

[0013]

According to the data processing method of an LTI system of the present invention, a fixed-point representation of an input data x [n] and a system constant h [m] are processed to produce an output represented by a fixed-point representation. When obtaining the data y [n], each system constant h [m] is expressed as a floating point by limiting the range of the exponent size, and the system constant h [m] whose absolute value is a certain size or more. Is converted into a plurality of system constants h ′ [m] and h [m], and mantissa parts hm and h ′ of the respective system constants h ′ [m] and h [m] are converted.
m and each input data x [n] are multiplied by a fixed point,
And the multiplication results executed for the system constants h '[m] and h [m] having the same exponent parts pm and p'm are added by a fixed point to obtain a partial sum, and also to each different exponent part. The partial sums are added by fixed point, for example, the partial sums corresponding to the system constants h '[m] and h [m] having small exponents pm and p'm are sequentially added to output data y [n]. It is characterized by finding the sum total for

[0014]

According to the data processing method of the LTI system according to the present invention, first, each system constant h [m] is an exponent part pm.
The floating-point expression is limited to the range of the magnitudes of the system constants, and the system constants whose absolute values are equal to or greater than a certain magnitude are converted into a plurality of system constants h ′ [m] and h [m].

The reason for converting the system constant into such a floating point representation is as follows. Usually, when the value of the system constant is expressed by Q-bit fixed point, most of the system constants take a value near zero without taking the full-scale value. For this reason, most of the upper bits of the system constant are not used for the arithmetic processing, and in the end, the Q-bit arithmetic processing is extremely wasteful.

On the other hand, if the system constant is expressed in floating point, the word length of the mantissa part is reduced, and each bit can be effectively utilized in the arithmetic processing. However, even if the floating point representation is simply used, since the input / output data is represented in the fixed point representation, each bit may not contribute to the final result of the arithmetic processing. Therefore, in order not to unnecessarily widen the range of values that the mantissa can take, a conversion method is adopted in which R bits are extracted from the system constant that is expressed in Q-bit fixed point in advance and expressed in floating point.

On the other hand, the value near the zero in the system constant is shorter than the word length R of the input / output data because only the carry part contributes to the final result by the arithmetic processing for obtaining the partial sum. May be. However, since all the bits near the full scale can contribute to the final result, if the word length of the mantissa is shorter than the word length of the input / output data, it causes a quantization error of the system constant, and in the end correct operation I can't get any results. Therefore, in general, arithmetic processing is performed with a relatively short error length of R bits, and for values near full scale (absolute value is 2 ^-S or more), it is divided into two, S bits and R bits. It was made to process.

The system constants are expressed in floating point,
And when the arithmetic processing is performed by the above-mentioned method, the values near the full scale are duplicated, but the system constants that take values near the full scale are compared to the total number of system constants. Since it is extremely small, the influence on the calculation time is extremely small. Therefore, highly accurate and high-speed arithmetic processing is realized.

Next, a specific processing procedure based on the data processing method according to the present invention will be described. First, │h [m] │
The maximum value of is normalized to 1-2 ^-Q (Q: positive integer). Next, | h [m] | is linearly quantized, and is expressed by a Q-bit fixed point, and this is set ^to ˜h [m]. The bit weights in ^~ h [m] are 2 ^-1 , 2 ^-2 , 2 ^-3 ... 2 ^-Q from the higher order to the lower order. And
Floating point representation the ^{~ h} [m] according to the conditions of ~ shown below. In addition, "INT ()" described below is ()
Represents the largest integer that does not exceed the value in.

^~ H [m] <2 ^{-Q + R} (R: 0 <R <Q
When an integer) as the, in this case, exponent pm = -Q, and mantissa hm = INT (h [m] / 2 pm), ~ h [m]
≈hm × 2 ^pm The mantissa part hm is expressed by R bits, and when h [m] can take a negative value, a sign bit is added to hm and expressed by R + 1 bits.

[0021] ^{2 -Q + R ≦ ~ h [} m] <2 -S (S: 0 <
If S <Q), in this case, the exponent part pm = I
NT (log ₂ | h [m] |) -R + 1, mantissa hm = IN
T (h [m] / 2 ^pm ), and ^~ h [m] ≈hm × 2 ^pm . The number of bits of the mantissa part hm conforms to.

[0022] ^~ h [m]> time of 2 ^-S, in this case,
Exponent part p'm = -S, mantissa part h'm = INT (h [m]
/ 2 ^pm ) system constant and exponent part pm = INT (log ₂
{│h [m] │-hm × 2 ^-S })-R + 1 (pm≤-Q
If so, pm = −Q), mantissa part hm = INT (h [m]
/ 2 ^pm ) system constants. That is, ^~ h
[M] ≈h′m × 2 ^p ′ ^m + hm × 2 ^pm . In this case, the mantissa part h'm is represented by S bits, and when h [m] can take a negative value, it is represented by S + 1 bits by adding a sign bit, like hm.

The above floating-point representation method means that R bits can be extracted with the highest precision from the Q-bit system constant, and both S bits and R bits can be extracted from the system constant having a large absolute value.

On the other hand, according to the above-mentioned floating point representation,
[Equation 1] can be rewritten as the following [Equation 2],
The equation (2) is used in the data processing method of the present invention.

[0025]

[Equation 2] The following [Formula 3] in the formula [2] means a partial sum of hm · x [n−m] with respect to m where pm = −Q.

[0026]

[Equation 3] Therefore, it is possible to perform the arithmetic processing for obtaining the output data by the formula [2]. In this case, in order to speed up data processing and simplify the circuit, arithmetic processing is performed in the following procedure.
First, a partial sum obtained by adding each multiplication result for each multiplication result executed for system constants having the same exponent part, that is,
[Equation 3] is obtained by fixed point arithmetic. Next, the obtained partial sums are added in the ascending order of the exponent part pm to obtain the total sum, that is, y [n] in the formula [2] by fixed-point arithmetic. In this case, the bit of the partial sum of the exponent part pm = -Q is shifted to the lower side by 1 bit and added to the partial sum of the exponent part pm = -Q + 1, and the bit of this partial sum is further shifted to the lower side by 1
Bit-shifting is performed, and the partial sums are sequentially added such that the partial sums of the exponent part pm = −Q + 2 are added to obtain the total sum.

Since such an addition process includes a process of aligning decimal point positions by bit shift, it can be called a pseudo-floating point operation. In particular, by adding partial sums in the order of increasing exponent part pm, an operation error is generated. It can be reduced.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments according to the present invention will be described in detail with reference to the drawings.

First, the configuration of an LTI system capable of implementing the data processing method according to the present invention will be described with reference to FIG. The embodiment is an example of the LTI system, which is F
An IR digital filter is shown.

In FIG. 1, reference numeral 1 denotes an FIR digital filter, which has an input section 2 for input data x [n] and output data y.
The output unit 3 of [n] is provided. In the digital filter 1, 4 is a RAM, which stores the input data x [n] input from the input unit 2. A first address generator 5 generates a write address Aw for writing the input data x [n] in the RAM 4 and a read address Ar for reading from the RAM 4. in this case,
The read address Ar corresponds to the latest write address Aw,
Input data x so that the operation of the above [Formula 2] can be executed.
Read [n]. That is, specifically, the exponent part p
Input data x [n] multiplied by the mantissa hm for which m = -Q
Of the input data x [n], which is multiplied by the mantissa part hm with the exponent part pm = −Q + 1, and then with the mantissa part hm with the exponent part pm = −Q + 2. [n] are sequentially read, and thereafter, the same reading is sequentially performed.

On the other hand, 6 is a ROM, which is a system constant h
Mantissa part h of tap coefficient (filter coefficient) that is [m]
m and h'm are stored. In this case, the mantissa part hm,
h'm is preset based on the conditions described in the above-mentioned "action" column. The mantissa parts hm and h'm are stored in an order that facilitates multiplication with the input data x [n] read from the RAM 4. Since it is unnecessary to store the exponent part pm, the ROM capacity can be reduced. A second address generator 7 generates a read address Af for reading the target mantissa part hm from the ROM 6.

On the other hand, 8 is a multiplication function unit, which multiplies the mantissa part of the tap coefficient and the input data, that is, hm × x [n-
[m] is processed by a fixed point. Reference numeral 9 denotes a first addition function unit, which is a partial sum obtained by adding each multiplication result for each multiplication result executed for tap coefficients having the same exponent part pm, that is, Σhm · x [ n-
[m] is processed by a fixed point. Note that 10 is Σ
It is a selector that initializes the first addition function unit 9 every time the summation by symbols is obtained.

Reference numeral 11 denotes a second addition function unit, which calculates a total sum obtained by adding all the partial sums shown in [Equation 3] obtained from the first addition function unit 9 using a fixed point. In addition,
A selector 12 initializes the second addition function unit 11 every time the sum of [Equation 3], that is, y [n] in the above [Equation 2] is obtained. On the other hand, 13 is the second addition function unit 1.
A shift bit unit for shifting the output of 1 to the lower side by 1 bit. This shift bit unit 13 can be realized only by wiring that does not require a circuit element.

In addition, 14 is a gain correction function unit that multiplies the addition result obtained from the second addition function unit 11 by a gain correction constant, and a rounding function that converts the gain-corrected value into a required word length and outputs it as output data. It is an output processing unit including a unit. With such a gain correction function unit, it is possible to correct the filter gain generated by expressing the values forming the tap coefficient in floating point. Reference numeral 15 is a timing signal generator that gives a timing signal to each block. The function in each block can be realized by either hardware or software.

Next, the function of the FIR digital filter 1 including the data processing method according to the present invention will be described with reference to FIG.

First, input data x represented in fixed point
[N] is the write address Aw from the first address generator 5.
Is written in the RAM4. In this case, the write address Aw is 0000 _H ... FFFF _H , 00 as in the conventional case.
It is cyclically generated like 00 _H ... FFFF _H.

On the other hand, the input data x stored in the RAM 4
[N] is the read address A from the first address generator 5.
It is read by r and given to the multiplication function unit 8. That is, specifically, the mantissa part h where the exponent part pm = -Q, where the operation of the above [Formula 2] can be executed from the RAM 4,
The input data x [n] that is multiplied by m is sequentially read, and then the input data x [n] that is multiplied by the mantissa part hm with the exponent part pm = −Q + 1 is sequentially read, and then the exponent part p
Input data x to be multiplied by the mantissa part hm such that m = -Q + 2
All the input data x [n] are sequentially read such that [n] is sequentially read.

On the other hand, from the ROM 6, the mantissa parts hm and h'of the tap coefficients can be calculated so that the operation of the formula [2] can be executed.
m is read in the order set in advance by the read address Af from the second address generator 7 and given to the multiplication function unit 8.

The input data x [n] read from the RAM 4 and the mantissa parts hm and h'm of the tap coefficients read from the ROM 6 are multiplied by the multiplication function unit 8. That is, hm · x [n−m] is calculated by the fixed point. This multiplication result is given to the first addition function unit 9, and the partial sum obtained by adding each multiplication result for each multiplication result executed for the tap coefficient having the same exponent part pm, that is, [Formula 3] is a fixed point. It is processed. On this occasion,
Each time the [Equation 3] is obtained by the selector 10,
The first addition function unit 9 is initialized.

The partial sum obtained by the first addition function unit 9 is given to the second addition function unit 11, and the above [Formula 3]
The total sum of the partial sums indicated by is calculated by the fixed point. In this case, the shift bit unit 13 is the second addition function unit 1
The selector 12 has a function of shifting the output of 1 to the lower side by 1 bit, and further, the selector 12 has a function of initializing the second addition function unit 11 every time one y [n] is obtained. The addition function unit 11 adds the partial sums in ascending order of the exponent part pm to obtain y [n] in the equation [2]. Specifically, the bit of the partial sum of the exponent part pm = -Q is shifted to the lower side by 1 bit, added to the partial sum of the exponent part pm = -Q + 1, and the bit of the partial sum is further shifted to the lower side by 1 Bit-shifting is performed, and the partial sums are sequentially added such that the partial sums of the exponent part pm = −Q + 2 are added to obtain the total sum.

On the other hand, y [n] of the obtained [Formula 2] is obtained.
Is provided to the output processing unit 14. The output processing unit 14 multiplies the added sum, that is, one y [n] according to the formula [2] by a gain correction constant by the gain correction function unit and expresses a value forming the tap coefficient in a floating point. The resulting filter gain is corrected, and the rounding function unit converts the gain-corrected value into a required word length. Therefore, the output processing unit 14 provides the output unit 3 with the output data in the fixed-point representation.

The embodiment has been described in detail above.
The present invention is not limited to such an embodiment.
For example, although the embodiment has been shown to be applied to the FIR digital filter, it can be applied to the digital autocorrelator as well, and is generally applicable to various LTI systems. In addition, the detailed configuration can be arbitrarily changed without departing from the scope of the present invention.

[0043]

As described above, in the data processing method of the LTI system according to the present invention, each system constant is expressed as a floating point by limiting the range of the size of the exponent part, and the absolute value is equal to or larger than a certain size. The system constant is converted into multiple system constants, and the mantissa part of each system constant and each input data are multiplied by a fixed point, and the multiplication result executed for the system constant having the same exponent part is fixed. The partial sum is calculated by adding decimal points, and the partial sum calculated for each different exponent part is added by the fixed decimal point to calculate the total sum for the output data. It is remarkable that the characteristics (filter characteristics, etc.) can be improved, and in addition, the circuit configuration can be reduced and the data processing can be speeded up. Achieve the results.

[Brief description of drawings]

FIG. 1 is an FI which is an example of an LTI system according to the present invention.
Block circuit diagram of R digital filter,

FIG. 2 is a block circuit diagram of a FIR digital filter which is an example of an LTI system according to a conventional technique,

[Explanation of symbols]

 1 FIR digital filter

Claims (3)

[Claims] 1. A data processing method of an LTI system for calculating input data expressed in fixed point and a system constant to obtain output data expressed in fixed point,
Each system constant is expressed as a floating-point number with a limited exponent size range, and the system constant whose absolute value is greater than a certain size is converted into multiple system constants, and the mantissa of each system constant is also converted. Section and each input data are multiplied by a fixed point, and the multiplication results executed for system constants having the same exponent part are added by the fixed point to obtain a partial sum, and partial sums obtained for different exponent parts are also calculated. A data processing method for an LTI system, characterized by adding by fixed point to obtain a sum for output data. 2. A data processing method for an LTI system according to claim 1, wherein partial sums corresponding to system constants having a small exponent are sequentially added to obtain a total sum for output data. 3. The system constant is a tap coefficient of an FIR digital filter, according to claim 1 or 2.
A data processing method of the described LTI system.