EP0366155A2

EP0366155A2 - Logarithmic function arithmetic unit including means for separately processing pseudo division and multiplication

Info

Publication number: EP0366155A2
Application number: EP89120128A
Authority: EP
Inventors: Misayo C/O Nec Corporation Nakayama
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1988-10-28
Filing date: 1989-10-30
Publication date: 1990-05-02
Anticipated expiration: 2009-10-30
Also published as: JP2822399B2; EP0366155B1; DE68926563D1; EP0366155A3; DE68926563T2; US5041999A; JPH02118725A

Abstract

In a log_e(1 + x/y) arithmetic unit by use of the STL algorithm, in order to reduce the arithmetic time, a pseudo division is at first effected by use of w = (2X_k - Y_k) for k, initial values being mantissas X and Y of given x 2^-i·X and y = 2^-j·Y to produce X_m and Y_m, and thereafter, using X_m and Y_m as initial values a pseudo multiplication is effected by use of X_k+1 = (X_k + Γ_k) or X_k+1 = X_k/2 for k to obtain a mantissa of log_e(1 + x/y). The unit comprises coefficient generator for producing k and Γ_k, and first and second adder/subtractors accompanying with first and second registers for executing the pseudo division and the pseudo multipliction according to k and Γ_k from the coefficient generator.

Description

Background of the Invention:

The present invention relates to a scientific computing machine and, in particular, to a logarithmic function arithmetic unit for use in the machine.
As a known logarithmic function arithmetic method, so called STL (Sequenctial Table Lookup) method is known to be fittable for a computing machine of a microprogram control type, and is efficient, espetially, for a computing machine having no high speed multiplier.
A known logarithmic function arithmetic unit using the STL method comprises a single barrel shifter and a single adder/subtractor and effects loop processes of the STL method under the microprogram control.
However, the known arithmetic unit suffers from the following problems.
When it is provided that b (b is an integer) clocks are required for processing one loop process of the STL, (n x b) clocks (n being an integer) are required for processing n loop processes of the STL to compute a logarithmic function. This means that it takes a long time for computing a logrithmic function.
Further, the arithmetic result is not so good in precision, for example, a significant digits being reduced.

Summary of the Invention:

Therefore, it is an object of the present invention to provide a logarithmic function arithmetic unit which has hardware for effecting the STL method to thereby considerably reduce the computing time in comparison with use of the microprogram control.
It is another object of the present invention to provide a logarithmic function arithmetic unit which can produce a computed result with precision and with an increased significant digits.
According to the present invention, a logarithmic function arithmetic unit is obtained which comprises coefficient producing means for producing 2^k log_e(1+2^-k) and log_e(1+2^-k) for k=(m-1) to k=0; first and second register means; barrel shifter means for rightwardly shifting a value stored in the second register means by k digits; first adder/subtractor means for adding or subtracting a content of the barrel shifter, a content in the coefficient producing means, or zero to a content in the first register means to produce a first result, the fist result being stored in the first register means; second adder/subtractor means for the content in the first register means or zero to the content of the second register means to produce a second result, the second result being stored in the second register means; first-in last-out stack means responsive to a sign indication bit in the second register means for controlling the arithmetic in the first and second adder/subtractor means; and deviding means for dividing the content in the first register means by the content in the second register means.

Brief Description of the Drawings:

Fig. 1 is a block diagram view of a kown logarithmic function arithmetic unit using the microprogram control;
Fig. 2 is a flow chart for illustrating the arithmetic processes in the known unit of Fig. 1; and
Fig. 3 is a block circuit diagram view of a logarithimic function arithmetic unit according to an embodiment of the present invention.

Description of Preferred Embodiments:

Prior to description of preferred embodiment of the present invention, description is made as to the STL method and a known logarithmic function arithmetic unit using the microprogram control in order to help better understanding of the prsent invention.
The STL method will be described below for computing a logarithmic function log_e(1 + x) with a precision of n digits in the binary system.
A given value x is represented by the following equation (1) by use of a sequence of numbers {a_k}, as is known in the art:
a_k = {+1, 0} (2).
Therefore,
r_k = log_e(1 + 2^-k) (4).
In those equations (1) through (4), it is defined as a pseudo division to obtain {a_k} from x and it is defined as a pseudo multiplication to obtain log_e(1 + x) from {a_k}.

Algorithm of the STL method

Now, the algorithm of the STL method will be described below.

Process I. x₀ = x (1/2 ≦ x < 1), y₀ = 1, and z₀= 0 are given as initial values.
Process II. For k = 0, 1, 2, ..., (n - 1), the following process III are repeated.
Process III. w = x_k - y_k (5),
when w ≧ 0, the following equations (6) through (9) are computed:
a_k = +1 (6)
x_k+1 = w (7)
y_k+1 = y_k + 2^-k x y_k (8)
z_k+1 = z_k + r_k (9);
when w < 0, the following equations (10) through (13) are also computed:
a_k = 0 (10)
x_k+1 = x_k (11)
y_k+1 = y_k (12)
z_k+1 = z_k (13).
Process III is called as an STL loop. The STL loop is repeated n times.
Process IV. log_e(1 + x₀/y₀) = log_e(1 + x₀) = Zn is obtained.

Referrring to Fig. 1, a known logarithmic function arithmetic unit shown therein uses the STL algorithm as described above. The arithmetic unit comprises w, x, y, and z registers 11, 12, 13 and 14 for holding w, x_k, y_k and z_k, respectively, an adder/subtracter 15 for effecting addition/subtraction of two inputs A and B, a read-only memory (ROM) 16 for generating r_k, a barrel shifter 17 for shifting an input value by desired digits rightwardly, k counter 18 for providing k to read-only memory 16 and a digit number to be shifted at the barrel shifter 17, and a loop number control counter or n counter 19 for controlling the STL loop number. Those registers 11-14, adder/subtracter 15, read-only memory 16, barrel shifter 17, and counters 18 and 19 are connected through a data bus 20. The unit comprises a micro controller 10 for controlling those blocks 11-19.
Now, operation of the arithmetic unit will be described below with reference to Fig. 2.

Operation 1. According to Process I, initial values x₀, y₀ and z₀ are set in the x, y and z counters 12, 13 and 14, respectively, at steps 21, 22 and 23 as shown in Fig. 2. Values n and 0 are set in the loop number control counter 19 and k counter 18 at steps 24 and 25 in Fig. 2.
Operation 2. According to Process II, the following operation 3 is repeated until content of the loop number cotrol counter 19 becomes 1.
Operation 3. The arithmetic unit executes the STL loop of Process III as follows.

Contents x_k and y_k in x and y counters 12 and 13 are transferred to the adder/subtracter 15 as inputs A and B, respectively, through the data bus 20 under control of the micro controller 10. The adder/subtracter 15 makes (x_k - y_k) which is supplied to the w register 11. The w register 11 holds (x_k - y_k) as w. Thus, Equation (5) is given at a step 26 as shown in Fig. 2.
When w ≧ 0 at a step 27 in Fig. 3, that is, a sign digit in the w register 11 indicates positive, the following operation is effected under control of the micro controller 10. The content w in the w counter is transferred to the x counter 12 at a step 28. Thus, Equation (7) is obtained. Then, y_k is transferred from y register 13 to the adder/subtracter 15 as the A input and to the barrel shifter 17. The y_k is shifted by the shifted digit number supplied from the k counter 18 to produce y_k·2^-k which is supplied to the adder/subtracter 15 as the B input. Then, the adder/subtracter 15 makes (A + B) = (y_k + y_k2^-k) which is transferred to the y register 13 at a step 29 shown in Fig. 2. Thus, Equation (8) is obtained. Then, z_k in the z register 14 is transferred to the adder/subtracter 15 as the A input, while a constant indicated by the k counter 18, that is, r_k is read from the read-only memory 16 and is supplied to the adder/subtracter 15 as the B input. The adder/subtracter 15 makes (A + B) = (Z_k + r_k) which is transferred to the z register at a stpe 30. Thus, Equation (9) is obtained.
When w < 0, that is, a sign digit in the register 11 indicates negative at step 27, the arithmetic unit does nothing as shown at steps 31, 32 and 33.
After a loop of steps 26 to 30 or 33 is completed, the content of k counter 18 is increased by one (1) at step 34 and the content of loop number control counter 19 is reduced by one (1) at step 35 as shown in Fig. 2. The loop is repeated until the content of loop number control counter 19 becomes 0.
Operation 4. When the content of loop number control counter 19 is 0 at the step 36, the operation 3 is completed. Then, the content of the 2 register 14 provides an arithmetic result of log_e(1 + x₀) as shown at stpe 37 in Fig. 2.
In the known arithmetic unit, the above-described operation is executed under the microprogram control. Providing that b clocks are required for processing the STL loop in operation 3 one time, (n x b) clocks are required for obtaining the arithmetic result. Therefore, it takes a long time to compute the logarithmic function.
Further, since r_k of Equation (4) is reduced by increase of k, significant digits are reduced so that rouning errors are accumulated at the least significant bit. Moreove, since Equations of (7), (8), (9), (11), (12) and (13) are computed with use of fixed-point numbers, conversion must be made between the fixed-point system and the floating-point system when x and log_e(1 + x) are represented by use of the floating-point system. In conversion of x of a small number from the floating-point system to the fixed-point system, the significant digits are considerably reduced. Therefore, the known unit is low in the precision.
In order to resolve those problems of the known arithmetic unit using the STL method under the microprogram control, the present invention attempts to use a modified STL method so as to seperately perform the pseudo division and the pseudo multiplication by use of hardweare such as a single barrel shifter, two adder/subtracters, a stack of a first-in last-out type and a divider without use of the microgram control.

Modified STL method

Although the pseudo division and the pseudo multiplication are executed in simultaneously or corelatively in the conventional STL method, the former is at first executed and then the latter is done in the modified STL method.
In the conventional STL method, ε (pseudo reminder) in Equation (1) is ignored and the pseudo multiplication is executed using y₀ = 1 as the initial value. Therefore, n-times of the STL loop are required for achieving a n-digit precision in the binary system.
In Equation (1), ε < 2ⁿ. Therefore, in order to achieve 2n-digit precision in the binary system according to the modified STL method, the pseudo multiplication is executed by use of approximation log_e(1 + ε)≒ε which is accepted according to the Taylor expansion. Accordingly, the total step number of the pseudo division and the pseudo multiplication is about n which is equal to the stpe number in the conventional STL method.
In the modified STL method, y_k is shifted to a lower digit at one step of the pseudo division in order to improve the precision. On the contrary, x_k is shifted to a higher digit in the pseudo multiplication.
Further, using Xm = Xm/Ym as the initial value where Xm is a remainder of a pseudo division and

Ym =
(1 + 2^-k)^ak, the pseudo multiplication given by the following equation (14) is repeated from k = m to k = (i + 1):
X_k-1 = X_k-1 + a_k (14).
Since x and y are floating-point numbers and since log_e(1 + x/y) ≒ x/y for x/y«1, the pseudo division is stated from an intermediate step while the pseudo multiplication, is stopped at an intermediate step. As a result, it is prevented that the significant digits are reduced due to digit matching as well as performance is improved.

Algorithm of the modified STL

Now, description is made as to the algorithm of the modified STL for computing log_e(1 + x/y) with n-(= 2m) digit precision.

Process I. x and y are inputted (0 ≦ x< y < +∞).
Process II. X, Y, i and j are determined for satisfying x = 2^-i X (1 ≦ X < 2, i being an integer) and y = 2^-j·Y (1 ≦ Y < 2, j being an integer), X and Y are mantissa portions of x and y, respectively, while i and j are exponential portions of x and y, respectively. Values X_i = x, y_j = Y and i = (j - i) are selected as initial values.
Process III. For k = i, (i + 1), (i + 2), ..., (m - 1), the following process IV is repeated, that is, pseudo division is executed.
Process IV. The following equation (15) is given:
W = 2X_k - Y_k (15).
When W ≧ 0, the following equations (16) to (18) are obtained:
a_k = +1 (16)
Y_k+1 = Y_k + 2^-k·Y_k (17)
2·X_K+1 = 2·W (18).
When W < 0, the following equations (19) to (21) are obtained:
a_k = 0 (19)
Y_k+1 = Y_k (20)
2·X_k+1 = 2·2·X_k (21).
Process V. Y_m given by the following equation (22) is selected as an initial level for the pseudo multiplication:
X_m = X_m/Y_m (22).
Process VI. For k= m, (m - 1), (m - 2), ..., (i + 1), the following process VII is repeated, that is, the pseudo multiplication is executed.
Process VII. For a_k = +1,
X_k+1 = (X_k + Γ_k)/2 (23)
Γ_k = 2^k·r_k = 2^k·log_e(1 + 2^-k) (24)
are computed, while for a_k = 0,
X_k+1 = X_k/2 (25)
is computed.
Process VIII. log_e(1 + x/y) = X_i is obtained.

Arithmetic Unit using the Algorithm of Modified STL method

Now, a logarithmic function arithmetic unit using the above algorithm of the modified STL method will be described with reference to Fig. 3.
Referring to Fig. 3, the arithmetic unit shown therein comprises a first and a second register 41 and 42 for holding two variables 2X_k and Y_k, a read-only memory 43 for generating a constant Γ_k in Equation (23), a barrel shifter 44 for shifting a value of a variable supplied from the second register 42, an exponential circuit 45 for executing Process II and for controlling a digit number to be shifted at the barrel shifter 44 and an address of the read-only memory 43, a first adder/subtracter 46 for effecting addition/subtraction of two inputs A and B so as to execute Equations (17) and (18), a second adder/subtracter 47 for effecting addition/subtraction of two inputs C and D so as to execute Equation (15), a fist shifter 48 for shifting an output value from the first adder/subtracter 46 to produce a half value, a second shifter 49 for shifting an output value from the second adder/subtractor 47 to produce a twice value, a stack of a first-in last-out type 50 for holding an inversion of a sign indication bit of a value in the second register 42 so as to control the addition, subtraction or transferring in the first and the second adder/subtractors 46 and 47, and a divider 51 for executing Process V, which are connected to one another through a data bus 52. An output of the first register 41 is connected to the first and the second adder/ subtractors 46 and 47 as inputs A and C, respectively, through another data bus 53. The unit further comprises a controller 54 for controlling the blocks 41-51.

Operation of the Arithmetic Unit of Fig. 3

Now, description will be made as to the operation of the arithmetic unit of Fig. 3 below, according to the Algorithm of the modified STL method.

Operation 1. According to Process I, binary floating-point numbers x and y are supplied onto the bus 52. Where 0 ≦ x < y < +∞.
Operation 2. The exponential circuit 45 receives the numbers x and y and execute Process II to obtain the mantissa portions X and Y and the index portions i and j and j = (i - j). Y and 2·X are transferred under control of the controller 54 to the first and the second registers 41 and 42, respectively, through the bus 52.
Operation 3. According to Process III, the following operation 4 is repeated with k being incremented by 1 from k = i to k =(m - 1), that is, the pseudo division is executed. The incrementation is performed by the exponential circuit 45.
Operation 4. At first, Y_k is supplied from the first register 41 to the second adder/subtractor 47 as an imput C through the data bus 52, while 2X_k is supplied from the second register 42 to the second adder/subtractor 47 as another input D. The adder/subtractor 47 subtracts the input C from the input D to produce W = 2X_k - Y_k which is shifted by the shifter 49 and written as 2X_k+1 - 2W into the second register 42. Thus, Equation (15) is completed.
Then, a sign indication digit of the value in the second register 42 is pushed out and supplied to the stack 50. Y_k is supplied from the first register 41 to the first adder/subtractor 46 as input A through the data bus 53 and is also supplied to the barrel shifter 44 through the data bus 52. The barrel shifter 44 shifts Y_k by the digit number indicated by the exponential circuit 45 to produce 2^-k·Y_k which is supplied to the first adder/multiplier 46 as input B. When the sign indication bit indicates positive in the second register 42, that is, a_k = +1, the first adder/subtractor 46 makes (A + B)= (Y_k + 2^-k·Y_k) which is supplied to the first register 41. As a result, Equation (17) is obtained.
On the other hand, when the sign indication bit is negative, the second adder/subtractor 47 makes (0 + D) = 2X_k which is shifted at the second shifter 49 to produce a twice value of 2·2·Y_k. The value 2·2·Y_k is held in the second register 42. Thus, Equation (21) is obtained.
Operation 5. According to Process V, the divider 51 divides X_m held in the second register 42 by Y_m held in the first register 41 to form X_m = X_m/Y_m which is supplied to the first register 41 as an initial value for the pseudo multiplication.
Operation 6. According to Process VI, the following operation 7 is repeated with k being decremented by 1 from k = m to k =(i + 1), that is, the pseudo multiplication is executed. The decrementation is also performed by the exponential circuit 45.
Operation 7. X_k is supplied from the first register 41 to the first adder/subtractor 46 as input A through the data bus 53. Simultaneously, Γ_k is supplied from the read-only memory 43 to the first adder/subtractor 46 as input B. At that time, when a positive number is popped from the stack 50, that is a_k = +1, the first adder/subtractor 46 makes (A + B) = (X_k + Γ_k) which is shifted at the first shifter 48 to produce (X_k + Γ_k)/2. Then, (X_k + Γ_k)/2 is held as X_k+1 in the first register 41. Thus, Equation (23) is obtained. On the other hand, a negative number is popped from the stack 50, that is a_k = 0, the first adder/subtractor 46 makes (A+0) to produce X_k. The X_k is shifted by the first shifter 48 to produce X_k/2 which is held as X_k+1 in the first register 41. Thus, Equation (25) is obtained.
Operation 8. As a result, the content X in the first register 41 provides a mantissa portion of log_e(1 + x/y).

Each of Operations 4 and 7 is executed by one clock. Therefore, the entire processing time is 2(m - i) clocks which is equal to or smaller than n clocks.
The operation has been described in connection with use of floating-point numbers but the arithmetic unit of the present invention can use fixed-point numbers by fixing the index portion i to be 0.

Claims

1. A logarithmic function arithmetic unit for computing a function of log_e(1 + x/y), which comprises:
means responsive to input numbers x and y (0 ≦ x y < +∞) for computing x = 2^-i·X (1 ≦ X < 2, i being an integer) and y = 2^-j·Y (1 ≦ Y < 2, j being an integer), X and Y being mantissa portions of x and y, respectively, while i and j being exponential portions of x and y, respectively;
means for producing coefficient of k = i, (i + 1), (i + 2), ..., (m - 1) one after another:
means responsive to X, Y and k for computing the following equations (1) to (7):
W = 2X_k - Y_k (1),
for W ≧ 0,
a_k = +1 (2)
Y_k+1 = Y_k + 2^-k·Y_k (3)
2·X_k+1 = 2·W (4),
for W < 0,
a_k = 0 (5)
Y_k+1 = Y_k (6)
2·X_k+1 = 2·2·X_k (7)
to produce X_m and Y_m;
means responsive to X_m and Y_m for dividing X_m by Y_m to produce X_m = X_m/Y_m;
means responsive to k from the coefficient producing means for producing Γ_k = 2^k log_e(1 + 2^-k); and
means for responsive to X_m, Y_m, k= m, (m - 1), (m - 2), ..., (i + 1) and Γ_k for computing the following equations (8) and (9):
for a_k = +1,
X_k+1 = (X_k + Γ_k)/2 (8)
for a_k = 0,
X_k+1 = X_k/2 (9),
to produce log_e(1 + x/y) = X_i.

2. A logarithmic function arithmetic unit as claimed in Claim 1, wherein i is maintained 0 so that the arithmetic is executed by use of fixed-point system.

3. A logarithmic function arithmetic unit for computing a function of log_e(1 + x/y), which comprises:
coefficient producing means for producing 2^k log_e(1 + 2^-k) and log_e(1 + 2^-k) for k=(m-1) to k=0;
first and second register means;
barrel shifter means for rightwardly shifting a value stored in said second register means by k digits;
first adder/subtractor means for adding or subtracting a content of said barrel shifter, a content in said coefficient producing means, or zero to a content in said first register means to produce a first result, said fist result being stored in said first register means;
second adder/subtractor means for the content in the first register means or zero to the content of said second register means to produce a second result, said second result being stored in said second register means;
first-in last-out stack means responsive to a sign indication bit in said second register means for controlling the arithmetic in said first and second adder/subtractor means; and
dividing means for dividing the content in said first register means by the content in said second register means.