JP3538512B2 - Data converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data conversion device.

[0002]

2. Description of the Related Art In recent years, DSP (Dig) has been developed in the field of sound reproduction.
Devices for performing various audio signal processes using an ital Signal Processor have been increasing. For example, in surround reproduction of a movie sound or the like, a difference between logarithmic values of signals is used as a numerical value indicating the direction of sound. In addition to logarithmic conversion, when an input signal is processed to obtain an output, complicated processing takes a long time to perform an arithmetic operation. Therefore, a lookup table method using a memory in which processing results are stored in advance is used. Often used. Further, as one of the methods for obtaining the logarithm, there is a method for obtaining the logarithm by an operation such as Taylor expansion. In addition, there is a method in which a logarithm calculation result table is configured in advance to reduce the circuit scale of the calculation circuit and the calculation time, and the logarithmic value is obtained by referring to the table.

A conventional logarithmic conversion method using a look-up table will be described with reference to FIG. In FIG. 3, 10
Is a bus, 11, 12, 16, and 17 are buffer memories, 13 and 18 are multipliers, 14 and 19 are arithmetic logic units (ALUs), 15 and 20 are accumulators,
Reference numeral 4 denotes a signal data memory for storing input data to be converted to a logarithmic value.

A high-order coefficient memory 21 stores non-zero-order high-order coefficients for data values within a specific numerical value range. A zero-order coefficient memory for storing coefficient values corrected in accordance with digit shift of data; a digit shift circuit for digit shifting input data so as to fall within a range of a specific numerical value;
Reference numeral 24 denotes a signal data memory for storing signal data, and reference numeral 25 denotes an address designating circuit for generating an address for reading a zero-order coefficient corresponding to the number of digits moved by the digit moving circuit 23.

The addressing circuit 24 is a digit moving circuit 23
Sends a signal designating the address of the 0th order coefficient memory 22 in which the 0th order coefficient corresponding to the number of digits moved by the digit is stored. Next, all operations are performed by a sequence controller (not shown).

[0006] Zero order coefficient memory 22 and high order coefficient memory 2
The coefficient data of 1 is stored before the operation of the logarithmic conversion process is started, and when the arithmetic operation is started, first, in a first step, the signal data x is read from the signal data memory 24 and the buffer memories 12 and 16 are read out. And 17. On the other hand, the buffer memory 11 has a high-order coefficient memory 21.
Coefficient data c ₁ is supplied read from. Therefore, the multiplier 13 multiplies the value of the signal data x and the coefficient data c _1. The value c ₁ x of the result of the multiplication by the multiplier 13 is A in the second step one step after the first step.
It is supplied to and stored in the accumulator 15 via the LU 14. Further, the multiplier 18 multiplies the signal data x to perform a square calculation. The value x ² of the result of the multiplication by the multiplier 18 is supplied to the buffer memories 12 and 17 in the second step.

In the second step, the coefficient data c ₂ is read from the higher-order coefficient memory 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies x ² by the coefficient data c ₂ . The value c ₂ × ² of the result of the multiplication by the multiplier 13 is supplied to the other first input of the ALU 14. In synchronization with this supply, the data value c ₁ x held in the accumulator 15 is supplied to one input of the ALU 14. Therefore, in the third step, ALU 14
The accumulation of ₁ x + c ₂ x ² is performed, and the value of the accumulation result is held in the accumulator 15. The multiplier 18 multiplies the signal data x stored in the buffer memory 16 by the signal data x ² stored in the buffer memory 17. The value x ³ of the multiplication result by the multiplier 18 is supplied to the buffer memory 12 and 17 in the third step.

In a third step, the buffer memory 11
The coefficient data c ₃ is read from the higher-order coefficient memory 21 and supplied. Therefore, the multiplier 13 supplies the x ³ and the coefficient data c ₃ x ³ to the other first input of the ALU 14. The accumulated data value c ₁ x + c ₂ x ² held in the accumulator 15 is supplied to one input of the ALU 14 in synchronization with this supply. Therefore, in the fourth step, the ALU 14 accumulates c ₁ x + c ₂ x ² + c ₃ x ³ , and the value of this accumulation result is held in the accumulator 15. Further, the multiplier 18 multiplies the signal data x ³ held in the buffer memory 16. The value x ⁴ of the result of the multiplication by the multiplier 18 is stored in the buffer memory 1 in the fourth step.
2 and 17.

By repeating such an operation n times, the sum total from the first order to the nth order is calculated. In a step after the sum is held in the accumulator 15, the coefficient data c ₀ is read from the zero-order coefficient memory 22 and supplied to the other second input of the ALU. In synchronization with this supply, the accumulated data values from the primary to the n-th stored in the accumulator 15 are supplied to one input of the ALU 14. Therefore, the ALU 14 accumulates the accumulated data values from the 0th order and the 1st to the nth order, and the value of this accumulation result,
That is, the logarithmically converted value is held in the accumulator 15.

[0010]

As described above, in the conventional data conversion by the look-up table method, since the address is calculated by addition, processing time by addition is required, and other processing is performed by software. There was a problem that the usable time was reduced and the program was restricted. Accordingly, an object of the present invention is to provide a data conversion device having a small circuit size and a short processing time in view of the above-described problems.

[0011]

According to a first aspect of the present invention, there is provided a data conversion apparatus, comprising: a register for storing input bit data; and a first conversion data corresponding to the input bit data. And a predetermined lower bit of a first reference address of the first conversion table comprises at least a part of the input bit data, and an upper bit larger than a predetermined lower bit of the first reference address is It is characterized by comprising a first base address. According to a ninth aspect of the present invention, there is provided a data conversion method comprising:
A data conversion method for converting input bit data, comprising: an input step of inputting input bit data; a step of setting a part of the input bit data to a predetermined lower bit of a first reference address; The method includes the steps of: setting a first predetermined base address to an upper bit larger than a predetermined lower bit; and referring to a first conversion table from a first reference address to obtain first conversion data.

[0012]

According to the present invention, as described above, in the data conversion by the look-up table method, when the address of the look-up table is obtained, the address can be obtained by simply combining the upper address and the lower address. It does not require a software program for the calculation, and does not require a new circuit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is intended to perform high-speed and high-accuracy logarithmic conversion, which is usually realized by software in a digital arithmetic unit such as a DSP or a microcomputer, by partially assisting with simple hardware. It is.

In general, a logarithmic conversion value y of input data x is expressed by the following equation. y = a + b · log ₂ x (1) where a and b are constants, x is input data, and y is output data to be obtained. Note that x is 2− ^{(N + 1)} ≦
It is assumed that the range is limited to x <1.0. Further, the input data x is represented by x = t · 2 ⁻ⁿ (2), where n = 0, 1, 2,... N, 0.5 ≦ t <
When 1.0, equation (1) y = a - b · n + b · log 2 t (3) = p (t) + q (n) p (t) = b · log 2 t (4) q (n) = a−b · n (5)

According to the present invention, when x is input, a table data memory address in which p (t) and q (n) are stored is output. FIG. 1 shows a configuration of logarithmic conversion according to the present invention. In FIG.
It is composed of a fixed-point binary number with a bit sign, the most significant bit indicates a sign, and if the next bit is “1”, 1
If the decimal number is 0.5 and the next bit is “1”,
Decimal number 0.25, 0.125, 0.0625.
. The address space of the table data memory 113 is configured by m bits. The table data memory 113 is divided into a first table and a second table, and the first table stores two sections from 0.5 to 1.0.
^(mi) p (t) for input t, divided into equal parts, and
The second table stores q (n) for n = 0, 1,..., 2 ^(mj) .

The upper i bits of the table data memory address of p (t) are constituted by a predetermined p (t) base address α. Then, the p (t) base address α is stored in the logarithmic table upper address register 105. The lower mi bits of the table data memory address of p (0) are set to 0. The lower mi bits of the table data memory address of p (1) are 001b
(1 in decimal notation), p (2) is 010b (2 in decimal notation), p (3) is 011b (3 in decimal notation),. Are set to t in decimal notation. Similarly, for q (n), the upper j bits of the table data memory address of q (n) are given by q (n)
It consists of a base address β. Then, the q (n) base address β is stored in the inverse normalization table upper address register 106. Also, the lower mj bits of the table data memory address of q (0) are set to 0. Lower m of table data memory address of q (1)
-J bits are 001b (1 in decimal notation), and q
(2) is 010b (2 in decimal notation), q (3) is 0
11b (3 in decimal notation),..., In that order, the lower mj bits of the table data memory address of q (n) are set to n in decimal notation.

The input data x for performing logarithmic conversion is stored in the input register 104. Next, the contents of the input register 104 are input to the normalizer 109. The normalizer 109 calculates a left shift amount for normalizing the input data x to a value within a predetermined range. For example, the normalization range of the normalizer 109 is 0.5 or more and less than 1.0. Specifically, it detects whether the bit next to the most significant bit is 1 and
The left shift amount is determined so that the next bit of the most significant bit becomes 1.

For example, if the input data x is 0.000101
00b (b indicates a binary binary number), this is the first bit in the fifth bit viewed from the most significant bit.
Appears. Accordingly, since the data is normalized by shifting left by 3 bits, the output of the normalizer 109 is 3. The normalized shift amount is n for the input data x. Then, the arithmetic left shifter 107 shifts the input data x left by the normalized shift amount obtained by the normalizer 109 to normalize the input data x. This value corresponds to t for x.
In the above example, the input data x is 0.00010100
Since b is shifted to the left by 3 bits, the input bit data t after normalization is 0.10100b.

Next, mi bits are extracted from the third bit from the most significant bit of t, and are taken as lower mi bits of the logarithmic conversion table address register 111.
The upper i bits of the logarithmic conversion table address register 111 are the value of the logarithmic table upper address register 105. For example, the most significant bit of the above-mentioned t = 0.10100b is a sign bit, and the next second bit (a normalized digit, for example, a lower bit next to the most significant bit in this embodiment is Since the normalized digit is normalized, it is always "1", and is used as a part of the table address from the third lowermost bit, which is the next lower bit of the normalized digit. If the mi bits are three bits, the bit of 010b is extracted. If the p (t) base address α is 100b, the logarithmic conversion table address is 100010b. Then, the value of p (t) is obtained by referring to the table data memory 113 using the logarithmic conversion table address.

Similarly, the value of the normalized shift amount is set to the lower mj bits of the inverse normalized table address register 112. Top j of inverse normalization table address register 112
The bit is the inverse normalization table upper address register 106
Value. For example, the aforementioned normalized shift amount is 3 (01
1b), if the mj bits are 3 bits, the lower mj bits of the denormalized table address are 011b. If the q (n) base address β is 111b, the denormalized table address becomes 111011b. Then, the value of q (n) is obtained by referring to the table data memory using the denormalized table address.

Logarithmic conversion table address register 111
And the address indicated by the denormalized table address register 112.
The data p (t) and q (n) extracted from 13 are added by an arithmetic unit (not shown) to obtain a logarithmically converted value of the input data x. In this embodiment, as the lower mj bits of the logarithmic conversion table address, three bits are taken out from the next lower bit of the normalized digit of t and used. However, if it is a continuous bit string including the next lower bit of the normalized digit, it may be configured to include the sign bit and the normalized digit.

With this configuration, when combining the predetermined bit of t, which is the input data after normalization, and the upper address value of the logarithmic table to obtain the address of the logarithmic conversion table, the two addresses are simply obtained without requiring arithmetic addition. An address can be obtained only by combining with the logarithmic conversion table address register 111. For this reason, an increase in the scale of hardware can be suppressed. The same applies to the calculation of the denormalized address. In addition, since the logarithmic conversion can be performed without performing a higher-order power series operation, the execution speed is increased.

Next, the inverse logarithmic transformation will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the antilogarithmic conversion. The input data x is x (0.0 ≦ x <1.0), N = 2 ^l ,
The antilogarithmic transformation is represented by y = 2− ^{N (1-x)} (6) where 1 is an integer. Also, it is expressed as x = n / N + t (7). At this time, n = 0, 1,..., N-1, 0 ≦ t
<1 / N. Thus, y is expressed as shown below. y = ( ^2Nt / 2) ・ 2 ^{(1- (Nn))} = P (t) ・^{2Q (n)} (8) P (t) = ^2Nt / 2 (9) Q (n) = 1− (N−n) (10) Here, since 0 ≦ t <1 / N, 0.5 ≦ P
(T) <1.0. Further, since 0 ≦ n ≦ N−1, −N + 1 ≦ Q (n) ≦ 0, and 2 ^{Q (n)} is expressed by an arithmetic right shift. The present invention is to input x and output a table address and Q (n) for obtaining P (t).

In FIG. 2, the data of the numerical processing is composed of a fixed-point with a k-bit sign, and the address space of the table data is composed of m bits. Table data memory 2
05 stores P (t) for the input t obtained by dividing the section from 0.5 to 1.0 into 2 ^(mi) equal parts. P
The upper mi bits of the table data memory address of (t) are constituted by a predetermined P (t) base address γ. Then, the P (t) base address γ is stored in the antilog table upper address register 202. Also,
The lower i bits of the table data memory address of P (0) are set to 0. Further, the lower i bits of the table data memory address of P (1) are set to 001b (1 in decimal notation). Similarly, P (2) is 010b (2 in decimal notation), P (3) is 011b (3 in decimal notation), and so on, in that order, the lower i of the table data memory address of P (t). The bit is set as t in decimal notation.

First, input data x is stored in an input register 201.
To be stored. Since the input data x is a positive integer, the most significant sign bit is always 0. The upper l bits are extracted from the bit next to the sign bit, which corresponds to n. By inverting all the bits, a right shift amount -Q (n) for inverse normalization is obtained. For example, assuming that input data x is 0.01101001011b and l = 4, four bits from the second bit which is the next bit of the sign bit of the input data x, that is, 0110b are all bits inverted by the all bit inverter 206 and 1001b
(9 in decimal notation). This value becomes -Q (n) and is stored in the denormalized shift amount storage register 203.

Assuming that the lower i bits of the table data memory address are 3, as described above, the most significant bit of the input data x is a sign bit, and 1 bit (for example, 4 bits) from the next bit is all bits. Inverter 206
, The next bit, that is, 3 bits from the 6th bit to the 8th bit as viewed from the most significant bit, and 100b are the lower 3 bits of the table data memory address.
Bit. Therefore, 100b is stored in the lower three bits of the antilog table address register 204. Then, the upper mi bits of the table data memory address of P (t) are constituted by a predetermined P (t) base address γ. Therefore, the mi-bit P (t) stored in the antilog table upper address register 202
The base address γ is output to the antilog table address register 204. Then, the antilogarithmic table address register 204 combines the P (t) base address γ with the i bit from the input register 201 to obtain the address of the table data memory 205. For example, m is 7
Then, the P (t) base address γ has 4 bits (m−i
Bit) and the value is 1001b, the address of the table data memory 205 is 1001100b. The value corresponding to this address is read from the table data memory 205. This value is P (t). This P (t) is stored in a denormalized shift amount storage register 203 by a shift means (not shown).
The antilogarithm conversion value y is obtained by arithmetically shifting right by (n). Thus, an antilogarithm conversion value y for the input data x is obtained.

With such a configuration, addition is not required when obtaining the inverse logarithmic conversion table address, and the necessary address can be obtained simply by combining the addresses similarly to the above-described logarithmic conversion. As a result, an increase in the scale of hardware can be suppressed.

[0028]

As described above, a table address for extracting data necessary for logarithmic conversion can be obtained with a simple configuration. By adding the data extracted from the address indicated by the log conversion table address register and the data extracted from the address indicated by the denormalization table address register, the log conversion value of the input data x is obtained. Addition is not required when the normalized shift amount and the logarithmic table upper address value are combined to obtain the logarithmic conversion table address. For this reason, an increase in the scale of hardware can be suppressed. The same applies to the calculation of the denormalized address. In addition, since the logarithmic conversion can be performed without performing a higher-order power series operation, the execution speed is increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of logarithmic conversion according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of antilogarithmic conversion according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional logarithmic conversion using a lookup table method.

[Description of Signs of Main Parts]

10 Bus 11, 12, 16, 17 Buffer memory 13, 18 Multiplier 14, 19 Arithmetic logic unit 15, 20 Accumulator 21 High-order coefficient memory 22 Zero-order coefficient memory 23 Digit shift circuit 24 Signal data memory 25 Address designating circuit 104 Input register 105 Logarithmic table upper address register 106 Inverted table upper address register 107 Arithmetic left shifter 109 Normalizer 110 Normalized shift amount 111 Logarithmic conversion table Address register 112 ··· Inverse normalized table address register 113 ··· Table data memory 201 ··· Input register 202 ... antilog table upper address register 203 .... denormalization shift amount storage register 204 ... inverse logarithmic conversion table address register 205 .... table data memory 206 .... total bit inverter

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-175826 (JP, A) JP-A-4-137117 (JP, A) JP-A-5-3344051 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 7/00

Claims (16)

(57) [Claims] 1. A register for storing input bit data, and a first conversion table storing first conversion data corresponding to the input bit data, wherein a predetermined lower order of a first reference address of the first conversion table is provided. A data conversion device, wherein a bit comprises at least a part of the input bit data, and an upper bit larger than the predetermined lower bit of the first reference address comprises a first base address. 2. The data conversion apparatus further includes a normalizing unit and a shifting unit, wherein the normalizing unit determines a shift amount necessary for normalizing the input bit data to a value within a predetermined range. Wherein the shift means shifts the input bit data based on the shift amount to obtain normalized data, wherein the predetermined lower-order bits of the first reference address comprise at least a part of the normalized data. The data conversion device according to claim 1, wherein 3. The data conversion device further includes a second conversion table, wherein the second conversion table stores second conversion data, and a predetermined second reference address of the second conversion table. 3. The data conversion device according to claim 2, wherein a lower bit comprises the shift amount, and an upper bit larger than the predetermined lower bit of the second reference address comprises a second base address. 4. The data conversion apparatus according to claim 3, wherein a value of the input bit data after data conversion is calculated by calculating the first conversion data and the second conversion data. 5. The data conversion device according to claim 4, wherein the value of the input bit data after data conversion is a logarithmic value of the input bit data. 6. The data converter according to claim 1, further comprising an inverting unit, wherein the inverting unit obtains an inverse normalized shift amount obtained by inverting a part of the input bit data.
The data conversion device according to the above. 7. The data conversion apparatus according to claim 6, wherein a value of the input bit data after data conversion is calculated by calculating the first conversion data and the denormalized shift amount. 8. The data conversion device according to claim 7, wherein a value of the input bit data after data conversion is an inverse logarithm of the input bit data. 9. A data conversion method for converting input bit data, comprising: inputting the input bit data; and setting a part of the input bit data to a predetermined lower bit of a first reference address. Setting a first predetermined base address to an upper bit larger than the predetermined lower bit of the first reference address; and obtaining a first conversion data by referring to a first conversion table from the first reference address. A data conversion method characterized by having. 10. A step of obtaining a shift amount necessary for normalizing the input bit data to a value within a predetermined range; and a step of obtaining the normalized data by shifting the input bit data based on the shift amount. 10. The method according to claim 9, further comprising: setting at least a part of the normalized data in the predetermined lower bits of the first reference address. Setting the shift amount to a predetermined lower bit of a second reference address; setting a second base address to an upper bit larger than the predetermined lower bit of the second reference address; 11. The data conversion method according to claim 10, further comprising a step of referring to a second conversion table from two reference addresses to obtain second conversion data. 12. The data according to claim 11, further comprising a step of calculating a value of the input bit data after data conversion by calculating the first converted data and the second converted data. Conversion method. 13. The data conversion method according to claim 12, wherein the step of calculating the value of the input bit data after the data conversion includes obtaining a logarithmic value of the input bit data. 14. The data conversion method according to claim 9, further comprising a step of inverting a part of the input bit data and storing it in a register as a denormalized shift amount. 15. The data conversion according to claim 14, further comprising: calculating a value of the input bit data after data conversion by shifting the first conversion data by the reverse shift amount. Method. 16. The data conversion method according to claim 15, wherein the step of calculating the value of the input bit data after the data conversion calculates an antilog value corresponding to the input bit data.