JPH074658Y2 - Logarithmic conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION << Industrial Application Field >> The present invention relates to improvement of a scaling function of a logarithmic conversion circuit.

<< Conventional Technology >> Since the dynamic range of the measured power spectrum is wide in an FFT (Fast Fourier Transform) analyzer,
Since it is difficult to display the measurement result on a linear scale, it is often converted to a logarithmic scale and displayed. Since such logarithmic conversion must be performed at high speed, RAM (Random
A so-called look-up table is used in which a logarithmically converted value is written in an m Access Memory) or a ROM (Read Only Memory), and data before conversion is input to the address. To realize scaling by the lookup table method (a) The contents of the lookup table are rewritten each time scaling is performed.

(B) Prepare and switch a plurality of tables in advance according to the type of scaling.

(C) Add a scaling circuit.

Etc. are considered.

<< Problems to be solved by the device >> However, in the above scaling means, (a)
Takes time, (b) increases the memory capacity, and (c) increases costs. Therefore, scaling cannot be easily realized by the method using the memory lookup table for logarithmic conversion.

The present invention has been made to solve such a problem, and an object thereof is to realize a logarithmic conversion circuit that executes scaling for display accompanying logarithmic conversion with a high-speed and simple configuration.

<< Means for Solving the Problem >> The present invention relates to a logarithmic conversion circuit for converting an input digital signal into its logarithmic value, which is characterized by a signal related to exponential data of the input digital signal and a conversion constant. A multiplier for multiplying by, an accumulator for computing a linear interpolation value corresponding to the mantissa data of the input digital signal, and an adder for adding the output of the multiplier and the output of the accumulator, The point is that scaling is possible by setting a constant.

Further, instead of performing linear interpolation, the logarithm of the mantissa data of the input digital signal is approximated by a quadratic equation.

<< Operation >> Since the logarithmic operation value output from the multiplier and the logarithm value of the mantissa can be added to obtain the final conversion value, and scaling can be performed by changing only the conversion constant input to the multiplier, Can achieve the purpose of.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of a logarithmic conversion circuit according to the present invention. 1 is a register for inputting and holding the exponent part of input data, 2 is a subtracter for subtracting the output of the register 1 from input word length constant data, 3 is this subtracter 2
The multiplier 4 which multiplies the output of the shift register with the input conversion constant data inputs the conversion constant, and the shift register 5 performs the shift operation to the LSB side bit by bit by the shift clock, and 5 outputs the output of the shift register 4. An adder having one input, 6 is a register which receives the output of the adder 5 and whose output is the other input of the adder 5, 11 is the adder 5
And a register 6, an adder 7 for adding the output of the multiplier 3 and the output of the register 6, a register 8 for holding the output of the adder 7, and an input data 9 The parallel / serial converter that inputs the mantissa part of and performs parallel / serial conversion by the shift clock, 10 is the output of the parallel / serial converter 9 and the shift
It is a gate that generates a clock to the register 6 by a clock.

The operation of the apparatus configured as described above will be described together with the basic principle. When the input data is X and the output data is Y, the logarithmic conversion formula is represented by Y = 10 · LOG (X). The data representation of the input data X is, for example, a 16-bit floating point format in order to secure the dynamic range of Y in the calculation of the power spectrum. FIG. 2B shows an example of input data X expressed in a floating point format having an exponent part of 8 bits and a mantissa part of 8 bits. FIG. 2 (a) shows data expressed in a fixed-point format corresponding to (b), and X has a length of 32 bits corresponding to a Y dynamic range of 96 dB. If the data in (a) is input as it is, the circuit scale becomes large, so the floating point format is used as in (b). In FIG. 2, the exponent part of (b) shows in binary the value obtained by counting the position of the highest "1" of (a) from the 32nd bit. The mantissa part of (b) indicates 8-bit data from the position of the most significant digit “1” of (a) to the lower part.

Here, the scaling means how many dots the Y value (dB) is displayed on the output screen. For example, 51
In the case of 2 dots / 96 dB, if the highest position where "1" stands is p, the converted value for this is p x 512/32. For example, when displaying the logarithmic conversion value corresponding to 2 ³² with 512 dots, when p = 28, the logarithmic conversion value corresponding to 2 ²⁸ is 10 ・ LOG (2 ²⁸ ) = 10 ・ LOG {(2 ³² ) ・2 ^28/32 } = p × 10 × LOG (2 ³² ) / 32, which is clear. A coefficient (for example, 512/32 described above) for converting the value corresponding to the position p into the number of display dots corresponding to the logarithmic conversion value is called a conversion constant here. In the data of FIG. 2 (b), p is 28. The true logarithmic conversion value is p
Since it is between × 512/32 and (p + 1) × 512/32, the mantissa part “0011” of the lower 4 bits of the most significant digit where “1” of the floating-point format input data stands is used. If it is interpolated, Y can be calculated as follows.

Y = (31-3) × 512/32 + 0 × 8 + 0 × 4 + 1 × 2 + 1
× 1 = 451 (2) In the circuit of Fig. 1, this is realized as follows. 3 (A) to (L) show detailed time charts at this time. The operation will be described below based on the floating-point format input data in FIG. The value of each data is shown in parentheses. The subtracter 2 subtracts the value (3) of the input data exponent part held in the register 1 from the word length constant value (31). The output (28) of the subtractor 2 is multiplied by the conversion constant (512/32 = 16), and the output becomes the A input value (448) of the adder 7. The conversion constant (16) is output from the shift register 4 by shifting to the LSB side bit by bit by the shift clock, and in synchronization with this, the mantissa part (1001
The output of the gate 10 corresponding to 1) becomes the clock of the register 6, but the first bit value (1) corresponding to the conversion constant (16) is cleared (0) by the clear signal. The lower value (0011) is accumulated,
This becomes the B input value (3) of the adder 7. The adder 7 outputs a value (451) obtained by adding both input values (448 and 3) as a logarithmic conversion value via the register 8.

That is, in the logarithmic conversion circuit of the above, the logarithmic transformation, as well as calculating the conversion values corresponding to 2 ^n, the linear value corresponding to the difference between the logarithmic conversion value existing between it and the 2 ⁿ and 2 ^{n + 1} A final conversion value is obtained from the values of both by performing interpolation. In the above example, the interpolation section is divided into 16. The load signal, clear signal, output clock, etc. are applied at intervals corresponding to the conversion constant.

In the embodiment of FIG. 1, since the logarithm of the mantissa part is linearly interpolated, the error becomes large. FIG. 4 is a graph showing the difference between the true value of the logarithm of the mantissa part and the value obtained in FIG. As can be seen, an error of about 0.05 occurs. In order to reduce this error, a higher-order polynomial may be used for approximation. The value N of the mantissa is a standardized value and is limited to the range of 0.5 ≦ N <1. N were placed and N = 1 + x, when subjected to a microphone Rollin deployment, Ln (1 + x) = x-x 2/2 + x 3/3 can be expressed by ....... Taking up to the second order term of the expansion type, Ln (N) = (N -1) - represented by ^{(N-1) 2/2} ...... (3). Since the approximation is rough as it is, the approximation formula is modified using the integral formula. Using integration, it can be expressed as Ln (N) = ∫ (1 / x) dx (4). In FIG. 5, this value is f
(X) = 1 / x corresponds to the area surrounded by the x-axis and x = N, x = 1. This f (x) = 1 / x is f (x) = − 2 · x
By approximating with +3 and replacing the area surrounded by this straight line with the x-axis and x = N, x = 1 (the hatched portion in FIG. 5) by the equation (4), f (x) = (N-1 ) {1-2N + 3)} / 2 = (N-1). (N-2) ... (5). Although this approximation formula also has a rough degree of approximation, it has a relationship of canceling the error with the formula (3), and therefore the arithmetic mean of the formulas (5) and (3) is calculated to obtain Ln (N) =-(N -1) {3 (N-1) -4} / 4 ...
(6) FIG. 4 shows the difference between the value obtained by this approximate expression and the true value. The difference is 0.01 or less, which is considerably improved as compared with the embodiment shown in FIG. Multiply this natural logarithm by 0.434 to convert it to the common logarithm.

FIG. 6 shows an embodiment of a logarithmic conversion circuit using the equation (6). The same elements as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 6, reference numeral 12 is an arithmetic unit, which receives the data of the mantissa part, executes the arithmetic operation of the equation (6), and converts it into a common logarithm. Reference numeral 13 denotes a multiplication unit, which receives the output of the calculation unit 13 and the conversion constant and multiplies these values. The output of the multiplication unit 13 is output to the addition unit 7, and the multiplication unit 3
Is added to the output of. FIG. 7 shows the configuration of the calculation unit 12.
The mantissa part is assumed to be represented by a binary number. In FIG. 7, reference numeral 14 denotes a subtraction unit which receives data of the mantissa part and subtracts 1 from the data of the mantissa part. Reference numeral 15 is a shifter, which shifts the output of the subtraction unit 14 to the right by 2 bits. That is, 1/4 times. Reference numeral 16 is a multiplication unit, which multiplies the output of the shifter 15 by (-1). 17 is a multiplication unit, and a subtraction unit
Multiply the output of 14 by 3. 18 is a subtraction unit, and a multiplication unit 17
Subtract 4 from the output of. Reference numeral 19 is a multiplication unit, and multiplication unit 16
And the output of the subtraction unit 18 are multiplied and output. Reference numeral 20 denotes a multiplication unit, which multiplies the output of the multiplication unit 19 by 0.434 to convert natural logarithm into common logarithm. In this way, the equation (6) is calculated. With this configuration, calculation of-(N-1) / 4 and 3 (N-
The operations 1) -4 are performed in parallel to speed up the operation. The output of the calculation unit 12 and the output of the subtractor 2 may be added before being multiplied by the conversion constant.

According to the logarithmic conversion circuit having such a configuration, since the multiplier in the logarithmic conversion circuit is also used for scaling the output, scaling can be performed at a high speed and with a simple configuration.

In the above embodiment, the multiplier 3 and the multiplication units 13, 16, 1
7,20 can also be realized by a look-up table using ROM or RAM.

<< Advantages of Device >> As described above, according to the present invention, it is possible to realize a logarithmic conversion circuit that executes scaling for display accompanying logarithmic conversion with a high-speed and simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a logarithmic conversion circuit according to the present invention, FIG. 2 is a diagram showing an expression format of input data of the apparatus of FIG. 1, and FIG. 3 is an operation of the apparatus of FIG. FIG. 4 is a characteristic curve diagram showing an error, FIG. 5 is a diagram for explaining an approximate expression, FIG. 6 is a configuration diagram of another embodiment, and FIG. 7 is a configuration diagram of an arithmetic unit. is there. 3,13 …… Multiplier, 7 …… Adder, 11 …… Accumulator, 12 ……
Arithmetic section.

Claims (2)

[Scope of utility model registration request] 1. A logarithmic conversion circuit for converting an input digital signal into its logarithmic value, which corresponds to a multiplier for multiplying a signal related to exponent data of the input digital signal by a conversion constant, and mantissa data of the input digital signal. An accumulator for calculating a linear interpolation value and an adder for adding the output of the multiplier and the output of the accumulator are provided, and scaling is possible by setting a conversion constant. Logarithmic conversion circuit. 2. A logarithmic conversion circuit for converting an input digital signal into its logarithmic value, wherein a multiplier for multiplying a signal related to exponent data of the input digital signal by a conversion constant, and mantissa data of the input digital signal are inputted. , A calculation unit that calculates a quadratic approximation formula of the logarithm of this value, a multiplication unit that multiplies the output of this calculation unit and the conversion constant, and an adder that adds the outputs of these multipliers, A logarithmic conversion circuit characterized in that scaling is possible by setting.