JP4529600B2 - MEMORY AND PROCESSOR HAVING MEMORY - Google Patents

Description

  The present invention relates to a memory for storing data necessary for audio digital signal processing. In particular, the present invention relates to a memory in which data is arranged so that an access range becomes as narrow as possible when the data is accessed via a cache memory. The present invention also relates to a processor provided with such a memory.

  In recent years, calculations using large-scale data have been performed in MPEG audio encoding and decoding processes. For example, the MPEG audio AAC system requires an operation of x ^ a (x to the power of a: a is a constant) for the input value x, and a table memory is used to perform this processing at high speed. That is, for the input value x, a desired result is obtained by extracting the value from the table memory in which the value of x ^ a is stored in the area where x is an address. However, such a method requires an excessively large memory, and therefore, a device has been devised to reduce the memory size (see, for example, Patent Document 1). The prior art will be described below with reference to FIGS. 3, 4, 5, and 7. FIG. In the following, N is 10.

  First, FIG. 3 shows an input value z which is an N + 1 digit binary number. The input value z can take the entire N + 1-digit binary range, but in FIG. 3, as an example, the input value z is assumed to be a 4-digit value. That is, the upper bit is “0” (represented by a white square) and has a value after the fourth digit from the bottom (represented by a colored square). Note that the fourth digit from the bottom is “1”.

  Next, FIG. 4 shows a preparatory process for drawing the table memory, and shows how the input value z is normalized. In other words, the input value z is shifted up by p digits according to the magnitude of the input value z, which is “1” at the top of the input value z, in this case “1” at the fourth bit from the bottom. Shift up to come to the upper bits.

  Next, FIG. 5 shows a process of determining an address for actually retrieving the table memory. That is, in the bit pattern generated in FIG. 4, since the value of the most significant bit is always “1”, no information is lost even if it is deleted, so it is deleted as an address for subtracting the table memory. .

  The table memory is drawn using the bit pattern generated in this way as an address, and the table memory stores data as shown in FIG. That is, ((1 << N) + t) ^ a is stored at the position where the address is t. Here, the reason why (1 << N) is added to t is that the address value t has been deleted because the most significant bit has been deleted as described above. By holding such a table, the address is reduced by 1 bit, so that the size of the table memory can be reduced to ½.

Now, since the value extracted from the table memory as described above is a value obtained by subjecting the original input value z to 2 ^ p and a power of a, the following correction is necessary. is there. That is, when the value extracted from the table memory as described above is T, the result obtained by correcting T * (2 ^ (-pa)) is the calculated value.
US Pat. No. 6,304,890

  However, in the method as described above, since the probability that a non-zero value is arranged on the upper bit side of the address value when accessing the table memory is increased, the same frequency is used over the entire area of the table memory. When access is performed and the table memory is accessed via the cache memory, there is a problem that cache misses frequently occur.

  The same problem as described above also occurs in signal processing using trigonometric functions. For example, in the FFT processing, a trigonometric function value for θ when A is a relatively small value at a phase angle θ = i * π / A (A is a power of 2 and i is an integer not less than 0 and less than A) ( The complex unit circle e ^ (jθ)) is used with high frequency. For example, a trigonometric function value is used at a high frequency when the phase angle is 0, π / 2, π / 4, 2π / 4, 3π / 4, or the like. Here, if such trigonometric function values are stored in the table memory in order from the smallest phase angle (or in order from the largest), the jump area is accessed widely. When accessed via a cache memory, there has been a problem that cache misses frequently occur.

  The present invention has been made in view of such a conventional problem, and a memory in which data is arranged so that an access range of a memory accessed through a cache memory is as narrow as possible, or the memory It aims at providing the processor provided with.

  In order to solve the above problem, the invention according to claim 1 of the present application is a memory for storing a value of a function F (x) for a value x which is an N-digit binary number, and the value x The value of the function F (x) corresponding to the value x is stored at a position where the address is an N-digit binary number y obtained by placing the lower-order bits in the higher-order side. To do.

  The invention according to claim 2 of the present application is the memory according to claim 1, wherein the value x is obtained by normalizing the value z which is a binary number of N + 1 digits from the value z ′ obtained by normalizing the value z ′. It is an N-digit binary number obtained by deletion, and the function F (x) is characterized by performing a predetermined process on the value of x + (1 << N).

  Invention of Claim 3 of this application is the memory of Claim 1 or Claim 2, Comprising: The said function F (x) is a function which gives the a power of x + (1 << N), It is characterized by the above-mentioned. It is what.

  The invention according to claim 4 of the present application is the memory according to claim 1, wherein when θ is a phase angle having a domain of 0 or more and less than π, the value x is a value expressing the θ, The value of (1 << N) * θ / π is represented by an N-digit binary number.

  The invention according to claim 5 of the present application is the memory according to claim 4, wherein the function F (x) is a function that gives a trigonometric function for the θ represented by the value x. is there.

  The invention according to claim 6 of the present application is the memory according to claim 4, wherein the function F (x) gives a complex number e ^ (jθ) (j is an imaginary number unit) for the θ represented by the value x. It is characterized by being a function.

  The invention according to claim 7 of the present application is the memory according to any one of claims 1 to 6, wherein the binary number y is a value obtained by bit position reverse order processing of the value x. It is a feature.

  The invention according to claim 8 of the present application is the memory according to any one of claims 1 to 7, further comprising a cache memory, wherein data is accessed via the cache memory. It is.

  The invention according to claim 9 of the present application is a processor including the memory according to any one of claims 1 to 8, which is obtained by arranging the lower-order bits of the input value x on the upper-order side. Bit exchanging means for generating an N-digit binary number y, data fetching means for fetching data from the memory using the N-digit binary number y as an address, and computing means for performing a predetermined computation using the fetched data It is characterized by having.

  According to the first aspect of the present invention, when there is a high probability that the lower-order bit of x will be a predetermined value, it is possible to narrow the frequently accessed area of the memory storing the value of the function F (x). .

  According to the invention of claim 2, the size of the memory for storing the value of the function F (x) can be halved, and the area with high access frequency can be narrowed.

  According to the invention of claim 3, when the function F (x) is a function that gives a power, the size of the memory for storing the value of the function F (x) can be halved. Therefore, it is possible to narrow the area with high access frequency.

  According to the fourth aspect of the present invention, when F (x) is a function that handles the phase angle, it is possible to narrow a memory area that frequently stores the value of the function F (x).

  According to the fifth aspect of the present invention, when F (x) is a function that handles a trigonometric function, it is possible to narrow a frequently accessed area of the memory that stores the value of the function F (x).

  According to the sixth aspect of the present invention, when F (x) is a function that handles a complex number e ^ (jθ) (j is an imaginary unit), the access frequency of the memory that stores the value of the function F (x) The high area can be narrowed.

  According to the seventh aspect of the present invention, it is possible to narrow a frequently accessed area of the memory storing the value of the function F (x) by simple bit position reverse order processing.

  According to the invention of claim 8, the probability of a miss hit in the cache memory is reduced.

  According to the ninth aspect of the present invention, in a processor that performs predetermined signal processing, it is possible to narrow a frequently accessed area of a memory that stores the value of the function F (x).

(Embodiment 1)
Hereinafter, a memory and a processor using the memory according to the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a processor according to the first embodiment. In FIG. 1, 100 is a memory for storing the value of the function F (x) with respect to a value x that is an N-digit binary number, and 101 is an input value z that can be expressed by an N + 1-digit binary number. A normalizing unit that normalizes the input value z according to the magnitude of the input value z, deletes the most significant bit from the value normalized by the normalizing unit 101, and cuts out the lower N bits to obtain N digits. A bit cut-out means for generating a value x that can be expressed by the following: 103, a bit replacing means for generating an N-digit binary number y obtained by placing the lower-order bits of the value x that can be expressed by the N-digits on the higher-order side; Reference numeral 104 denotes data extraction means for extracting data from the memory using the N-digit binary number y as an address, and reference numeral 105 denotes calculation means for performing a predetermined calculation using the extracted data.

  Here, the input value z is a quantized value according to the MPEG standard AAC method, and the processor according to the first embodiment is a processor that performs a process of raising the input value z to a power.

  FIG. 2 is a diagram showing the contents of the memory in the first embodiment.

  The memory shown in FIG. 2 corresponds to the memory 100, and stores the value of the function F (x) with respect to the value x, which is an N-digit binary number, and is a subordinate of the value x. The value of the function F (x) corresponding to the value x is stored at the position where the N-digit binary number y obtained by placing the bit on the higher side is the address. In the present embodiment, it is assumed that the function F (x) is a function that raises a value obtained by adding (1 << N) to x.

  In the present embodiment, N is 10 in 1, but it goes without saying that other values may be used.

  FIG. 3 shows an example of an input value that can be expressed by the N + 1 digit binary number. FIG. 4 shows the operation of the normalizing means 101. FIG. 5 shows the operation of the bit cutout means 102. FIG. 6 shows the operation of the bit exchanging means 103.

  The operation of the processor configured as described above will be described below.

  First, FIG. 3 shows an input value z which is an N + 1 digit binary number. This corresponds to the input value z in FIG. The input value z can take the entire N + 1-digit binary range, but in FIG. 3, as an example, the input value z is a 4-digit value. That is, the upper bit is “0” (represented by a white square) and has a value after the fourth digit from the bottom (represented by a colored square). Note that the fourth digit from the bottom is “1”.

  Next, FIG. 4 shows the operation of the normalizing means 101, and shows a preparation process before the memory 100 is pulled. In other words, the input value z is shifted up by p digits according to the magnitude of the input value z, which is “1” at the top of the input value z, in this case “1” at the fourth bit from the bottom. Shift up to come to the upper bits.

  Next, FIG. 5 shows the operation of the bit cutout means 102. That is, in the bit pattern generated in FIG. 4, since the value of the most significant bit is always “1”, information is not lost even if it is deleted. Therefore, it is deleted as an address for subtracting the memory 100. Yes.

  Next, FIG. 6 shows a process of determining an address for actually retrieving the memory 100. In the first embodiment, for the value cut out by the bit cutout means 102, an address for actually pulling the memory 100 is determined by the bit position reverse order processing. The reason why the bit position reverse order processing is performed here is to move “0” as far as possible to the bit position to the upper side, as is apparent from FIG. In the first place, since the value cut out by the bit cutout unit 102 is a value normalized by the normalization unit 101, in many cases, there is a high probability that “0” exists in the lower bit position. This is because the original input value z is a quantized value of the AAC standard, and the value is often a small value. Therefore, by performing the bit position reverse order processing in the bit replacement means 103, the probability that “0” is gathered at the upper bit position is increased, and as a result, the area where the access frequency to the memory 100 is high is narrowed. Can do.

  The memory 100 is pulled by the data extracting means 104 using the bit pattern thus generated as an address. The memory 100 stores data as shown in FIG.

  That is, ((1 << N) + s) ^ a is stored in the position where the address is t, where s is a value obtained by the bit position reverse order processing of t.

  Here, the reason why (1 << N) is added to t is that the address value t has been deleted because the most significant bit has been deleted as described above. By having such data, the address is reduced by 1 bit, so that the memory size can be reduced to ½.

  Here, the value extracted from the memory 100 as described above is a value obtained by subjecting the original input value z to 2 ^ p and a process of a-th power, so the following correction is necessary. It is. That is, when the value taken out from the memory 100 as described above is T, the result of correcting T * (2 ^ (-pa)) is the value to be obtained.

  In the present embodiment, N = 10, but it goes without saying that other hot spots may be used.

  As described above, in the first embodiment, since the probability that the value of the upper bit position of the address when the memory 100 is pulled becomes “0” is high, the area with high access frequency of the memory 100 is Therefore, it concentrates on the area where the address value is small. Accordingly, when the memory 100 is accessed via a cache memory, the possibility of a miss hit is reduced.

(Embodiment 2)
Hereinafter, a memory according to Embodiment 2 of the present invention will be described with reference to the drawings.

  FIG. 8 is a diagram showing the contents of the memory according to the second embodiment. The memory shown in FIG. 8 is a memory for storing a trigonometric function value corresponding to a value x which is an N-digit binary number. The value x is a value expressing the phase angle θ whose domain is a value of 0 or more and less than π, and is a value expressing the value of (1 << N) * θ / π in an N-digit binary number. . The stored trigonometric function value is a trigonometric function value for the θ expressed by the value x.

  In FIG. 8, a trigonometric function corresponding to the value x at a position where the address is an N-digit binary number y obtained by the process of switching the lower bit and the higher bit of the value x, that is, the bit position reverse order process. A value is stored.

  By arranging the trigonometric function values at the positions as described above, the following effects can be obtained. For example, in processing such as FFT, a trigonometric function value for θ when A is a relatively small value at a phase angle θ = i * π / A (A is a power of 2 and i is an integer not less than 0 and less than A). Alternatively, the complex unit circle (e ^ (jθ)) is used with high frequency. For example, a trigonometric function value is used at a high frequency when the phase angle is 0, π / 2, π / 4, 2π / 4, 3π / 4, or the like. Here, if such trigonometric function values are stored in the memory in order from the smallest phase angle (or in order from the largest), the skipped area is accessed widely, so that the memory is the cache memory. In such a case, cache misses frequently occur. However, if arranged as shown in FIG. 8, the trigonometric function value for the phase angle 0 is stored at the address 0 position, and the trigonometric function value for the phase angle (π / 2) is stored at the address 1 position. The trigonometric function value for the phase angle (π / 4) is stored at the position 2, the trigonometric function value for the phase angle (3π / 4) is stored at the address 3 position, and the phase angle (π / 8) is stored at the address 4 position. The trigonometric function values frequently accessed in the FFT processing are stored in a concentrated area with a small address value, and the number of cache misses can be reduced.

  Although the memory for storing the cosine function value is shown in the second embodiment, it goes without saying that the memory for storing the sine function value can be configured similarly. In addition, a memory for storing a complex number (complex unit circle (e ^ (jθ))) composed of a pair of a cosine function value and a cosine function value can also be configured in the same manner, an example of which is shown in FIG. The value and the sine function value are stored in the adjacent bit field.

  In the second embodiment, N is set to 10, but it goes without saying that other values may be used.

  The memory and the processor according to the present invention relate to a memory for storing data necessary to perform audio digital signal processing, and in particular, when accessing the data via a cache memory, the access range becomes as narrow as possible. Since the data is arranged as described above, it can be applied to a small-sized, power-saving audio device.

The figure which shows the structure of the processor in this Embodiment 1. The figure which shows the content of the memory in this Embodiment 1. Diagram showing an example of input values Diagram showing the operation of normalization means The figure which shows the operation of the bit extraction means Diagram showing the operation of the bit swapping means The figure which shows the contents of the memory with conventional technology The figure which shows the content (trigonometric function value) of the memory in this Embodiment 2. The figure which shows the content (complex number e ^ (j (theta)) (j is an imaginary unit)) in this Embodiment 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory 101 Normalization means 102 Bit extraction means 103 Bit replacement means 104 Data extraction means 105 Calculation means

Claims (9)

This is a memory for storing the value of the function F (x) for the value x which is an N-digit binary number, and is obtained by arranging the lower-order bits of the value x on the upper-order side. A memory in which a value of a function F (x) corresponding to the value x is stored at a position having a binary number y as an address. The value x is an N-digit binary number obtained by deleting the most significant bit from a value z ′ obtained by normalizing the value z, which is an N + 1 digit binary number,
2. The memory according to claim 1, wherein the function F (x) performs a predetermined process on a value of x + (1 << N). The memory according to claim 1, wherein the function F (x) is a function that gives x + (1 << N) to the power a. When θ is a phase angle having a range of 0 or more and less than π, the value x is a value expressing the θ, and the value of (1 << N) * θ / π is expressed by an N-digit binary number. The memory according to claim 1, wherein the value is a calculated value. The memory according to claim 4, wherein the function F (x) is a function that gives a trigonometric function for the θ represented by the value x. 5. The memory according to claim 4, wherein the function F (x) is a function that gives a complex number e (jθ) (j is an imaginary unit) for the θ represented by the value x. The memory according to any one of claims 1 to 6, wherein the binary number y is a value obtained by a bit position reverse order process of the value x. 8. The memory according to claim 1, further comprising a cache memory, wherein data is accessed through the cache memory. A processor comprising the memory according to any one of claims 1 to 8, wherein the bit generates an N-digit binary number y obtained by placing a lower bit of an input value x on a higher side. A processor, comprising: replacement means; data fetching means for fetching data from the memory using the N-digit binary number y as an address; and computing means for performing a predetermined calculation using the fetched data.

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