JPH02287873A - Product sum arithmetic unit - Google Patents

Abstract

PURPOSE:To execute the arithmetic processing with high accuracy by bringing a coefficient to 2<n> multiple, multiplying it as a coefficient in which a difference of the maximum value and the minimum value of its value becomes two folds or below by plural input signals, respectively, and also, bringing a result of each multiplication to 2<-n> multiple in accordance with 2<n> multiple of the coefficient and adding them. CONSTITUTION:Input digital data A - D are converted into serial data by P-S converting circuits 38 - 41, respectively, and thereafter, supplied to multiplying circuits 42 - 45, and coefficient data of 8 bits stored in each coefficient ROM 46 - 49 are multiplied. In this case, the coefficient data stored in each coefficient ROM 46 - 49 are multiplied in advance by 2<n>(n = 0, + or -1, + or -2, + or -3,...), and corrected so that a difference of the maximum value and the minimum value thereof becomes two folds or below. Subsequently, a result of this multiplication is supplied to S-P converting circuits 50 - 53, respectively, and converting into parallel data of 8 bits or more, based on a clock outputted from a timing control circuit 54. In such a way, an arithmetic processing of high accuracy can be executed without increasing the number of bits of data.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a product-sum calculator used for example in digital filters, and particularly relates to a product-sum calculator used in digital filters, etc. It relates to something that can perform high-level calculations.

(Prior Art) As is well known, product-sum calculators are widely used in digital signal processing in general, and in particular in digital filters (DF).
It is indispensable when configuring a digital signal processor (DSP) or a digital signal processor (DSP).

FIG. 4 shows such a conventional product-sum calculator.

That is, in the figure, 11 to 14 are input terminals, to which, for example, 8-bit input digital data A to D are respectively supplied in parallel.

Input digital data A-D supplied to these input terminals 11-14 are converted into serial data by p-s (parallel-serial) conversion circuits 15-18, respectively, and then supplied to multiplication circuits 19-22. Each coefficient ROM
(Read-only memory) Coefficient data of 9 bits or more stored in 23 to 26 is multiplied.

The multiplication results serially output from each multiplication circuit 19 to 22 are 5-P (serial-parallel).
The clock input terminal 31 is supplied to the conversion circuits 27 to 30.
The data is converted into parallel data of 8 bits or more at the same timing based on a clock CK of a constant period supplied to the data.

Thereafter, the parallel data outputted from each S-P conversion circuit 27 to 30 is added by the addition circuit 32, thereby producing an 8-bit or more output digital data obtained by performing a sum-of-products operation on the human-powered digital data A to D. Data E is taken out from output terminal 33.

Here, each coefficient data stored in the coefficient ROMs 23 to 26 is set to a value smaller than "1" in order to prevent data being processed from overflowing.

That is, assuming that the coefficient ROMs 23 to 26 are 8 bits, the coefficient data is -128/128 to L/1.
28. It can take values in the range of O, l/128 to 127/128.

However, in the conventional product-sum calculation unit as described above, in order to improve the calculation accuracy and use highly accurate coefficient data that exceeds the range of the coefficient pigtails described above, the coefficient ROM 23 is required.
The only way is to increase the number of bits to ~26.

For example, to obtain coefficient data of 7.5/128, increase coefficient ROM23 to 26 by 1 bit to make it 15/2.
56, which may cause an economic disadvantage.

In addition, increasing the number of bits in the coefficient ROMs 23 to 26 does not change the number of bits in the multiplication circuits 19 to 22 and the
This is disadvantageous in that it also leads to an increase in the scale of the second-class circuit.

(Problems to be Solved by the Invention) As described above, in order to improve the calculation accuracy of conventional multiply-accumulators, it is necessary to increase the number of bits of data handled, which increases the circuit scale and makes it economically difficult. It has the problem of being disadvantageous.

Therefore, this invention was made in consideration of the above circumstances, and aims to provide an extremely good product-sum calculator that can perform highly accurate arithmetic processing without increasing the number of bits of data handled. purpose.

[Structure of the Invention] (Means for Solving the Problems) A product-sum calculator according to the present invention is intended for multiplying a plurality of input signals by respective coefficients and adding the respective multiplication results. Then, set the coefficient to 2″ (n=0. ±1.±2
．． ±3,...), then multiply each of the multiple input signals as a coefficient that makes the difference between the maximum value and minimum value within 2 times, and multiply each multiplication result by 2'' by the coefficient. The structure is such that the result is multiplied by 2 and added accordingly.

Ru.

(Function) According to the above configuration, for example, the coefficient 7.5/128, which cannot be expressed in 8 bits, can be expressed in 8 bits as 120/128 by multiplying by 24, and furthermore, the maximum value can be expressed as 120/128 in 8 bits. If the difference between
In effect, the possible values of a coefficient are only half the number of bits of the coefficient, without increasing the number of data bits.
This means that highly accurate arithmetic processing can be performed.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. That is, in FIG. 1, 34 to 37 are input terminals to which, for example, 8-bit input digital data A to D are respectively supplied in parallel.

The input digital data A-D supplied to these input terminals 34-37 are converted into serial data by P-8 conversion circuits 38-41, respectively, and then sent to multiplication circuits 42-45.
and is multiplied by 8-bit coefficient data stored in each coefficient ROM 48-49.

Here, the coefficient data stored in each coefficient ROM 48 to 49 is 2'' (n=o, ±1.±2.±3°...
) is multiplied, and the difference between the maximum value and the minimum value is corrected to within twice.

The multiplication results serially output from each of the multiplication circuits 42 to 45 are supplied to S-P conversion circuits 50 to 53, respectively, and based on the clock output from the timing control circuit 54, parallel data of 8 bits or more is converted. is converted to

Here, the above-mentioned S-P conversion circuit 50 is configured as shown in FIG. Note that the other S-P conversion circuits 51 to 5
3 has the same configuration as the S-P conversion circuit 50, so the explanation thereof will be omitted.

That is, numeral 55 in the figure is an input terminal to which multiplied serial data output from the multiplication circuit 42 is supplied.

The serial data supplied to this input terminal 55 is supplied to a clock input terminal 64 by a shift register 63 formed by cascading seven D-type flip-flop circuits (hereinafter referred to as D-FF circuits) 56 to 62. The bit clock BCK is sequentially captured in synchronization with the bit clock BCK.

The data latched in each of the D-FF1 paths 56 to 62 is transferred to the latch clock LCK supplied to the clock input terminal 66 by an 8-bit latch circuit 65.
The signals are latched all at once in synchronization with and output from eight output terminals 67, where serial-to-parallel conversion is performed.

Here, the 8-bit parallel data output from the output terminal 67 uses the latch clock LCK as the bit clock B.
It can be doubled or halved by generating it one clock earlier or later than CK.

Therefore, the coefficient data is first multiplied by 2'' in the coefficient ROMs 46 to 49, and then multiplied by 2'' in the S-P conversion circuits 50 to 53.
-Can be multiplied by 1.

Then, the parallel data output from each of the S-P conversion circuits 50 to 53 is added by the addition circuit 68, thereby producing an 8-bit or more output digital data obtained by performing a sum-of-products operation on the human-powered digital data A to D. Data E is taken out from output terminal B9.

According to the above configuration, even coefficient data such as 7.5/128 that cannot be expressed in 8 bits can be expressed as 2n.
(=IB) can be expressed in 8 bits as 120/128.

Also, since the difference between the maximum value and the minimum value of the coefficient data multiplied by 24 is set to within 2 times, that is, 64/128 to 128/128, the values that the coefficient data can take are essentially: It only requires half the number of bits of the coefficient data.

Furthermore, 2(-1/
By extracting the parallel data at the timing of 1B), highly accurate arithmetic processing can be performed without increasing the number of data bits.

FIG. 3 shows another embodiment of the invention.

That is, the 8-bit input digital data A-D supplied to the input terminals 70-73 is directly input into the coefficient ROM by the multiplication circuits 74-77 without being converted into serial data.
Multiply by the coefficient data (multiplied by 2'') stored in 78 to 81.

After this multiplication result is bit-shifted by bit shift circuits 82 to 85 so as to be multiplied by 2-'', an addition circuit 86
By adding the input digital data A
Output digital data E of 8 bits or more, which is obtained by performing a sum-of-products operation on -D, is taken out from the output terminal 87.

According to the configuration of the above embodiment, a P-3 conversion circuit or the like is not required, and the configuration can be further simplified.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide an extremely good product-sum calculator that can perform highly accurate arithmetic processing without increasing the number of bits of data handled. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the product-sum calculator according to the present invention, FIG. 2 is a block diagram showing details of the S-P conversion circuit of the embodiment, and FIG. FIG. 4 is a block diagram showing another embodiment. FIG. 4 is a block diagram showing a conventional product-sum calculator. 11-14...Input terminal, 15-18...P-8 conversion circuit, 19-22...Multiplication circuit, 23-26...
Coefficient ROM, 27-30... S-P conversion circuit, 31.
...Clock input terminal, 32... Addition circuit, 33...
・Output terminals, 34-37...Input terminals, 38-41・
・・P-8 conversion circuit, 42 to 45 ・・Multiplication circuit, 46
~49... Coefficient ROM, 50-53... S-P conversion circuit, 54... Timing control circuit, 55... Input terminal, 56-62... D-FF circuit, 63... Shift Register, 64... Clock input terminal, 65... Latch circuit, 6G... Clock input terminal, 67... Output terminal, 68... Addition circuit, 69... Output terminal, 70
~73...Input terminal, 74-77...Multiplication circuit, 78
~81...Coefficient ROM, 82-85...Bit shift circuit, 8G...Addition circuit, 87...Output terminal.

Claims (1)

[Claims] In a product-sum calculator that multiplies multiple input signals by coefficients and adds the multiplication results, the coefficients are calculated as 2^n (n=
0, ±1, ±2, ±3, ...), and multiply each of the plurality of input signals by a coefficient such that the difference between the maximum value and the minimum value is within 2 times, and each multiplication A product-sum calculator characterized in that the result is multiplied by 2^-^n corresponding to the coefficient multiplied by 2^n and added.