JPH0997166A - Digital multiplier, digital transversal equalizer, and digital product sum operation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale to realize high-speed multiplication or product sum operation by reducing the number of bits of a partial product generated in a multiplication part. SOLUTION: With respect to a digital multiplier, a digital transversal equalizer, and a digital product sum operation circuit which consist of a partial product generation circuit for partial product bit generation and a Wallace Tree circuit for partial product addition, bits of a partial product on the least significant bit side are not generated and are omitted or the sign (polarity) of a multiplier (coefficient value) is fixed or the set range of the coefficient value is limited (the dynamic range of the coefficient value is reduced) to reduce the number of bits of the generated product sum. Further, the error component due to omission of lower bits is corrected to keep the operation precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multiplier for digital signal processing, a digital transversal type equalizer and a digital sum-of-products arithmetic circuit, and more particularly,
It is possible to perform multiplication or multiply-accumulate operation at high speed.
The present invention relates to a digital multiplier, a digital transversal type equalizer, a digital product-sum operation circuit, and a digital signal processing device using them.

[0002]

2. Description of the Related Art A conventional multiplication structure in digital signal processing is, for example, a carry save adder parallel multiplier described in paragraphs 243 to 244 of "Digital Signal Processing Handbook" edited by the Institute of Electronics, Information and Communication Engineers; There are parallel multipliers that use the second-order Booth algorithm for generating partial products, and parallel multipliers that use the Wallace Tree method for adding partial products. In addition, Japanese Patent Publication No. 5-84530 describes that the configuration when the Booth method and the Wallace Tree method are combined is the fastest multiplication method. In addition, the Wallace Tree method makes it easy to apply the pipeline method by adjusting the number of stages of adders.

As an example of the configuration of the conventional 6-bit × 7-bit multiplication, a configuration using the partial product generation by the secondary Booth method of FIG. 9 and the Wallace Tree method, FIG.
A partial product is generated by the method of parallel multiplication of and the configuration using the method of Wallace Tree is shown. FIG. 11 shows a partial product generation circuit by the secondary Booth method used in FIG.
FIG. 12 shows a partial product generation circuit by parallel multiplication.

Table 1 compares the configurations of FIGS. 9 and 10 in terms of circuit scale and operation delay time. Table 1
The circuit scale reduction column of the configuration guide is the configuration when the circuit scale is minimized, and the calculation delay time is not taken into consideration. Further, the column of the calculation delay reduction of the configuration guide is the structure when the calculation delay is minimized, and the circuit scale is slightly increased.

[0005]

[Table 1]

As shown in FIG. 9, the Booth method requires a large number of circuits and exceeds the reduction amount of the circuit scale in the addition portion of the Wallace Tree method, resulting in a large scale as a whole. Regarding the delay time, as can be seen from FIG. 11,
Since the circuit delay is relatively large for the partial product generation and the calculation of the negative value is necessary (in this example, the method of adding 1 to the complement of 1 is used). Bits of partial products increase on the side, and it takes time to converge the bits.

Since the parallel multiplication method is used in FIG. 10, as can be seen from FIG. 12, the number of circuits for generating partial products is small, the circuit delay time is short, and the least significant bit is directly output. However, since the number of bits of the partial product does not particularly increase on the least significant bit side, the convergence of bits becomes faster. However, since the number of bits of the partial product is large as a whole,
Although the circuit scale of the Wallace Tree method is large, the multiplier as a whole is smaller than the multiplier of FIG. However, the circuit scale is still large.

In the transversal type equalizer, some of the multipliers shown in FIG. 9 and FIG. 10 are used in combination, the multiplication result is obtained, and they are added to obtain the operation result. FIG.
Shows a conventional example of a transversal equalizer having a multiplier of 7 bits, a multiplicand of 6 bits, and 7 taps. This is a circuit in which the multiplier shown in FIG. 10 and a Wallace Tree circuit are combined. If the multiplier configuration is a large-scale circuit that cannot support high-speed operation, even if a transversal-type equalizer is configured using this circuit, the circuit size of the transversal-type equalizer is reduced and the speed is increased. It is difficult. Therefore, even in the transversal type equalizer, it is indispensable to improve the structure of each multiplier.

Since the 1-bit full adder used in the Wallace Tree circuit has 2 outputs for 3 inputs as shown in FIG. 13A, one 1-bit full adder can reduce 1 bit. I know there is. Further, the half adder (almost half of the full adder in terms of circuit scale and circuit delay) has two outputs for two inputs as shown in FIG. 13B, so there is no direct effect on the bit reduction. , It only has the effect of causing carry. Therefore, the configuration without using the half adder can reduce the circuit scale. However, it is somewhat possible to speed up the carry and speed up the bit convergence by using a lot of half adders. Therefore, Wall
The minimum circuit scale of the ace Tree circuit can be roughly estimated from the number of input bits and the number of output bits as follows.

[0010]

[Equation 1]

As can be seen from this equation, in order to reduce the circuit scale of the Wallace Tree circuit, it is conceivable to reduce the number of bits of the input partial product, increase the number of output bits, and reduce the circuit scale of the full adder. .

The number of output bits is usually determined by the number of bits of the multiplier and the multiplicand and is difficult to increase. Further, in practice, the data may be rounded before being output, and the number of output bits tends to decrease.

Next, reducing the circuit scale of the full adder is a basic circuit for realizing the addition function, and therefore there is a limit to the reduction of the circuit.

[0014]

Therefore, as a remaining structure for reducing the circuit scale, it is conceivable to reduce the number of bits of the partial product to be input. According to the present invention, in the digital multiplier, the digital transversal type equalizer, and the digital sum-of-products arithmetic circuit, the circuit scale is reduced by reducing the number of bits of the partial product generated in the multiplication part. Accordingly, it is an object of the present invention to provide a digital multiplier, a digital transversal type equalizer, and a digital product-sum operation circuit which are capable of performing multiplication or product-sum operation at high speed. At the same time, a configuration for correcting an error caused by the reduction in the number of bits of the partial product is also provided.

[0015]

According to the present invention, a digital multiplier comprising a partial product generating circuit for generating bits of partial products in multiplication and a Wallace Tree circuit for adding partial products, and a digital transversal type equalizer. A digital multiplier and a digital sum-of-products arithmetic circuit, the number of bits of partial products generated in the multiplication process is reduced to speed up the operation by increasing the convergence in the addition of bits of partial products, and The circuit scale can be reduced at the same time. Further, by using a Wallace Tree circuit as the adder circuit, it is easy to apply pipeline processing and further speedup is possible.

The first configuration for reducing the number of bits of the partial product generated in the multiplication process is to cut off and delete the bits of the partial product on the least significant bit side without generating them. When using a Wallace Tree circuit as an adder circuit for partial products, the addition result is determined from the lower-order bit side in particular, so the bits of the partial product on the lowest-order bit side are generated for speedup. It is useful to truncate without deleting. For example, if three digits on the least significant bit side are not generated and are truncated and deleted, the bits of the partial product of 6 bits can be reduced by one multiplication. this is,
The 6 × 7-bit multiplication (multiplicand is 6 bits) reduces the circuit size by about 14%, and the convergence of addition is
It converges faster by the delay time of one full adder.
Further, the error caused by the bit truncation at this time is about 0.4% with respect to the output range of the multiplier.

In the above-described configuration for reducing the number of bits of the partial product, by truncating the lower bits, an error occurs in the calculation. By correcting the generated error, it is possible to maintain the calculation accuracy. A first configuration example for correcting the error is to add the correction amount as a fixed value. For example, the size of the error can be reduced by adding a bit having a value that is ½ of the maximum value of the truncated bits. Since the correction value is a fixed value, for example, as shown in FIG. 14, the correction can be performed with a circuit as simple as a half adder.

A second configuration example for correcting the error is to change the correction amount by a multiplier. This is because the size of the truncated bits depends on the multiplier. The correction amount is calculated according to the multiplier, and the value is added in the same manner as the bits of the partial product to further reduce the error that occurs. It is relatively easy to obtain the correction value from the multiplier, and the circuit delay and the circuit scale are insignificant.

A third configuration example for correcting an error is to allow the correction amount to be set arbitrarily. In the above configuration example, instead of obtaining the correction value, a register or the like is provided and an arbitrary value is set to perform the correction.

The first, second and third configuration examples as described above not only correct the error due to truncation, but also
It is possible to add an arbitrary value, for example, it is possible to correct the offset of the circuit, etc., and it also functions as an arithmetic circuit for adding an arbitrary value.

In the transversal type equalizer, the first structure for reducing the number of bits of the partial product generated in the multiplication process is the same as the multiplier in the number of bits of the partial product generated in the multiplication process. Is to reduce.
In particular, when using the Wallace Tree circuit as an adder circuit for partial products, the addition result is determined from the lower-order bit side, so the bits of the partial product on the lowest-order bit side are also generated for speedup. It is a truncation without deleting it. For example, in a 7-tap transversal type equalizer, each tap consists of a 6 × 7-bit multiplier (multiplicand is 6 bits), and the 3 digits on the least significant bit side of each tap are truncated without being generated. Then, the bit of the partial product of 6 bits can be reduced by the multiplication of 1 tap, and the total reduction is 42 bits. This reduces the circuit scale by about 14% and also speeds up the convergence of addition. Also, the error caused by the bit truncation at this time is
The maximum is about 2.5% with respect to the output range of the multiplier.

Also in the transversal type equalizer having the above-mentioned first configuration, as in the case of the multiplier, an error occurs in the calculation by truncating the lower bits. By correcting the generated error, it is possible to maintain the calculation accuracy. In that case, instead of correcting the error amount for each tap, the correction amount of each tap is added in advance and calculated collectively, thereby reducing the number of bits for correction and reducing the circuit scale. To do. Like the multiplier, the configuration example of the error correction may be a configuration example in which the correction amount is added as a fixed value, a configuration example in which the correction amount is variable, or a configuration example in which the correction amount can be arbitrarily set.

The sign (polarity) of the multiplier (coefficient value) of each tap of the transversal type equalizer is generally alternating, and the sign of the coefficient is fixed. With that feature,
Multiplier (coefficient value) of each tap of transversal equalizer
By fixing the sign (polarity) of, the bits of the partial product generated by the calculation of the sign bit are truncated and deleted without being generated. This is the second configuration for reducing the bit number of the partial product. For example, in a 7-tap transversal type equalizer, each tap is composed of a 6 × 7-bit multiplier (multiplicand is 6 bits), and if the coefficient bit of each tap is fixed, the multiplication of 1-tap The bits of the partial product of 6 bits can be reduced as the operation amount. This reduces the circuit scale by about 14%, and the convergence of addition will converge somewhat faster as the bits of the partial product are reduced (about the improvement of the wiring length due to the reduction of the circuit scale. ).

A third configuration for reducing the number of bits of partial products generated in the multiplication process is to narrow the setting range of the coefficient value of the taps far from the center tap of the transversal equalizer (to reduce the dynamic range). By restricting, the number of bits of the partial product generated is reduced. Generally, in a transversal type equalizer, a tap farther from the center tap has a multiplier (coefficient value) of a value having a smaller absolute value. Therefore, the number of bits of the partial product generated is reduced by keeping the setting range of the coefficient value of the tap far from the center tap small. For example, in a 7-tap transversal equalizer, each tap consists of a 6 × 7-bit multiplier (multiplicand is 6 bits),
By limiting the dynamic range of the multiplier of one tap to the range of 1/4, the number of bits of the multiplier can be reduced by 2 bits. Therefore, the bits of the partial product of 12 bits can be reduced as the operation amount of the coefficient bit in one multiplication in that case.
This reduces the partial product of 24 bits in the whole circuit,
The circuit scale is reduced by about 8%. Further, the improvement of the convergence of the addition cannot be expected so much, and the convergence is somewhat fast (about the improvement of the wiring length due to the reduction of the circuit scale).

The general characteristic of the transversal type equalizer is that the sign of the multiplier of each tap has an alternating property, the sign of the coefficient is fixed, and that the taps far from the center tap are separated. The fact that the magnitude (absolute value) of the coefficient value is small has been described above, and the circuit scale reduction configuration using that feature has been shown. However, in the transversal type equalizer, the tap coefficients at both ends are
Although the magnitude (absolute value) of the coefficient value is small without following the above-mentioned characteristics, the sign of the coefficient may not be determined in some cases. for that reason,
There is also a configuration in which the tap coefficients at both ends are not fixed and have both polarities. In this case, the effect of reducing the circuit scale is reduced, but the opportunities for applying the third configuration are increased.

Further, in the taps of the transversal type equalizer, when there are always taps having the same multiplier, as a configuration for reducing the bit number of the partial product generated in the multiplication process, the multiplicand is first calculated. It is possible to reduce the generation of partial products by adding and then multiplying by a multiplier. For example, with a 7-tap transversal equalizer,
Each tap is a 6 × 7 bit multiplier (multiplicand is 6 bits)
And if there is always one tap with equal multipliers, then 6
Even if the multiplicand of bits is added first and the multiplication of the multiplicand of 7 bits and the multiplier of 7 bits is performed, the partial product is reduced by 35 bits. However, since an adder circuit for first adding the multiplicand and a latch circuit for holding the added multiplicand are required, the effect of reducing the circuit scale is reduced. The convergence of the addition is definitely better and faster.

The configuration in which the circuit scale is reduced by truncating and deleting the partial product bit on the least significant bit side of the multiplication does not generate a product-sum operation circuit without a fixed form like a transversal type equalizer. Can also be applied. Similar to the transversal type equalizer, it is possible to collectively correct the error caused by truncating and deleting the partial product bit on the least significant bit side without generating it.

By reducing the number of bits of the partial product generated in the multiplication process by using the above configuration,
It is possible to speed up the convergence in the addition of the bits of the partial products. As a result, it is possible to realize high-speed multiplication or high-speed transversal equalizer having a product-sum operation. Further, at the same time, it is possible to reduce the circuit scale to a small size, and there is an advantage that power consumption can be reduced.
Further, by using the Wallace Tree circuit as the adder circuit, it is possible to easily apply the pipeline processing, and further, it is possible to cope with the speedup.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic operation of the first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is composed of a diagram (a) showing generation of partial products by a parallel multiplication method of a 6-bit × 7-bit multiplier and a diagram (b) showing a bit flow. Originally 44
Partial product of bits (including correction bits for 2's complement)
Is truncated, the partial product of 6 bits for 3 digits on the least significant bit side is not generated but is truncated and deleted, so that only the partial product of 38 bits is generated. Therefore, the number of bits input to the Wallace Tree circuit for adding partial products is 38 bits, which is 6 bits less. Therefore,
The circuit scale for the partial product generation and the Wallace Tree circuit is smaller, and the bit convergence is faster. As can be seen from Table 2, the circuit scale is reduced by about 13 to 16%, and the calculation delay until the calculation result is output is reduced by 1/2 to 1 stage with a full adder, resulting in high speed. . Table 2
The circuit scale reduction column of the configuration guide is the configuration when the circuit scale is minimized, and the calculation delay time is not taken into consideration. Further, the column of the calculation delay reduction of the configuration guide is the structure when the calculation delay is minimized, and the circuit scale is slightly increased.

[0031]

[Table 2]

The basic operation of the second embodiment of the present invention will be described with reference to FIG.

FIG. 2 shows a state in which an error amount due to the truncation of the least significant bit is corrected in the first embodiment, and 6-bit × 7-bit multipliers are connected in parallel. It consists of figure (a) showing the generation of partial products by the method of multiplication and figure (b) showing the flow of bits. If the size of 1 bit of the least significant bit is 1 [LSB], the maximum and minimum of the truncated bits are 17 [LSB] and 0 [LSB], respectively.
Therefore, here, 8 [LSB] is corrected as a fixed value. Therefore, the number of bits of the partial product becomes 39 bits by adding the correction bit. As shown in Table 2, the circuit scale and the calculation delay until the calculation result is output do not change with respect to the circuit of FIG.

The basic operation of the third embodiment of the present invention will be described with reference to FIG.

FIG. 3 shows a state in which an error amount due to the truncation of the least significant bit is corrected with respect to the above-mentioned first embodiment, and a 6-bit × 7-bit multiplier is connected in parallel. It consists of a diagram (a) showing the generation of partial products by the multiplication method, a diagram (b) showing the flow of bits, and a diagram (c) showing examples of correction values obtained according to the multipliers X, Y, and Z. . The correction bits P, Q, R and S are obtained from the multipliers X, Y and Z. Here, the values when correcting with 4 bits and 2 bits are shown. Since the correction bits Q, R, and S are obtained from the multiplier, they do not affect the operation delay. Further, the correction bit P is added together with the partial product, but the circuit scale is increased by 3 gates in the Wallace Tree circuit and only increased by several gates to obtain the correction value, and the operation delay remains unchanged.

Further, the correction bits P, Q, R and S can be arbitrarily given from the outside. The circuit scale at that time is an increment for a register or the like for giving an arbitrary value, and the operation delay is the same as the configuration of FIG.

FIG. 4 is a first embodiment of the transversal type equalizer according to the present invention. In this example, with 7 taps, the multiplier of each tap is 7 bits, the multiplicand is 6 bits, and the sum is added to obtain the output result. Further, TAP: C-1 and TAP: C + 1 always have the same multiplier. Here, the D flip-flop 12
3 and the value of the output of the D flip-flop 125 should be calculated using the values of the D flip-flop 122 and the D flip-flop 124 one clock before (addition)
Then, the result is multiplied by the data held in the D flip-flop 128. By doing so, since the circuit configurations after the multiplier can be made the same, the adaptation such as pipeline processing becomes easy. The partial product for three digits from the least significant bit side is not generated but is truncated and deleted, the sign is fixed, and the range is limited.

The setting range of the multiplier of each tap is only TAP: C-3 -1 / 4-1 [LSB] to 0 TAP: C-20 to + 1 / 2-1 [LSB] TAP: C0 +1. (Fixed value) TAP: C ± 1-1-1 [LSB] to 0 TAP: C + 2 0 to + 1 / 2-1 [LSB] TAP: C + 3 -1 / 4-1 [LSB] to 0. The tap C0 is fixed at only 1 time.
Therefore, the number of bits of the partial product of each tap is 18 bits, 24 bits, 6 bits, 36 bits, 24 bits, and 18 bits, respectively, as shown in FIG. 4, and the total including the correction value is 131 bits. Is.

The number of bits can be reduced by collectively calculating the correction value of each tap in advance to obtain the value. Here, as shown in FIG. 4, the entire size can be 5 bits.

The state of generation of the partial product of each tap in FIG.
This is as shown in FIG.

Table 3 shows the rounded-off value and correction amount of each tap. Here, the maximum value and the minimum value of the truncated values are halved, but the value of 64 [LSB] is corrected with 1 bit in consideration of the number of bits to be corrected. Therefore, the error is -42 to
It becomes +43 [LSB], which is reduced.

[0042]

[Table 3]

The circuit scale and the like according to this configuration are shown in Table 4 in comparison with the conventional configuration. The way to read the table is the same as in Tables 1 and 2. It can be seen that the circuit scale is reduced to about 50%, the operation delay is also reduced by 1 to 2 stages with a full adder, and high speed can be realized.

[0044]

[Table 4]

FIG. 6 shows a second embodiment of the transversal type equalizer according to the constitution of the present invention. Similar to the example of FIG. 4, with 7 taps, the multiplier of each tap is multiplied by 7 bits, and the multiplicand is multiplied by 6 bits. Further, TAP: C-1 and TAP: C + 1 always have the same multiplier. Here, the values of the outputs of the D flip-flop 153 and the D flip-flop 155 are to be calculated, and the values of the D flip-flop 152 and the D flip-flop 154 one clock before are calculated (added). The result is multiplied by the data held in the D flip-flop 158. The partial product for 3 digits from the least significant bit side is not generated and is truncated and deleted, the sign is fixed except the taps at both ends, and the range is also limited. The taps at both ends have sign bits, and bipolar coefficient values can be set, which is the only difference from FIG.

Therefore, the setting range of the multiplier of each tap is as follows: TAP: C-3 -1/4 to + 1 / 4-1 [LSB] TAP: C-20 to + 1 / 2-1 [LSB] TAP : C0 + 1 only (fixed value) TAP: C ± 1-1-1 [LSB] to 0 TAP: C + 20 to + 1 / 2-1 [LSB] TAP: C + 3 -1/4 to + 1 / 4- It is set to 1 [LSB]. The tap C0 is fixed at only 1 time.
Therefore, the bit numbers of only partial products of each tap are 24 bits, 24 bits, 6 bits, 36 bits, 24 bits, and 24 bits, respectively, as shown in FIG. 6, and the total including the correction value is 142 bits. Is.

Further, the correction value of each tap is collectively calculated in advance to obtain a value, so that the number of bits can be reduced. Here, as shown in FIG. 6, the whole can be 4 bits.

The state of generation of the partial product of each tap in FIG.
This is as shown in FIG. TAP: C-3 and TAP: C +
Since the partial product of 3 has a sign bit, the coefficient value is shifted to the left by 2 bits for multiplication, and the multiplication result is shifted to the right by 2 bits. By doing this, coefficient bit 1
This can be handled by increasing the number of bits only, and the circuit scale can be reduced.

Table 5 shows the rounded-off value of each tap and the correction amount. Here, the maximum value and the half value of the truncated value are intended to be corrected, but the value of 48 [LSB] is corrected with 2 bits in consideration of the number of bits to be corrected. Therefore, the error is -44 ~
It becomes +41 [LSB], which is reduced.

[0050]

[Table 5]

The circuit scale and the like according to this configuration are shown in Table 6. The way to read the table is the same as in Tables 1 and 2. As for the circuit scale, by giving the taps at both ends bipolar, the partial product is increased by 11 bits as compared with the configuration of FIG. 4, and the circuit scale of 81 gates is increased accordingly. The effect of circuit scale reduction is reduced. The calculation delay time is equivalent to that of the configuration shown in FIG. The breakdown of 81 gates for the circuit increase is 12 gates for generating partial products and 69 gates for adding partial products. According to Equation 1, if the partial product increases by 11 bits, 11 full adders are required. In this example, the partial product is 1
By increasing by 1 bit, it means that the number of full adders has increased by 11.5, which is in good agreement with the estimation by the equation 1.

[0052]

[Table 6]

FIG. 8 is a diagram for explaining the sum of products operation according to the present invention. In this example, a plurality of multiplication circuit portions 201 and 202 for obtaining partial products and an addition circuit unit 203 for adding bits of partial products generated therein are included. A Wallace Tree circuit is used for the adder circuit unit. The multiplication part has a multiplier of two circuits or more, and the multiplier and the multiplicand of each multiplier may not be related to each other like a transversal equalizer. Each multiplication circuit
The bits of the partial product are output, and the partial product is input to the addition circuit unit. Further, the multiplication circuit is configured so that the partial product on the least significant bit side is truncated and not output. Further, similar to the above-described configuration, the error components caused by the partial products being truncated and not output are collected and input to the adder circuit unit as correction bits.

As described above, by reducing the partial product on the least significant bit side due to multiplication, it is possible to realize high speed and small scale circuit.

[0055]

According to the present invention, it is possible to realize a digital multiplier, a digital transversal type equalizer, and a digital sum-of-products arithmetic circuit which can operate at high speed and are smaller in scale than conventional circuits. Further, the signal processing device to which the digital multiplier, the digital transversal type equalizer and the digital sum-of-products arithmetic circuit according to the present invention are applied can also cope with high speed operation.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a first configuration example according to the configuration of the present invention.

FIG. 2 is a diagram illustrating a second configuration example according to the configuration of the present invention.

FIG. 3 is a diagram illustrating a third configuration example according to the configuration of the present invention.

FIG. 4 is a diagram illustrating a first embodiment of a transversal type equalizer according to the configuration of the present invention.

FIG. 5 is a diagram showing how partial products with the configuration of FIG. 4 are generated.

FIG. 6 is a diagram illustrating a second embodiment of the transversal type equalizer according to the configuration of the present invention.

FIG. 7 is a diagram showing how partial products with the configuration of FIG. 6 are generated.

FIG. 8 is a diagram illustrating a configuration example of a product-sum calculation circuit according to the configuration of the present invention.

FIG. 9 is a diagram illustrating a configuration example (1) having a conventional configuration.

FIG. 10 is a diagram illustrating a configuration example (2) having a conventional configuration.

FIG. 11 is a diagram illustrating a partial product generation circuit according to a second-order Booth method.

FIG. 12 is a diagram illustrating a partial product generation circuit of a parallel multiplication method.

FIG. 13 is a diagram illustrating a configuration of an adder.

FIG. 14 is a diagram showing a configuration of an adder including an input “1”.

FIG. 15 is a diagram illustrating a transversal type equalizer having a conventional configuration.

[Explanation of symbols]

 121-128 D flip-flop 129 6-bit adder 131-132 Multiplier partial product generation circuit 134-137 Multiplier partial product generation circuit 138,168 Wallace Tree circuit 151-158 D flip-flop 159 6-bit adder 161- 162 Multiplier Partial Product Generation Circuit 164 to 167 Multiplier Partial Product Generation Circuit

Claims (9)

[Claims] 1. m bits × n bits (m and n are natural numbers)
In the multiplication of the digital data of, the product has a partial product generation circuit unit for generating a bit of the partial product and an addition circuit unit for adding the bits of the partial product.
A digital multiplier circuit using an ee circuit, wherein the partial product at least one digit from the least significant bit side of the partial product is discarded. 2. The digital multiplier according to claim 1, wherein an error caused by truncating the least significant bit side of the partial product is corrected. 3. A multi-tap digital transversal equalizer using a digital multiplication circuit for multiplying a digital data of a multiplicand and a multiplier, a partial product for generating a bit of a partial product of each tap. A digital transversal type equalizer using a Wallace Tree circuit as an addition circuit, which has a generation circuit unit and an addition circuit unit that collectively adds bits of the partial products, and at least from the least significant bit side of the partial products. A digital transversal type equalizer characterized by rounding down a partial product of the first digit. 4. The digital transversal type equalizer according to claim 3, wherein errors caused by truncating the least significant bit side of the partial product are collectively corrected. 5. The digital signal according to claim 3, wherein the sign (polarity) of the multiplier (coefficient value) of each tap is fixed so that the bit of the partial product generated by the operation of the sign bit is not generated. Transversal type equalizer. 6. The partial product generated according to claim 3, 4 or 5, wherein the setting range (dynamic range) of the multiplier (coefficient value) of each tap is made smaller (narrower) as it goes away from the center tap. A digital transversal type equalizer characterized by reducing the number of bits. 7. The tap data according to any one of claims 3 to 6, when the multipliers (coefficient values) of each tap always have the same multiplier (coefficient value). A digital transversal type equalizer characterized by adding and then multiplying. 8. A circuit for digital-signal processing, comprising a digital multiplication circuit and a digital addition circuit, and performing a sum-of-products operation for immediately performing an addition operation on the results of two or more multiplication operations. , A circuit using a multiplication method such as obtaining a partial product in multiplication, rounding down at least the first product from the least significant bit side,
A digital sum-of-products arithmetic circuit characterized by collectively adding partial products generated by multiplication. 9. The digital sum-of-products arithmetic circuit according to claim 8, wherein an error component generated by truncating the least significant bit side of the partial product is collectively corrected.