JP2000183753A - Signal converter and signal conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a signal converter to conduct high speed conversion suitable for real time processing and smooth nonlinear conversion with higher precision. SOLUTION: Comparatos 111, 112 and a computing element 120 discriminate to which of predetermined blocks an input signal belongs. According to the discrimination result, a parameter in a higher degree polynomial for each block stored in a storage means 200 is selected and outputted to an arithmetic section 300. The arithmetic section 300 uses the selected parameter to apply an arithmetic operation of the higher degree polynomial and calculates its output. In this case a quadratic polynomial (ax+b)x+c is employed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal converter, and more particularly, to a signal converter for performing non-linear conversion of a digital signal and a signal conversion method thereof.

[0002]

2. Description of the Related Art Among digital signal conversions, a conversion process called a non-linear conversion is used for various purposes such as gamma correction of an image signal and voltage conversion of a luminance value in a liquid crystal driving device.

Conventionally, in non-linear conversion of a digital signal, a one-to-one conversion for directly outputting an output value corresponding to an input value of an original signal from a storage unit which stores the output value corresponding to the input value of the original signal, A conversion using a first-order polygonal line has been used in which a parameter set having two elements a and b of a slope and an intercept is selected according to the input value of a signal, and these parameters are used as parameters for a linear operation of the original signal.
In addition, a method for realizing the non-linear conversion by a non-polynomial operation by using a division unit or a division operation routine, and a method for realizing by performing a recursive operation and obtaining an approximate value of the convergence value thereof have also been generalized.

[0004] One-to-one conversion will be described as a first conventional nonlinear conversion method. FIG. 8 is a diagram showing a configuration of a conventional signal conversion device that performs one-to-one conversion. The one-to-one conversion is
The relationship between the input value x and the output value y is a one-to-one direct conversion method. The output value is stored in a storage unit 51 called a ROM table.
It is written to 0. Usually, the storage unit 510 is a ROM
(Read Only Memory), and by connecting the bit line of the input value x to the address line of the ROM, the corresponding output value y obtained in advance is obtained.
Is output as the data value of the corresponding address in the ROM.

Next, as a second nonlinear conversion method, conversion using a primary polygonal line will be described. FIG. 9 is a diagram illustrating a configuration of a conventional signal conversion device that performs conversion using a primary broken line. Transformation using a first-order polygonal line is generally used recently. The signal converter using the primary polygonal line stores several parameters a and b in advance in a storage unit 540 including a ROM or the like, and selects one parameter set according to the range of the input value x. And linear operation

[0006]

## EQU1 ## ax + b (1) is applied, and this is set as an output value. LUT (L
(OK Up Table). Normal,
A number of comparators 521 equal to the number of ranges into which the input x is divided,
522, a simple arithmetic unit 530 for selecting a range, a storage unit 540, and a delay unit 55 for matching delay with a parameter.
1 and a multiplier 552 and an adder / subtractor 553. The magnitude of the input value x is determined by the comparators 521 and 522, and it is determined where the input value x falls within the divided range. The address of the storage unit 540 is specified according to the determination result output from the comparators 521 and 522, and the parameters a and b are obtained. Then, a linear operation is performed on the input x, and the result is output.

A conventional conversion method using a primary polygonal line will be described in detail. FIG. 10 is a diagram showing a conventional conversion method using a primary polygonal line. This method divides the range of input values into several parts and regards the relationship between the input and output of the divided range as approximately linear. Is the same as For example, if the input value x is a value between t1 and t2, the comparator compares x with t1 and t2, and x becomes t1 and t2.
2 and the parameters a and b of the first-order polygonal line 592 approximating the non-linear function 591 during this period.
Is output from the storage unit. From a, b and x, according to Equation 1,
An output value y is calculated.

[0008]

However, the conventional signal conversion apparatus has a problem that the operation amount or the circuit scale increases to improve the accuracy, and the efficiency deteriorates.

The first non-linear conversion method described above,
The 1 conversion has a problem that the conversion efficiency becomes worse as the bit length of the input value increases. If the bit length of the input value increases by one bit, both the address line and the data line of the ROM
The number of ROMs increases, and the capacity of the ROM becomes four times as large. That is, the problem of ROM cost increases exponentially. In addition, the input method and the output value
One-to-one correspondence is inefficient.

[0010] In the above-described conversion using the first-order polygonal line, which is the second non-linear conversion method, the non-linear function 591 is set to 1
In order to approximate with the next polygonal line 592 with high precision, it is necessary to make the section to be approximated linearly fine, that is, to divide the section into many. For this purpose, many comparators are required to determine the section of the input value, and there is a problem that the circuit scale becomes large. Also, the primary broken line 592
As shown in FIG. 10, since the output y cannot be changed smoothly before and after the division point of the input value x, there is a problem that the conversion is unnatural.

As other nonlinear conversion methods, there are methods using division and recursive operation. Both techniques can be expected to be accurate, but cannot be used in systems where the conversion speed and hardware scale are enormous, which imposes restrictions.

The present invention has been made in view of the above points, and an object of the present invention is to provide a signal conversion device and a signal conversion method for performing high-speed conversion suitable for real-time processing and smoother non-linear conversion with higher accuracy. Aim.

[0013]

According to the present invention, in order to solve the above-mentioned problems, in a signal conversion device for performing a nonlinear conversion of a digital signal, a high-order polynomial in which a source function of the nonlinear conversion is divided into predetermined sections and approximated. Storage means for storing the parameters for each of the predetermined sections; determination means for determining the predetermined section to which the input signal belongs; and the high-order polynomial parameter stored corresponding to the determined predetermined section. And a calculating means for performing a calculation on the input signal by using the signal converter.

In the signal conversion device having such a configuration, when an input signal is input, the determination unit determines which of the predetermined sections the input signal belongs to. According to the determination result, the parameters of the high-order polynomial for each section stored in the storage unit are selected. Subsequently, using the selected parameters, a high-order polynomial operation is performed on the input signal to calculate an output value.

Further, in the signal conversion method of the signal conversion device for performing the nonlinear conversion of the digital signal, the original function of the nonlinear conversion is divided into predetermined sections, and for each of the sections, the higher-order polynomial of the higher-order polynomial which approximates the original function in advance is defined. A step of storing a parameter, a step of determining which section the input signal belongs to in the predetermined section, a step of selecting the parameter stored in advance corresponding to the determined section, Performing a high-order polynomial operation on the input signal using the parameter to calculate an output value.

In the signal conversion method of such a procedure, the original function of the non-linear conversion is divided into predetermined sections, and parameters of a high-dimensional polynomial approximating the original function are stored for each section. When an input signal is input, a section to which the input signal belongs is determined, and parameters of a higher-order polynomial corresponding to the section are calculated.
Using these, a higher-order polynomial operation is performed to calculate an output value.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. First, a high-order polynomial for performing nonlinear conversion and its parameters will be described.

In actual non-linear conversion, there are often functions (exponential functions, etc.) that directly express the non-linear conversion, such as gamma correction of an image. A function expressing such a non-linear transformation is called an original function. In such a case, the original function will be approximated by some segmented polynomial. Then, in order to optimally (efficiently and accurately) approximate the original function, the number of polynomials in the order and the number of parameters (coefficients) of each of the divided polynomials is set as a problem. .

However, this is a parameter derivation method for approximating a nonlinear function with a high-order polynomial that is divided, and this method will not be described in detail in the present case. At least, if the degree of the polynomial and the dividing point for dividing the range of the input value are fixed in a sufficiently fine range, it is easy to approximate the dividing range with almost the same polynomial as the original function.

A specific example of a method for deriving parameters of a high-order polynomial for performing a non-linear conversion will be described. Here, the polynomial is a quadratic polynomial, the values at both ends of a certain range of the input value x are x1, x2, and x3 is the average of x1, x2. It is also assumed that the approximating quadratic polynomial intersects the original function f (x) at both ends of the segmented range and the midpoint thereof. At this time, the following equation holds for the original function f (x).

[0021]

F (x1) = ax1 ² + bx1 + c (2)

[0022]

F (x2) = ax2 ² + bx2 + c (3)

[0023]

F (x3) = ax3 ² + bx3 + c (4)

[0024]

X3 = (x1 + x2) / 2 (5) By solving these equations, a second-order polynomial can be obtained.

[0025]

Ax ² + bx + c (6) The parameters a, b, and c are determined. If the division range of the input value is made sufficiently small, the polynomial (Equation 6) becomes
1, x2] can be said to be an approximate function of the original function f (x).

In this way, it is possible to derive appropriate parameters of the higher-order polynomial. Therefore, in the following description, the parameters are assumed to be known. Next, a signal conversion device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram of a signal conversion device according to an embodiment of the present invention.

The signal conversion apparatus according to the present invention includes comparators 111 and 112 for determining a range to which an input value belongs, an arithmetic unit 120, a storage unit 200 for storing parameters of a high-order polynomial used for conversion, and a high-order polynomial operation. And an arithmetic unit 300 for performing the following. Comparators 111 and 112 and arithmetic unit 120
Determines whether the value of the input x belongs to a preset division range, and outputs the determination result to the storage unit 200.
The storage unit 200 stores a parameter of a higher-order polynomial determined in advance for each section, and stores a parameter corresponding to the section of the determination result input from the arithmetic unit 120 in the arithmetic unit 30.
Output to 0. The operation unit 300 stores the input x and the storage unit 20
A predetermined higher-order polynomial operation is performed using the parameters output by 0 to calculate an output y. Here, the arithmetic unit 300
Are multipliers 312 and 315 and adders / subtractors 313 and 316
And delay units 311, 314.

The details of each section will be described below. First, a comparator 111 that determines a section range to which an input value belongs,
The 112 and the computing unit 120 will be described. Comparator 11
1, 112 is required by the number of section ranges, that is, by one less than the number of parameter sets. Here, the number of sections is 3
Therefore, the number of comparators is two. The value to be compared with the original signal in the comparator is a value indicating a segment point, but it is not necessary to compare the minimum value and the maximum value of the original signal. Therefore, the number of comparators is one less than the number of sections. As described above, the comparators 111 and 112 provided according to the number of the division ranges compare the input x with the value of the division point and output the result to the arithmetic unit 120. Arithmetic unit 12
0 determines the classification range to which the input x belongs from the comparison results input from the comparators 111 and 112.

The operation of the comparators 111 and 112 and the operation unit 120 will be described. FIG. 2 is a diagram showing a relationship between an input and an output of the signal conversion device according to one embodiment of the present invention. A plurality of comparators 111 and 112 derive a section (section range) of the value to which the input x belongs. For example, as a result of comparing the input x with the first segment value (t1),

[0030]

If x <t1 (7), the input x belongs to the interval 1, and
Similarly, as a result of the comparison between x and t1 and t2,

[0031]

X ≧ t1 (8)

[0032]

If x <t2 (9), the input x belongs to the interval 2.
Also,

[0033]

If x ≧ t2 (10), the input belongs to section 3. These processes are performed by the comparators 111 and 112 and the arithmetic unit 1
The arithmetic unit 120 outputs to the storage device 200 a signal indicating the section to which the input x belongs.

Next, the storage section 200 will be described with reference to FIG. The storage unit 200 is configured by a ROM or the like, and stores a set of parameters a, b, and c as one set in advance by the number of sections. Arithmetic unit 1
The parameter sets a, b, and c corresponding to the section are output to the arithmetic unit 300 according to the signal indicating the section from 20.

Next, the operation section 300 will be described. Using the parameter set output from the storage unit 200 and the input x, the arithmetic unit 300 calculates an output y by a higher-order polynomial approximating the original function. The high-order polynomial calculation performed by the calculation unit 300 can take various forms depending on the use of the signal conversion device, such as the degree of the polynomial and the calculation method. The arithmetic unit 300 shown in FIG. 1 is a first arithmetic unit configuration example, and approximates a higher-order polynomial to a second-order polynomial;

[0036]

## EQU11 ## This is a configuration in the case of (ax + b) x + c (11). Arithmetic unit 300 includes delay units 311 and 31 for matching timing with parameters.
4, multipliers 312 and 315, and adders / subtractors 313 and 31
And 6. The operation of the arithmetic unit 300 will be described. The x input to the multiplier 312 with the timing matched with the parameter by the delay unit 311 is sent to the adder / subtractor 313 as ax, where ax + b is calculated. Based on the input x delayed by the delay unit 314 and the output of the adder / subtractor 313, (ax + b) x is calculated by the multiplier 315, and (ax + b) x + by the adder / subtractor 316.
c is calculated. Thus, the output y is calculated. If the multiplication and the addition / subtraction can each be processed in one clock, the delay unit 314 causes a delay corresponding to the sum of the two clocks.

Returning to FIG. FIG. 2 is a diagram showing a relationship between an input x and an output y of the signal conversion device. When signal conversion is performed using the high-order polynomial 400, the original function is more approximated than conventional conversion using a first-order polygonal line, so that a highly accurate output value can be obtained. The output y changes smoothly before and after the section point of the input x.

The feature of this signal converter using the equation 11 is that, for example, by setting the parameter a to 0, a linear equation can also be expressed, so that a highly general-purpose and general-purpose operation can be performed.

Some other examples of the operation section 300 will be described. First, a configuration example of the second arithmetic unit 300 using a second-order polynomial will be described. Delay device 3
11 is a timing for starting the calculation,
In the following description, it is omitted. FIG. 3 is a configuration example of a second arithmetic unit of the signal conversion device according to the embodiment of the present invention. In this case, a second-order polynomial is used as an approximate expression,

[0040]

(12) a (x + b) ² + c (12) is used. The other parts are the same as those described in FIG.
This is the same as the signal conversion device of the first configuration example. The second arithmetic unit 300 includes adders / subtractors 321 and 324 and a multiplier 322,
323. The input x becomes (x + b) by the adder / subtractor 321 that inputs the parameter b, and (x + b) ² is calculated by the multiplier 322. Subsequently, a (x + b) ^{2 is obtained} by the multiplier 323 for inputting the parameter a, and the adder / subtractor 324 for inputting the parameter c,
The result of the operation a (x + b) ² + c of Expression 12 is obtained. The feature of Expression 12 is that the word length of the input value is reduced by performing addition and subtraction first, and the amount of calculation in subsequent processing can be reduced, or the circuit size can be reduced.

Equation 12 may be configured as shown in FIG. FIG. 4 is a configuration example of a third arithmetic unit of the signal conversion device according to the embodiment of the present invention. This third computing unit 300
Is an adder / subtractor 33 that inputs an input x and a parameter b.
1. Multiplier 332 for inputting parameter a, multiplier 33
3. The calculation of Expression 12 is performed by sequentially passing through the adder / subtractor 334 for inputting the parameter c. In the third example of the operation unit, only the order of the adder / subtracter and the multiplier in the second example of the operation unit is changed.
If the operation word length is limited, the result may change.

Next, a fourth operation unit 3 using a third-order polynomial
A configuration example of 00 will be described. FIG. 5 is a configuration example of a fourth arithmetic unit of the signal conversion device according to the embodiment of the present invention. In the above description, the conversion using the second-order polynomial has been described. However, if the parameter set stored in the storage unit 200 shown in FIG. Transformation of degree polynomials is also possible. 3
As a degree polynomial:

[0043]

It is considered that ((ax + b) x + c) x + d (13) is appropriate. A configuration example of the fourth arithmetic unit 300 will be described. FIG. 5 is a configuration example of a fourth arithmetic unit of the signal conversion device according to the embodiment of the present invention. The fourth arithmetic unit 300 includes multipliers 341, 344, 346, adders / subtractors 342, 345, 348, and delayers 343, 34.
And 7. The input x becomes ax by the multiplier 341 that inputs the parameter a, and ax + b is calculated by the adder / subtractor 342 that inputs the parameter b. Subsequently, x timed by the delay unit 343 is output to the multiplier 34.
4 and (ax + b) x is calculated. The adder / subtractor 345 that inputs the parameter c adds c to calculate (ax + b) x + c, and multiplies this by x delayed by the delay unit 347 by the multiplier 346. Thus, ((ax + b) x + c) x is calculated. Next, the adder / subtractor 348 for inputting the parameter d obtains d.
Is added, and the operation ((ax + b) x + c) x +
d is performed.

By using the third-order polynomial, the degree of freedom of the conversion curve within one section is further increased as compared with the second-order polynomial.
As a result, the number of sections can be reduced. However, since the scale of the polynomial operation circuit part becomes large, it is necessary to determine the trade-off.

When a higher-order polynomial is realized, as can be seen by comparing the configuration of the second-order polynomial shown in FIG. 1 with the configuration of the third-order polynomial shown in FIG. It is only necessary to cascade as a set of containers. Therefore, a detailed description of a configuration example using a higher-order polynomial will be omitted.

Next, a description will be given of a configuration example of the fifth arithmetic unit 300 in which a shift register is provided immediately after the multiplier. FIG. 6 shows a fifth embodiment of the signal conversion apparatus according to the present invention.
Is a configuration example of the arithmetic unit 300. This is shown in FIG.
Multipliers 312, 315 of first configuration example using degree polynomial
, A shift register is added immediately after. FIG.
Is a diagram extracted from the arithmetic unit 300 in FIG. 1, and the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
Further, the delay unit 311 in FIG. 1 is omitted. The fifth arithmetic unit 300 includes a shift register 351 immediately after the multiplier 312, and a shift register 3 immediately after the multiplier 313.
52 are provided. Here, similar to the first configuration example,
The calculation (ax + b) x + c of Expression 11 is performed.

Generally, between parameters a, b, and c,

[0048]

A <b <c (14) holds, but if the shift registers 351 and 352 are not provided, all the least significant bits of the parameters a, b and c must be the same at the time of calculation. B,
In c, some lower digits become redundant bits. For this reason, the data in the storage unit for storing b and c not only increases redundantly, but also the adder / subtractor 313 that operates using b and c,
The cost of 316 also increases.

On the other hand, in the case of general non-linear conversion such as gamma correction, the word lengths of the input x and the output y are often equal. That is, no matter how many parameters a, b, and c are in the decimal place, the lower-order bits must be finally cut. In the multipliers 312 and 315, the sum of the bit lengths of the multiplier and the multiplicand is equal to the bit length of the multiplication result.

Based on these points, the multipliers 312, 31
Immediately after 5, shift registers 351 and 352 are provided. As a result, the lower digits are cut to some extent, and almost sufficient accuracy is preserved. The shift amount may be a right shift having a length substantially equal to the word length of the input x in a general configuration.

The right shift amounts of the shift registers 351 and 352 are s1 and s2, respectively, and the right shift operator is >>
In the formula, the processing performed by the fifth configuration example is as follows.

[0052]

Y = (((ax >> s1) + b) x >> s2) + c (15)

When actually realized by hardware,
The shift registers 351 and 352 may be configured only by wiring to the next stage, in which wiring is not performed to the next stage of the lower bits of the outputs of the multipliers 312 and 315, which are several bits to be cut. In addition, if the multipliers 312 and 315 themselves omit the operation circuit portion of the lower cut bits, the scale can be further reduced.

By providing the shift register immediately after the multiplier, not only the redundant word length of the multiplication result can be reduced, but also the redundant word length of the subsequent parameter can be reduced. As a result, the overall operation cost and the size of the parameter storage device can be greatly reduced while maintaining the accuracy of the polynomial operation.

Next, a description will be given of a configuration example of a sixth arithmetic unit 300 in which a rounding bit is added to a parameter in advance and a shift register is provided immediately after the adder / subtracter of the fifth configuration example described above. FIG. 7 is a configuration example of a sixth arithmetic unit 300 of the signal conversion device according to the embodiment of the present invention. This is because the adders / subtractors 313 and 31 of the fifth configuration example shown in FIG.
A shift register is added immediately after 6.

The sixth arithmetic unit 300 includes an adder / subtracter 31
3, a shift register 361 is provided, and the adder / subtracter 31
A shift register 362 is provided immediately after 6. Less than,
The operation of the arithmetic unit in the sixth configuration example of the above configuration will be described based on the most commonly performed rounding method. Normal rounding is performed by adding 1 to the most significant bit to be cut immediately before the shift registers 351 and 352 for cutting lower redundant bits. However, even if only 1 is added, a full adder having the same length as the bit length of the augend is required in consideration of carry, which is inefficient. Therefore, in the shift registers 351 and 352 that cut the lower redundant bits, the shift is intentionally performed with one redundant bit left.

On the other hand, for the parameters b and c in the adders / subtractors 313 and 316 at the next stage, values obtained by extending the least significant bit by 1 bit and adding 1 to the extension bit are stored in the storage unit 200 in advance. deep. When the left shift operator is represented by <<, the conversion expression for parameter preprocessing is

[0058]

B ′ = (b << 1) +1 (16)

[0059]

C ′ = (c << 1) +1 (17)

As a result, the adder / subtractor 31 is calculated using the parameters b ′ and c ′ previously converted by the equations (16) and (17).
When the addition and subtraction by 3, 316 are performed, the rounding process is performed simultaneously with the addition of the parameter. Lastly, the added shift registers 361 and 362 perform a right shift by one bit, thereby cutting off the rounded bits, thereby obtaining the original shift amount.

Similar to equation 15 showing the processing of the fifth configuration example described above, the processing of the fifth configuration example is expressed by the following equation.

[0062]

Y = (((((ax >>> s1 ') + b') >> 1) x >> s2 ') + c') >> 1 (18)

[0063]

S1 ′ = s1-1 (19)

[0064]

Here, s2 ′ = s2-1 (20) Here, an example of a rounding process carried out at a rate of 50%, in which 1 is added to the most significant bit to be cut and one bit right shift is performed. However, for example, there is also a rounding process in which 3 is added to the most significant 2 bits to be cut and a 2-bit right shift is performed, and the rounding process is carried out at a rate of 75%.

Regardless of the rounding process, FIG.
, The conversion equations (Equations 16 and 17) for the parameter pre-processing, and the shift registers 361 and 36
It can be dealt with simply by changing the shift amount of 2.

As described above, by providing a new shift register immediately after the adder / subtractor, the rounding process can be performed efficiently. Note that the above processing functions can be realized by a computer. In this case, the processing content of the function that the signal conversion device should have is described in a program recorded on a computer-readable recording medium. Then, by executing this program on a computer, the above processing is realized on the computer. As a computer-readable recording medium,
There are a magnetic recording device and a semiconductor memory. When distributing to the market, CD-ROM (Compact Disc Read Only Me
mory) or a floppy (registered trademark) disk or the like to store and distribute the program, or store the program in a storage device of a computer connected via a network, and transfer the program to another computer via the network. You can also. When running on a computer,
The program is stored in a hard disk device or the like in the computer, loaded into the main memory and executed.

[0067]

As described above, according to the present invention, it is determined to which of the predetermined sections the input signal belongs, and according to the determination result, the high-order polynomial for each section stored in the storage means. Select the parameter of. Then, using the selected parameters, a high-order polynomial operation is performed on the input signal to calculate an output value. As described above, since the nonlinear original function is approximated by a higher-order polynomial, it is possible to perform smoother nonlinear conversion with higher accuracy. In addition, since a section is determined, a parameter determined in advance for each section is selected and an output value is calculated, the time required for processing is short, and high-speed conversion suitable for real-time processing can be performed.

In the signal conversion method of the present invention, the original function is divided into sections, and the parameters of the high-dimensional polynomial approximating the original function are stored for each section. When an input signal is input, a section to which the input signal belongs is determined, parameters of the section are calculated, and a higher-order polynomial operation is performed using these to calculate an output value. As described above, since the nonlinear original function is approximated by a higher-order polynomial, it is possible to perform smoother nonlinear conversion with higher accuracy. In addition, since a section is determined, a parameter determined in advance for each section is selected and an output value is calculated, the time required for processing is short, and high-speed conversion suitable for real-time processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal conversion device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an input value and an output value of the signal conversion device according to one embodiment of the present invention.

FIG. 3 is a configuration example of a second calculation unit of the signal conversion device according to the embodiment of the present invention;

FIG. 4 is a configuration example of a third arithmetic unit of the signal conversion device according to the embodiment of the present invention;

FIG. 5 is a configuration example of a fourth arithmetic unit of the signal conversion device according to the embodiment of the present invention;

FIG. 6 is a configuration example of a fifth arithmetic unit of the signal conversion device according to the embodiment of the present invention;

FIG. 7 is a configuration example of a sixth arithmetic unit of the signal conversion device according to the embodiment of the present invention;

FIG. 8 is a diagram showing a configuration of a conventional signal conversion device that performs one-to-one conversion.

FIG. 9 is a diagram showing a configuration of a conventional signal conversion device that performs conversion using a primary broken line.

FIG. 10 is a diagram showing a conventional conversion method using a primary polygonal line.

[Explanation of symbols]

111, 112 comparator, 120 arithmetic unit, 200 storage unit, 300 arithmetic unit, 311, 314 delay unit, 31
2, 315: multiplier, 313, 316: adder / subtractor, 40
0: High-order polynomial

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5B057 CA08 CB08 CD11 CH01 CH08 CH11 DA17 DB09 DC22 5C021 PA42 PA52 PA72 PA78 PA89 XA34 YC03 YC08 5J064 AA02 BA12 BC01 BC03 BC08 BC09 BD03

Claims (10)

[Claims] 1. A signal conversion device for performing a non-linear conversion of a digital signal, a storage means for storing, for each of the predetermined intervals, a parameter of a high-order polynomial approximating an original function of the non-linear conversion by dividing the original function into predetermined intervals, Determining means for determining the predetermined section to which the input signal belongs; and calculating means for performing an operation on the input signal using the higher-order polynomial parameter stored corresponding to the determined predetermined section. A signal conversion device characterized by the above-mentioned. 2. The computer according to claim 1, wherein the determining unit compares an input value with an end value of the segmented range in the predetermined section, and a calculator that calculates a section to which the input value belongs based on an output of the comparator. The signal conversion device according to claim 1, wherein the signal conversion device is configured. 3. The signal conversion device according to claim 1, wherein said operation means is an operation circuit in which a multiplier, an adder / subtracter, and a delay unit are combined. 4. The signal conversion device according to claim 3, wherein said operation means further includes a shift register immediately after said multiplier. 5. The signal conversion device according to claim 4, wherein said operation means further includes a shift register immediately after said adder / subtracter. 6. The storage means stores parameters a, b, and c of a second-order polynomial for each of the sections, and the calculation means performs (ax + b) x + c on an input x. The signal conversion device according to claim 1, wherein: 7. The storage means stores parameters a, b, and c of a quadratic polynomial for each of the sections, and the calculation means calculates a (x + b) ² + c for an input x. The signal conversion device according to claim 1, wherein the signal conversion is performed. 8. The storage means stores parameters a, b, c, and d of a cubic polynomial for each section, and the calculation means calculates ((ax + b) x + c) x + d The signal conversion device according to claim 1, wherein the calculation is performed. 9. A signal conversion method for a signal conversion device for performing a non-linear conversion of a digital signal, comprising: dividing an original function of the non-linear conversion into predetermined sections; Storing a parameter, determining which section the input signal belongs to in the predetermined section, selecting the parameter stored in advance corresponding to the determined section, Performing a higher-order polynomial operation on the input signal using the parameter to calculate an output value. 10. A computer-readable recording medium on which a signal conversion program for performing a non-linear conversion of a digital signal is recorded, wherein a non-linear conversion source function is divided into predetermined sections, and the source functions are approximated in advance for each section. Storing a parameter of a higher-order polynomial; determining which section the input signal belongs to in the predetermined section; selecting the parameter stored in advance corresponding to the determined section A computer-readable recording medium recording a program for causing a computer to execute the following steps: a step of performing a higher-order polynomial operation on the input signal using the parameter to calculate an output value.