JP2821406B2 - Product-sum operation unit and digital filter circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multiply-accumulate unit,
In particular, the present invention relates to a product-sum calculator used in a digital signal processor (DSP) and the like.

[0002]

2. Description of the Related Art This type of sum-of-products arithmetic unit is widely used for performing a fast Fourier transform using a DSP and an accumulation operation for generating a digital filter. In the conventional product-sum operation unit, when the multiplication result is input to the adder due to accumulation or the like,
In order to match the word length of each of the data of the adder with the result of the multiplication, a rounding process is performed in which the lower-order bit string of the multiplication result that protrudes from the data length of the adder is truncated.

Referring to FIG. 5A, which shows a block diagram of a general conventional first product-sum operation unit, this conventional first product-sum operation unit multiplies a multiplier A by a multiplicand B and performs multiplication. Multiplier 1 for outputting result M, multiplier register 2 for storing multiplier A and multiplicand B respectively, multiplicand 3, and multiplication result register for buffer for temporarily storing multiplication result M and outputting rounded addend data UM 101, an adder 6 for accumulating the addend data UM and outputting an addition result AD, and an addition result register 9 for storing the addition result AD.

[0004] Next, referring to FIG.
The multiplier 1 receives supply of the multiplier A and the multiplicand B from each of the registers 2 and 3 and executes a predetermined multiplication.
01 is stored. The adder 6 receives, from the multiplication result register 101, a higher-order bit string having the same data length as that of the adder, that is, the addend data UM, and adds the output data AA of the addition result register 9 to the new addition data AD.
Is stored in the addition result register 9. On the other hand, among the multiplication results M stored in the multiplication result register 101, the addend data U
Lower bit strings LM lower than M are discarded.

However, in the conventional method of calculating the first product-sum adder, the truncation error included in the addend data UM is always distributed in the negative direction. There has been a problem that the accumulation becomes extremely large.

[0006] To solve this problem, an attempt to reduce the accumulated error has been disclosed. For example, the conventional second device described in Japanese Patent Application Laid-Open No. Sho 62-216072.
Has a buffer that holds a part of the bit string that becomes a truncation error, and accumulates it separately by an adder to substitute the carry generated at the time of carry up into the product-sum operation, Carry-up addition is performed.

Referring to FIG. 5B, which shows the second conventional product-sum operation unit in common with FIG. 5A by using the same components as those in FIG. Are different from the first sum-of-products arithmetic unit in that a multiplication result register 102 having a buffer 111 for holding a part of the lower bit string LM to be truncated in the multiplication result M and a bit string Lm are accumulated. And an adder 103 for supplying the carry C generated at the time of carry-up to the adder 6.

Thus, in the second conventional product-sum operation unit, a product-sum operation in which the accumulation of truncation errors is reduced can be obtained without increasing the data word lengths of the internal bus, the intermediate data buffer, and the adder. Can be

As described above, it is generally known that this type of product-sum operation unit is applied to an integration process in a filter circuit using digital signal processing, that is, a digital filter circuit, by applying its function.

Referring to FIG. 4B, which shows a signal flow of a general digital filter circuit, the signal flow includes a multiplication 201, an addition 202, and a one-time delay 20.
3, the addition 202 and the temporary delay 203 constitute an accumulation loop. This type of digital filter circuit often performs a product-sum operation that is theoretically infinite, not within a limited time, but actually continues until the circuit starts and stops. Here, there is a problem that the truncation error is accumulated in the addition result and appears as a nonnegligible error in the result of the product-sum operation.

[0011]

The above-mentioned first product-sum operation unit of the prior art has the following problems. To avoid an increase in the circuit scale and not to attach importance to the operation accuracy exceeding the resolution of the input data, Since the input addend data word length is shorter than the result of the multiplication, the rounding process for cutting off the lower bit string of the multiplication result generates the addend data whose word length is adjusted by the rounding process, so that a truncation error occurs. Since the truncation error in the binary operation always has a negative polarity irrespective of the sign of the data, the product-sum operation has a disadvantage that the greater the number of repetitions, the larger the truncation error is accumulated.

Also, the conventional second sum-of-products arithmetic unit designed to improve this problem has a drawback that the truncation error is largely accumulated as the number of times of the sum-of-products operation is increased since the polarity of the truncation error does not change. Was.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a product-sum calculator that eliminates an error generated during execution of a product-sum operation and is biased to a certain polarity, and that performs a product-sum operation with high accuracy.

[0014]

According to the present invention, a multiply-accumulate unit according to the present invention comprises:
A multiplier that multiplies the multiplier by the multiplicand and outputs a multiplication result;
A product-sum operation comprising: an adder that adds a predetermined higher-order bit string of the multiplication result as an addend, adds the previous addition result as an augend, and outputs a cumulative addition result, and an addition result register that holds the cumulative addition result An adder for supplying the most significant bit of a lower bit string to be truncated except for the upper bit string of the multiplication result, wherein the adder responds to the supply of the most significant bit to supply the most significant bit. It is characterized in that carry addition is performed using the upper bit as a carry signal.

[0015]

FIG. 4 shows an embodiment of the present invention.
Referring to FIG. 1, in which the same components as those in FIG. 1A are denoted by the same characters and similarly denoted by blocks, the product-sum operation unit according to the present embodiment shown in FIG. , A multiplier register 2, a multiplicand register 3, an adder 6, and an addition result register 9, an upper register 4 for a buffer for temporarily storing an upper bit string of the multiplication result M, that is, the addend data UM, A lower register 5 for storing the lower bit string data LM, a flag register 7 for holding the carry flag F updated by the execution of the addition until the immediately following addition, and a register 5 in response to the value of the selection state signal S. A multiplexer 8 for selecting either the most significant bit MB of the held lower bit string data LM or the carry flag F and supplying it as a carry bit C to the adder 6. That. The adder 6 has a function of simultaneously adding carry bits C, that is, carry-up addition at the time of addition, similarly to the adder 6 of the second conventional product-sum operation unit, which is a general numerical operation unit.

Next, the operation of this embodiment will be described with reference to FIG. 1. For convenience of explanation, the selection state signal S is "1", and the most significant bit of the lower register 5 is input to the multiplexer 8 as an input thereto. It is assumed that an instruction has been given to select an MB and output it as carry bit C.
First, the multiplier 1 receives a supply of the multiplier A and the multiplicand B from each of the registers 2 and 3 and executes a predetermined multiplication. The higher bit sequence of the multiplication result M, that is, the addend data UM is stored in the upper register 4 in the lower bit sequence LM. Is transferred and stored in the lower register 5 respectively. Next, the addend data UM is supplied from the upper register 4 and the addend AA is supplied to the adder 6 from the addition result register 9. The adder 6 calculates the addend AA and the addend data U
Add M and carry bit C. This addition result AD
Is transferred to the addition result register 9 to end one product-sum operation. The most significant bit MB, that is, carry bit C
Since the probability of 1 'is 0.5, the probability of carry addition by carry bit C is also 0.5.

When the selection state signal S is "0", the multiplexer 8 selects the carry flag F and supplies it as the carry bit C, so that the operation is the same as that of the conventional product-sum adder.

Referring to FIGS. 2A and 2B showing the distribution of errors accumulated for one product-sum operation, the accumulated error per operation is obtained by adding the weight of the least significant bit of the addition result AD to 1 ,
Assuming that the number of bits to be truncated is n and the error is e, (A)
In the case where the operation by the conventional first product-sum operation unit shown in FIG.
When the carry-add operation is performed using the product-sum operation unit of this embodiment with respect to 2 ⁻ⁿ ) ≦ e ≦ 0, as shown in FIG.
(0.5-2- ⁿ ) /2≦e≦0.5. As described above, the error that has conventionally been distributed only in the negative direction is now distributed in the positive and negative directions, and the average of the error accumulated per product-sum operation is-(1-2) when the carry addition is not performed.
^-n ) / 2, when carry addition is performed, 2- ^{(n + 1)}
Becomes

Therefore, if the difference between the word length of the addend data, which is the higher-order bit string of the multiplication result, and the word length of the entire multiplication result is 2 bits or more, the effect of reducing the accumulated error can be obtained.

As an example, if the multiply-accumulate unit is composed of a multiplier of 16 bits as the multiplier and the multiplicand, a multiplier of 31 bits of the multiplication result output and an adder of 16 bits of the input, the number of truncated bits is 15 bits, and average error per product-sum operation one case without increasing addition - and (1-2 ^-15) / mean error 2 ^-16 in the case of performing the carry adder 2 to the product-sum operation unit of the present invention It can be greatly reduced to about 6 / 100,000 in the past.

Next, referring to FIG. 3, which shows the second embodiment of the present invention in the same manner as in FIG. The difference from the first embodiment is that a selection state signal register 10 for holding a selection state signal S is further provided.

As a result, the selection state signal S once supplied is held until a new selection state signal S is supplied again, and the held state signal S is continuously supplied to the multiplexer 8.

Next, referring to FIG. 4A, which shows a block diagram of a digital filter according to a third embodiment of the present invention, this digital filter is a product-sum calculator 2 of the present invention.
1, an instruction ROM 22 for storing an instruction code for designating execution of operation, input / output and transfer of data, and an instruction decoder 23 for decoding the contents of the instruction ROM 22 into control signals. A data RAM 24 for storing data in accordance with a control signal, and a data ROM 2 for storing constants mainly used for filter coefficients and the like.
5 and an internal data bus 26 which is a signal path used for data transfer inside the device.

Referring to FIG. 4B, which shows the signal flow of the digital filter according to the present embodiment, the signal flow includes a multiplication 201, an addition 202, and a one-time delay of two.
03, and the addition 202 and the temporary delay 203 form an accumulation loop.

The product-sum operation unit 21 uses the data input from the data ROM 25, the data RAM 24 and the internal data bus 26 in accordance with the control signal supplied from the instruction decoder 23, and corresponds to the signal flow of FIG. Perform the operation.

Thus, a digital filter having desired characteristics can be realized.

[0027]

As described above, the multiply-accumulate unit according to the present invention includes the most significant bit supply means for supplying the most significant bit of the lower bit string to be truncated, and carries the most significant bit as a carry bit. By performing the addition, the errors are evenly distributed in the positive and negative directions, so that the accumulated error due to the repetitive calculation can be greatly reduced, and there is an effect that an accurate calculation result can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of a product-sum operation unit according to the present invention.

FIG. 2 is an explanatory diagram showing an error in the product-sum operation unit of the present embodiment and a conventional truncation error.

FIG. 3 is a block diagram showing a second embodiment of the product-sum operation unit of the present invention.

FIG. 4 is a block diagram and a signal flow diagram showing a digital filter according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing an example of first and second conventional product-sum calculators, respectively.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Multiplier register 3 Multiplicand register 4 Upper register 5 Lower register 7 Flag register 9 Addition result register 6 Adder 8 Multiplexer 10 Selection state signal register 21 Multiply-accumulator 22 Instruction ROM 23 Instruction decoder 24 Data RAM 25 Data ROM 26 Internal data bus 101, 102 Multiplication result register

Continued on the front page (58) Fields investigated (Int.Cl. ⁶ , DB name) G06F 17/10 H03H 17/02 681 H03H 17/06 641 H03H 17/06 655 JICST file (JOIS)

Claims (4)

(57) [Claims] 1. A multiplier for multiplying a multiplier and a multiplicand to output a multiplication result, and adding a predetermined upper bit sequence of the multiplication result as an addend and adding a previous addition result as an addend and outputting a cumulative addition result. And an addition result register for holding the cumulative addition result, wherein the most significant bit supply for supplying the most significant bit of the lower bit string to be truncated excluding the upper bit string of the multiplication result Means, wherein the adder performs carry addition using the most significant bit as a carry signal in response to the supply of the most significant bit. 2. An apparatus according to claim 1, wherein said most significant bit supply means includes a most significant bit register for holding said most significant bit, and a most significant bit and a carry flag output from said adder in response to a selection control signal. 2. The multiply-accumulate operation unit according to claim 1, further comprising: a multiplexer that selectively supplies one of the carry signals as the carry signal to the adder. 3. The sum-of-products arithmetic unit according to claim 2, further comprising a selection signal register for holding the selection control signal. 4. An instruction ROM for storing an instruction code for designating execution of operation, input / output and transfer of data, an instruction decoder for decoding the contents of the instruction ROM into a control signal, and storing data according to the control signal. R to perform
AM, a data ROM for storing constants, the data ROM and data R according to the control signal.
A digital filter circuit comprising: the product-sum operation unit according to claim 1 for performing an operation corresponding to each of a predetermined signal flow using AM and external input data.