JPS6285333A - Round-off processing system for floating point multiplier - Google Patents

Abstract

PURPOSE:To realize the multiplication time at a high speed, and to reduce the quantity of a hardware by utilizing a fact that a mantissa multiplication cell of a floating point multiplier has a multiplying function and a partial product adding function, and making a partial product adding part contain a round- off processing use addition. CONSTITUTION:In case of executing a round-off processing, when a logic 1 is inputted to a round-off data input terminal MD, a round-off data is also added at the time of addition of a multiplication cell 12, and results of multiplication PS, P6-P1 are outputted. The result of multiplication which is obtained in such a way is shifted, in case a normalized shift exists, upper 4 bits are fetched and the result of operation of a final mantissa is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a parallel multiplier using a floating point arithmetic method in digital signal processing. Technology) Figure 3 shows a functional block diagram of a conventional floating-point arithmetic system. In the figure, normalized input data X and normalized input data Y are input to a calculation unit 1. The calculation unit 1 performs floating-point calculations, such as addition, subtraction, and multiplication. The calculation results are normalized by the normalization processing section 2 as necessary. The output of the normalization processing unit 2 is sent to the rounding processing unit 3.
After rounding, the final calculation result Z is output.

In this way, calculation section 1 → normalization processing section 2 → rounding processing section 3
In this processing sequence, the Si calculation result of calculation unit 1 is within the normalized data range of the mantissa (in binary representation, if KZ is the mantissa of Z, then KZ<1°-1 Kz(--) The decision was made from the perspective that accurate rounding cannot be performed unless a normalization operation is performed to ensure that the data is normalized. ,v0132
7. October 10, 1983, p129-152:
Self 1V1. has been done.

The rounding processing method of the conventional floating-point multiplier shown in the above-mentioned document will be explained based on the blow/roll diagram of FIG. If the mantissa parts of normalized input data X and Y are KX and KY, respectively, and the exponent parts are EX and EY, then KX and KY are input to the mantissa multiplication circuit 5■, and the mantissa parts are multiplied to obtain KX.・KY=KK is output, while EX and EY are input to the exponent part addition circuit 52 to perform addition of the exponent parts, and E
Outputs X+EY=EE. When the calculation results KK and EE are input to the normalization processing circuit 53 and converted into normalized floating point data, they become a mantissa part KS and an exponent part ES. The next rounding processing circuit 54 has the normalized processing outputs KS and ES.
is input, and the mantissa rounding data KM is further input, and the mantissa rounding operation KS+KM=KZ is performed. Note: If the exponent part is corrected in the rounding operation, the rounding result of the exponent part is converted to EX and output.

For example, consider the case where the multiplication data is a signed binary number with a mantissa part of 5 bits and an exponent part of 3 bits.

-Example Toshite, KX, EX, KY, EY are as follows.

KX=01010, EY=000 (decimal number
tX=o, 625 x 2°) and Y=01001,
EY=001 (Y=0.5625X in decimal
2') First, by performing these multiplications, KK=KXXKY=001011010, EE=0
01 (0J515625 x 2' in decimal)
becomes. Since the mantissa is outside the normalization range, K S = 01.0110100, E S =
A normalization operation is performed to set the value to 000 (0.703125 in decimal). Furthermore, if the number of output data bits of the mantissa part is rounded to match the number of input data bits, then M = 0000010 f
6'knee'1''9゛.1,1T, S on the hood
= 010110100 K M = 000001 ■ Rounding down KZ=01011, EZ=ES, and eventually output as KZ=01011, EZ=000 (0.6875 in decimal).

(Problem to be Solved by the Invention) However, in the conventional method described in Section 2, the θi calculation processing content of the /7 dynamic point multiplier is fixed in the sequence of multiplication → normalization → rounding, so the final The overall calculation processing time to obtain the multiplier output becomes long, and when the multiplier is configured in the pipeline processing method as described in the above-mentioned document, the processing per stage of the Vibler rn is completed. First, it has a multi-stage vibe line configuration, and there is a problem that the number of hearts in the adder circuit of the rounding and 11 arithmetic section is large.

Therefore, the present invention solves these problems and performs rounding operations with a precision sufficient for practical use, thereby shortening calculation processing time and reducing the amount of hardware required for floating-point multiplier rounding. The purpose is to provide a method.

(Means for Solving the Problems) The present invention is a multiplier that performs parallel multiplication on a multiplier and a multiplicand that are displayed in floating point numbers, and in which a multiplication cell that multiplies mantissa data is The target is a multiplier that is configured with multiple stages based on the number of bits in the mantissa.

The present invention is constructed by inputting rounded data to any of the multiplication cells at rounding designated bit positions when there is a normalization shift for the output of this multiplier.

(Operation) The multiplier that is the object of the present invention calculates a partial sum by adding the multiplication of the multiplier and the multiplicand and the carry from the lower order, and sends the carry to the next stage (this operation depends on each multiplication cell). ) The operational assumptions are repeated and operated.

In this case, according to the present invention, rounding data is input to one of the multiplication cells at the rounding designated bit position when there is a normalization shift for the output of this multiplier, so rounding is performed when calculating the partial sum. Data is added. In other words, the rounding operation is absorbed into the addition function of the multiplication cell. The operation result outputted from the multiplier in this manner is normalized, and finally rounded normalized data is obtained.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. This figure shows a parallel multiplier that can be used for signed binary 4-bit data, where the mantissa parts of input data X and Y are as shown below.

X→X, X3

It is required as.

In the figure, reference numbers IO to 29 are multiplication cells, respectively. Each multiplication cell is connected to an AND circuit 40 as shown in FIG.
and a full adder 41. In the figure, k is the partial sum, C
2 is a carry input, co is a carry output, and S is a sum output. This multiplication cell performs an operation of +cH on S=x·y+.

Normally, in a multiplier with such a configuration, the multiplication result P
If there is a normalization shift for
2t+) is obtained as follows.

Multiplication result p, p6p5p4p3p2p.

With normalization shift P, P5P4P3P2P, O-, 7↓
Self 4t3t2t.

* * No normalization shift '-PePsP4P3PzP+=ts
tetst4t3t2t+.

* * *: Output bit part Here, conventionally, rounding processing was performed in which addition processing was performed on the bit position t3 determined after the above normalization processing, and the multiplication result was adjusted to the number of bits of the input data, which was 4. It was being done.

The rounding process according to this embodiment corresponding to this rounding process is performed as follows. In FIG. 1, the rounding designation bit t3 when there is a normalization shift, that is, the terminal MD to which the partial sum k of the multiplication cell 12 at the top of the column of P2 (corresponding to the second least significant bit of the multiplication output LSB) is input. Let be the rounding data input terminal. When rounding is to be performed, a logic 1 is input to the rounding data input terminal MD. Therefore, when rounding is performed, rounded data is also added at the time of addition in the multiplication cell 12. In other words, the rounding process is absorbed into the multiplier operation. Therefore, the multiplication result p when logic “1” is input to the rounding data input terminal MD,
p6p5p4p3p2p is output after the rounding operation has already been performed. The multiplication result obtained in this way is shifted if there is a normalization shift (P
-P6P4P3P2P, O), of which the upper 4 bits are extracted to obtain the final mantissa calculation result.

Here, unlike the conventional case, in this embodiment, the rounding operation is performed before knowing the multiplication result, that is, before the value of bit position t3 is determined in the above example, so the final mantissa operation is There is some deterioration in accuracy in the results.

Table 1 shows the amount added during rounding to bit position t4 when there is a normalization shift for the multiplication result P, and Table 2 shows the bit position when there is no normalization shift for the multiplication result P. The amount added to t4 during rounding processing is shown. In these tables, A indicates the conventional rounding process, B indicates the rounding process of this embodiment, and C indicates the rounding process (corresponding to the rounding amount "0").

(Leaving space below) Table 1 Table 2 First, when there is a normalization shift shown in Table 1, the difference between this embodiment B and the conventional method A is the probability that the data content is divided into 0 and 1 (- ) and t3=i.

The difference from the case where 1=0 is as follows.

Example B: l/4x 1/2x 100=1
2.5 (%) Similarly, in the case of rounding down, C is rounded down: l/2X l/2x 1oo=25
．． 0 (%) On the other hand, the percentage difference from conventional method A when there is no normalization shift for the multiplication result is as follows: Example B: o (%) Rounding down C:
1/2X 1/2x 100=25 (%). Therefore, if we add up both cases, the total number of adders is 12.5% smaller in B than A, and 50% smaller in C. Therefore, the effect of rounding processing on the accumulation of errors in finite word length calculations is 12.
It can be said that a variation of only about 5% is considerably improved over the 50% variation in the case of truncation without further rounding. Also, this fluctuation ff112.5%
For, if the word length of the mantissa is made long enough, the actual downstream,
If it doesn't become a problem, I'll say M''.

In the embodiments described above, the data width is applied to an array-type multiplication configuration with a length of 4 bits, but it is also possible to apply it to cases where the data width becomes larger, such as 8 bits, 16 bits, 32 bits, etc., or to other multiplication configurations. It is clear that the rounding method of the present invention is a behavior even when a method such as the Booth algorithm method is adopted.

(Effects of the Invention) As described above, according to the present invention, by utilizing the fact that the mantissa multiplication cell of the floating-point multiplier has a multiplication function and a partial product addition function, the partial product addition is performed. Since the rounding addition is included in the part that performs the calculation, it is expected that the multiplication time will be faster. Furthermore, since the rounding process (addition circuit for V) which was conventionally necessary can be omitted, there is an advantage that the floating point multiplier can be made smaller and more economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a specific configuration of a multiplication cell, FIG. 3 is a functional block diagram of a conventional floating-point operation, and FIG. 4 is a block diagram of a conventional floating-point operation. FIG. 2 is a diagram illustrating a configuration example of a floating-point multiplier. IO~29-...Multiplication cell, 40...AND circuit,
41...Full adder.

Claims (1)

[Scope of Claim] A multiplier that performs parallel multiplication on a multiplier and a multiplicand expressed in floating point numbers, the multiplier having a plurality of multiplication cells that perform multiplication of mantissa data based on the number of bits of the multiplier mantissa and the multiplicand mantissa. A floating-point multiplier rounding process characterized in that, in a multiplier configured in stages, rounding data is input to one of the multiplication cells at a rounding designated bit position when there is a normalization shift for the output of the multiplier. method.