KR20040033198A - Floating point with multiply-add unit - Google Patents

Abstract

PURPOSE: A floating point MAU(Multiply-Add Unit) is provided to reduce a chip scale and enhance an operation speed by using a Booth algorithm for processing an operation at two cycles when a multiplier of the longest operation time among the 3 step pipelines of an operator is processed as an unsigned number in order to perform a floating point 'A*B+C' operation by a single instruction. CONSTITUTION: The multiplying part decides multiplication of A and C, and arranges a mantissa of B in order to add the multiplication. An adding part adds the multiplication and the mantissa. A normalizing part performs the first 0 or first 1/0 anticipation in order to normalize an adding result, and normalizes or rounds the result, or detects an overflow or underflow exception. The multiplying part comprises a multiplier(110) and an arranger(120). The multiplier comprises a partial multiplication generator(112), an adding tree tool(114), and a carry hold adder(116).

Description

Floating Point Multiplication and Accumulation Units {FLOATING POINT WITH MULTIPLY-ADD UNIT}

The present invention relates to a floating point multiply and accumulator, and more particularly, to perform an A * C + B operation of a floating point with a single instruction. The present invention relates to a floating-point multiply and accumulator that uses a booth algorithm to reduce the size of the chip and improves the computation speed so that the operation can be performed in two cycles during processing.

Floating point units are commonly used in graphic accelerators, digital signal processors, and computers requiring high performance.

In recent years, as the integration of chips increases due to the development of semiconductor technology, floating point arithmetic units have emerged as an important element of the main arithmetic unit by allowing a floating point arithmetic unit to be embedded in a chip together with a central processing unit. . When the floating point arithmetic unit is built in the central processing unit, only the basic arithmetic units such as addition / subtraction and multiplication are built in because of the area occupied by the floating point arithmetic unit. Therefore, the floating point multiplier greatly affects the overall floating point arithmetic.

On the other hand, in the floating point multiplication operation, the mantissa processing is performed in the order of first, multiplication, addition, normalization, and rounding of the carry and sum generated in the multiplication process. Second, it consists of four processes: multiplication, addition, rounding, and normalization.

In the IEEE-754 standard for binary representation of floating point numbers for performing the above process, there are a single precision format of 32 bits and a double precision format of 64 bits. The single-precision format includes a 1-bit sign bit, an 8-bit exponent part, and a 23-bit mantissa part. The double-precision format includes a 1-bit sign bit, an 11-bit exponent, and a 52-bit mantissa. Here, the normalized operand A according to the IEEE standard can be expressed by the following equation.

Where S: sign, M: mantissa, and E: exponent.

Where s is the sign bit for the mantissa, M is the mantissa in the form of an absolute value, and E is the exponent in the form of a bias. The normalized form of the mantissa part is called a hidden bit because the most significant bit (MSB) is 1, and the MSB is omitted in the floating point representation.

A common floating point multiply and accumulator (MAC) combines three values A, B and C by adding or subtracting one value B from the product of the other values A and C. An arithmetic circuit with a multiplier and an adder can perform these MAC operations in separate steps, multiplying the values A and C using a multiplier, rounding the result, and then using the adder to multiply the result of the multiplication. The value B is added or the value C is subtracted from the result of the multiplication.

Optionally, a fused MAC device performs multiplication and accumulation in parallel, and omits the rounding of the product to improve the processing performance (delay and accuracy) of the MAC operation, according to IEEE Journal of Solid-State Circuits, vol. 25, No. 5, October 1990, 'Second-Generation RISC Floating Point with Multiply-Add Fused', in parallel with multiplication of values A and C so that value B accumulates with product A * C without delay after determination of product A * C. A floating point MAC device is disclosed that performs bit alignment on value B.

The resulting A * C + B accumulates without rounding or truncating the intermediate product A * C that might introduce an error. Incidentally, the leading zero predictor is responsible for the shift required to normalize the result A * C + B according to the floating point representation while the value B is accumulated with the product A * C so that the result A * C + B is normalized immediately after accumulation. To identify. Therefore, the fused MAC device is faster and more accurate than the multipliers and accumulators used throughout.

1 is a simplified diagram of a multiply and accumulator for a typical floating point A * C + B operation.

Multiplier 10 for determining the product Ma * Mc of values A and C and aligning the mantissa Mb of value B to accumulate with product Ma * Mc as shown here, and the mantissa Mb and product Ma * of value B Accumulator 20 accumulating Mc and leading zero or leading 1 / zero prediction to normalize the accumulated result in accumulator 20 and normalizing or rounding the result or detecting overflow and underflow exceptions It consists of the normalization unit 30.

Then, the multiplication unit 10 aligns the multiplier 12 which determines the product Ma * Mb of the values A and B, and the mantissa Mc of the value C to accumulate with the product Ma * Mb, and the exponents of the values A, B and C. It is composed of a sorter 14 which classifies and simplifies each MAC according to the magnitude of the value B for the product A * C with the exponential difference (Ea + Ec) -Eb indicated by.

As described above, when a floating point A * C + B operation is performed with a separate multiplier and an accumulator, two or more instructions are required, which requires computation speed and a large design area. The use of (unsigned) number multiplier multi-stage multiplier increases the chip size and causes a delay in computation speed.

The present invention has been made to solve the above problems, and an object of the present invention is a multiplier having the longest operation time among the three-stage pipelines of an operator when performing a floating point A * C + B operation with a single instruction. In order to reduce the size of the chip and improve the operation speed by using a booth algorithm to perform the operation in two cycles in the unsigned number processing, a floating point multiplication and accumulation device is provided.

1 is a simplified diagram of a multiply and accumulator for a typical floating point A * C + B operation.

2 is a block diagram showing a multiplier of a floating point multiply and accumulator according to the present invention.

4 is a diagram illustrating a sign bit extension and removal method in a floating point multiply and accumulator according to the present invention.

5 is a flowchart illustrating a multiplication process of a floating point multiplication and accumulation device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10: multiplication unit 20: accumulator

30: normalization unit

110,12: multiplier 120,14: sorter

112: partial product generation means 114: addition tree means

116: carry-hold addition means

The present invention for achieving the above object is a multiplier and a multiplier including a multiplier for determining the product of the first value and the second value of the floating point and a sorter for aligning the mantissa for the determination of the product and the accumulation of the third value In the floating-point multiplication and accumulator comprising an accumulator for accumulating a product of three values, a first value and a second value, and a normalizing unit for normalizing the accumulated result, the multiplier of the multiplier is a first cycle of starting an initial multiplication operation. A partial product generating means for generating a partial product by using a booth algorithm by dividing a multiplication number of 2n bits from the first value and the second value to be multiplied by n bits, and adding the partial product generated by the partial product generating means to the first value. An addition tree means for generating a sum and a first carry, and a first sum and first carry outputted from the addition tree means in a first cycle are fed back to the addition tree means to be generated in a second cycle; Claim characterized in that formed, including a carry hold adding means for adding the output end a second sum and a second carry.

In the above, when the multiplication product of 2n bits is separated in the partial product generating means, a value of "0" is inserted into the upper two bits of the lower n bits in the first cycle, and separated into n + 2 bits, and the upper n bits in the second cycle are lower. The processing is characterized by shifting to n bits.

In addition, it is characterized in that the code bit complementation is applied when the partial product generation means processes the partial product.

In addition, the carry-hold adding means is characterized by applying the 3: 2 array technique.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2 is a block diagram showing a multiplier of a floating point multiply and accumulator according to the present invention.

The present invention is a single-precision unsigned floating point operator that determines the product Ma * Mc of values A and C and aligns the mantissa Mb of value B to accumulate with product Ma * Mc as shown in FIG. (10), an accumulator 20 accumulating the mantissa Mb of the value B and the product Ma * Mc, and a leading zero or leading 1 / zero prediction is performed to normalize the result accumulated by the accumulator 20 and the result Multiply and accumulate the floating point A * C + B through the same process as the normalization unit 30 that normalizes or rounds or detects overflow and underflow exceptions.

In this case, as shown in FIG. 2, the multiplier 10 aligns the multiplier 110 that determines the product Ma * Mc of the values A and C, and the mantissa Mb of the value B to accumulate with the product Ma * Mc. An exponential difference (Ea + Ec) -Eb indicated by exponents of values A, B and C consists of a sorter 120 that sorts and simplifies each MAC according to the magnitude of the value B for the product A * C.

In addition, the multiplier 110 generates a partial product by generating a partial product using a booth algorithm by dividing a multiplier of 2n bits in the first value and the second value to be multiplied in the first cycle to start the first multiplication operation by n bits. Means 112, an addition tree means 114 for generating the first sum and the first carry by adding the partial products generated by the partial product generating means 112, and outputting from the addition tree means 114 in the first cycle. The first sum and the first carry are fed back to the adding tree means 114, and the carry sum adding means 116 outputs the final sum of the second sum and the second carry generated in the second cycle.

When the multiplying unit 112 divides the multiplying unit, multiplying the multiplying number by 2 bits is performed by n bits to reduce the chip area. In this case, as shown in FIG. 3, in the first cycle, when the unsigned number is processed by forming an n + 2 bit by including the lower n bits of the multiplication number and the two bits of the upper "0" value in the first cycle, A partial product of n / 2 + 1 is generated by correcting an incorrect operation result generated by applying a processing algorithm, and seven subproducts are generated after shifting the upper n bits to the lower n bits in the second cycle.

In addition, in order to reduce the burden on code bit extension when processing partial signed products, the code bit is extended as shown in (a) or the code as shown in (b) as shown in FIG. This will remove the bit extension.

The operation according to the present invention will be described with reference to a flowchart showing the multiplication of the floating point multiply and accumulator of FIG.

In the first cycle, the sorter 120 receives the exponents of the values A, B, and C, performs Ea + Ec between the exponents of the values A and B, and determines the shift amount to match the exponent and the number of digits of the value B. Shift the mantissa of value B by Fit the digits to the result of Ma * Mc.

Meanwhile, in the multiplier 110, n + 2 including the lower n bits of the multiplication number and the two bits of the upper "0" value in the partial product generating unit 112 in the first cycle to generate the partial product of the values A and C. When a bit is formed and an unsigned number is processed, a partial product of n / 2 + 1 is generated by applying a booth algorithm that processes a sign number to generate a partial product of n / 2 + 1 to form a first sum in the mantissa tree means 114. And the first carry is generated.

After shifting the upper n bits to the lower n bits in the second cycle, seven partial products are generated to feed back the first sum and the first carry to the mantissa tree means 114 and the value generated in the sorter 120 is a mantissa. Outputted to the tree means 114 produces a second sum and a second carry finally added by the carry holding means 116.

Then, the second sum output from the carry holding means 116 and the aligned value of the second carry and aligner 120 are output to the accumulator 20 in the third cycle.

Subsequent processes include leading zero or leading 1 / zero prediction to accumulate the mantissa Mb of the value B and the product Ma * Mc in the accumulator 20 and normalize the result accumulated in the normalizer 30 as described above. Performs multiplication and accumulation of floating point A * C + B by performing, normalizing or rounding the result, or detecting overflow and underflow exceptions.

As described above, in the present invention, when performing the operation of A * C + B of floating point with a single instruction, the multiplier having the longest operation time among the three-stage pipelines of the operator can be operated in two cycles when unsigned. By using a booth algorithm to reduce the size of the chip and improve the operation speed, there is an advantage that can be embedded into a small-area, high-performance calculator in a portable device with a graphics function.

Claims (4)

A multiplier comprising a multiplier for determining the product of the first and second values of the floating point and a sorter for aligning the mantissa for the determination of the product and the accumulation of the third value, and the third and the first and second values, respectively. In the floating point multiplication and accumulation device comprising an accumulator for accumulating a product and a normalizer for normalizing the accumulated result, The multiplier of the multiplication unit generates a partial product by generating a partial product by a booth algorithm by dividing a multiplier of n bits from the first value and the second value to be multiplied in the first cycle to start the first multiplication operation by n bits. , Addition tree means for generating a first sum and a first carry by adding the partial product generated by the partial product generating means; Carry-hold adding means for feeding back the first sum and the first carry output from the adding tree means in the first cycle to the adding-tree means to finally add and output the second sum and the second carry generated in the second cycle. Floating point multiplication and accumulation device, characterized in that consisting of. 2. The method of claim 1, wherein when the multiplying means of 2n bits is separated in the partial product generating means, a " 0 " value is inserted into the upper two bits of the lower n bits in the first cycle and separated into n + 2 bits. A multiplicand and accumulator of a floating point number characterized in that the upper n bits are moved to the lower n bits for processing. The floating point multiplication and accumulating device according to claim 1, characterized in that code bit complementary is applied when the partial product generating means processes the partial product. The floating point multiplication and accumulating device according to claim 1, wherein the carry-hold adding means applies a 3: 2 array technique.