WO2022170809A1

WO2022170809A1 - Reconfigurable floating point multiply-accumulate operation unit and method suitable for multi-precision calculation

Info

Publication number: WO2022170809A1
Application number: PCT/CN2021/131745
Authority: WO
Inventors: 毛伟; 余浩; 谢歆昂; 李凯; 李博宇; 杜来民; 代柳瑶
Original assignee: 南方科技大学
Priority date: 2021-02-09
Filing date: 2021-11-19
Publication date: 2022-08-18
Also published as: CN112860220B; CN112860220A

Abstract

Disclosed in the present invention are a reconfigurable floating point multiply-accumulate operation unit and method suitable for multi-precision calculation. A uniform method is used to divide mantissas of floating points of different precision to obtain a plurality of bit segments; different numbers of same-type unit multipliers are called to implement multiplication operations of the plurality of bit segments in one period, and corresponding products are outputted; then, a shift-add operation is performed on the products to obtain a multiply-accumulate operation result of floating-point numbers. In the present invention, the problem of bit redundancy is avoided by employing a uniform mantissa division scheme, the hardware utilization rate is increased by employing a uniform unit multiplier, and the multiply-accumulate operation of half-precision floating-point numbers, the multiply-accumulate operation of single-precision dot product floating-point numbers, and the multiply-accumulate operation of double-precision floating-point numbers can be achieved. The problems in the prior art of bit redundancy, low hardware utilization rate and the like of an operation method supporting a multi-precision floating point multiplication operation are solved.

Description

A reconfigurable floating-point multiply-accumulate unit and method suitable for multi-precision computing

technical field

The invention relates to the field of digital circuits, in particular to a reconfigurable floating-point multiply-add operation unit and method suitable for multi-precision calculation.

Background technique

With the rapid development and wide application of scientific computing and machine learning training, multiplication units that can support floating-point data processing emerge as the times require. The fixed number of input bits of the conventional floating point multiplier cannot meet the requirements of multi-precision calculation, so there is a method to support multi-precision floating-point multiplication. However, the existing operation methods that support multi-precision floating-point multiplication require multiple mantissa division schemes and need to separate the generated product into two parallel parts by zero-filling, so there is a loss of precision, bit redundancy, and hardware utilization. lower issues.

Therefore, the existing technology still needs to be improved and developed.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a reconfigurable floating-point multiply-add operation unit and method suitable for multi-precision calculation, aiming at solving the problem of supporting multi-precision floating point in the prior art The operation method of the multiplication operation will cause problems such as bit redundancy and low hardware utilization.

The technical scheme adopted by the present invention to solve the problem is as follows:

In a first aspect, an embodiment of the present invention provides a reconfigurable floating-point multiply-add operation method suitable for multi-precision computing, wherein the method includes:

Obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several include one;

Determine the number of called unit multipliers according to the precision of the floating-point number to be operated, take a target segment as an operand of a unit multiplier, and obtain a product generated by the unit multiplier based on the operand;

A shift-add operation is performed on the product, and an operation result generated based on the shift-add operation is used as the result of the multiply-accumulate operation of the floating-point number to be operated.

In one embodiment, the obtaining the significant digits of the floating-point number to be operated, and generating several target segments based on the significant digits; the several target segments include one, including:

Add a 1-bit integer to the mantissa part of the floating-point number to be operated;

Taking the number on the significant digits of the floating-point number obtained after the addition is completed as the significant number of the floating-point number to be operated;

When the number of bits of the significant figure is greater than the number of bits of the unit multiplier, the significant number is divided according to the number of bits of the unit multiplier, and after division, several target segments are generated; including one.

In an embodiment, the number of called unit multipliers is determined according to the precision of the floating-point number to be operated, a target segment is used as an operand of a unit multiplier, and the unit multiplier is obtained based on the Operand-generated products include:

Determine the number of called unit multipliers according to the precision of the floating-point number to be operated;

take a target segment as an operand of a unit multiplier;

A number of row products are generated after the operands are input to the unit multiplier.

In an implementation manner, when the unit multiplier is a 14-bit multiplier, the determining the number of unit multipliers to be called according to the precision and logarithm of the floating-point number to be operated includes:

When the floating-point number to be operated is a half-precision floating-point number, n calls n unit multipliers for the floating-point number to be operated;

When the floating-point number to be operated is a single-precision floating-point number, n calls 4n unit multipliers for the floating-point number to be operated;

When the floating-point number to be operated is a double-precision floating-point number, n calls 16n unit multipliers for the floating-point number to be operated;

n is an integer greater than 0.

In one embodiment, the generating of several row products after the operand is input to the unit multiplier includes:

The operand is input into the unit multiplier, and the operand is encoded by the unsigned bit Booth to generate several row products.

In one embodiment, when the floating-point number to be operated is a double-precision floating-point number, before the using a target segment as an operand of a unit multiplier further includes:

When the number of bits of the target segment corresponding to the floating-point number to be operated is not equal, a complement operation is performed on the target segment with the smallest number of bits.

In an implementation manner, performing a shift-add operation on the product, and using an operation result generated based on the shift-add operation as the result of the multiply-accumulate operation of the floating-point number to be operated includes:

inputting the product into a preset addition tree;

Calculate the displacement amount of the product, and perform a shift operation on the product according to the displacement amount through the addition tree;

After the data obtained after the shift operation is summed, the result of the multiply-accumulate operation of the floating-point number to be operated is obtained.

In one embodiment, the displacement includes at least one of an internal displacement and an external displacement;

The calculation method of the internal displacement amount is: taking the sum of the high and low bits of the segment numbers divided based on the floating-point number to be operated as the internal shift amount of the product corresponding to the segment number;

The calculation method of the external displacement is as follows: adding the exponent parts of the floating-point numbers to be operated to obtain an exponent sum, and taking the maximum value of all the exponent sums obtained as a reference value; The difference obtains the exponent difference, and the exponent difference is used as the external shift amount of the product corresponding to the floating-point number to be operated.

In a second aspect, an embodiment of the present invention also provides a reconfigurable floating-point multiply-add operation unit suitable for multi-precision computing, characterized in that the operation unit includes:

A division module, used to obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several include one;

a unit multiplier, used for determining the number of unit multipliers to be called according to the precision of the floating-point number to be operated, taking a target segment as an operand of a unit multiplier, and obtaining the unit multiplier generated based on the operand the product of ;

An addition tree, configured to perform a shift-add operation on the product, and use an operation result generated based on the shift-add operation as a result of the multiply-accumulate operation of the floating-point number to be operated.

In one embodiment, the operation unit includes 16n unit multipliers, and n is a non-negative number.

Beneficial effects of the present invention: The embodiment of the present invention avoids the problem of bit redundancy by adopting a unified mantissa division scheme, improves the hardware utilization rate by adopting a unified unit multiplier, and can also realize the multiply-accumulate operation of half-precision floating-point numbers, single The multiply-accumulate operation of precision floating-point numbers and the multiply-accumulate operation of double-precision floating-point numbers. It solves the problems of bit redundancy and low hardware utilization in the operation method supporting multi-precision floating-point multiplication in the prior art.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic flowchart of a reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a division scheme of significant digits of floating-point numbers of different precisions provided by an embodiment of the present invention.

FIG. 3 is a schematic diagram of a working principle of a 14-bit basic multiplier provided by an embodiment of the present invention.

FIG. 4 is a calculation diagram of 16 groups of products input to an adder tree when a pair of FP64 is calculated according to an embodiment of the present invention.

FIG. 5 is an internal basic block diagram of a reconfigurable floating-point multiply-add operation unit suitable for multi-precision calculation provided by an embodiment of the present invention.

FIG. 6 is a reference diagram of a minimum operation unit that can implement mantissa multiply-accumulate operations of three types of floating-point numbers of different precisions provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer and clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indications are only used to explain a certain posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly.

With the rapid development and wide application of scientific computing and machine learning training, multiplication units that can support floating-point data processing emerge as the times require. The number of input bits of the conventional fixed-point multiplier is fixed, which cannot meet the requirements of multi-precision computing, and cannot maximize the use of hardware resources to improve the energy efficiency ratio and throughput rate according to application requirements. Hence the method for multi-precision floating-point multiplication. However, some existing methods that support multi-precision floating-point multiplication operations need to separate the generated product into two parallel parts by zero-filling when implementing multi-precision multiplication, which leads to a reduction in the utilization of system modules; Some methods that support multi-precision floating-point multiplication require different mantissa division schemes when implementing multi-precision multiplication. For example, the architecture is based on a 15-bit multiplier, which is optimized to support FP128-precision floating-point multiplication, but uses When performing floating-point multiplication operations of other precisions, a large amount of bit redundancy and waste of hardware resources will be generated. In short, the fixed-point multiplier has a fixed number of input bits, which cannot meet the requirements of multi-precision computing, and cannot maximize the use of hardware resources for application requirements to improve energy efficiency ratio and throughput; while the existing ones support multi-precision floating-point. The multiplication operation method also has problems such as loss of precision, bit redundancy, and low hardware utilization.

Based on the above-mentioned defects of the prior art, the present invention provides a reconfigurable floating-point multiply-add operation method suitable for multi-precision calculation. By adopting a unified method to divide the mantissas of floating-point numbers of different precisions, multiple bit segments are obtained. , and call different numbers of the same type of unit multipliers to complete the multiplication operation of multiple bit segments in one cycle and output the corresponding product, and then shift and add the product to obtain the mantissa phase of the floating point. The result of the multiplication operation. The invention adopts a unified mantissa division scheme to avoid the problem of bit redundancy, adopts a unified unit multiplier to improve the hardware utilization rate, and can also realize the multiply-accumulate operation of half-precision floating-point numbers, the multiply-accumulate operation of single-precision floating-point numbers, and the double-accumulation operation of double-precision floating-point numbers. Multiply-accumulate operation of precision floating-point numbers. It solves the problems of bit redundancy and low hardware utilization in the operation method supporting multi-precision floating-point multiplication in the prior art.

As shown in Figure 1, the method includes the following steps:

Step S100: Obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several target segments include one.

In the multiplication of floating-point numbers, the exponent part of the multiplication result is the sum of the exponent parts of the two floating-point numbers to be multiplied, and the mantissa part of the multiplication result is the product of the mantissas of the two multiplied floating-point numbers. This embodiment mainly optimizes the method for generating the mantissa part of the multiplication result in the multiplication of floating-point numbers, that is, the product of the mantissas of two multiplied floating-point numbers. Specifically, firstly, the present embodiment needs to obtain the significant digits of the floating-point number to be operated, and the significant digits refer to the data that needs to participate in the multiplication operation in the mantissa of the floating-point number to be operated. Only the significant digits that need to participate in the multiplication operation are determined first, Subsequent multiplication operations can be performed. After the significant figures are obtained, this embodiment needs to generate one or more target segments based on the significant figures, and then use the target segments as input data of the unit multiplier.

The step S100 includes the following steps:

Step S110, adding a 1-bit integer to the mantissa part of the floating-point number to be operated;

Step S120, taking the number on the significant digits of the floating-point number obtained after adding as the significant number of the floating-point number to be operated;

Step S130, when the number of bits of the significant figure is greater than the number of bits of the unit multiplier, divide the significant number according to the number of bits of the unit multiplier, and generate several target segments after division; The several include one.

Specifically, in order to obtain the significant digits of the floating-point number to be calculated, in this embodiment, a 1-bit integer needs to be added to the mantissa part of the floating-point number to be calculated, and then the significant digits of the floating-point number obtained after adding are added. The number is used as the significant figure of the floating point number to be operated on. For example, after adding a 1-bit integer to the mantissa part of a half-precision floating point number (floating point 16-bit, FP16), the significant number of digits is 11; for a single-precision floating point number (floating point 32-bit number, FP32) The mantissa After adding a 1-bit integer to the part, the significand is 24 bits; for a double-precision floating point number (floating point 64-bit number, FP64), after adding a 1-bit integer to the mantissa, the significand is 53 bits. After the significant figures are obtained, in this embodiment, the target segment needs to be obtained according to the significant figures, and the target segment is used as the input data of the subsequent unit multiplier.

Specifically, in this embodiment, it is necessary to compare the number of bits of the significant figure and the number of bits of the unit multiplier, and finally determine what processing should be performed on the significant number, and then generate the target segment. When the number of bits of the significant figure is less than or equal to the number of bits of the unit multiplier, the significant number may be directly input into the unit multiplier as a target segment. For example, as shown in Figure 2, when the unit multiplier is a 14-bit basic unit multiplier, the significant figures of the 16-bit floating-point numbers have only 11 bits, so there is no need to divide the significant figures of the 16-bit floating-point numbers. Use it directly as a target segment.

When the number of bits of the significant figure is greater than the number of bits of the unit multiplier, it is obvious that the significant number cannot be directly input into the unit multiplier, so the significant number needs to be divided, and then Several target segments generated after division are input into the unit multiplier. For example, when the unit multiplier is a 14-bit basic unit multiplier, the significant figure of a 32-bit floating point number is 24 bits, so the significant figure needs to be divided to generate two 12-bit target segments. In the same way, the significant figure of a 64-bit floating point number is 53 bits, so the significant figure also needs to be divided, and then 4 target segments of 14:13:13:13 are generated.

After the target segment is acquired, the target segment needs to be input into the unit multiplier, so as shown in FIG. 1 , the method further includes the following steps:

Step S200: Determine the number of called unit multipliers according to the precision of the floating-point number to be operated, take a target segment as an operand of a unit multiplier, and obtain a product generated by the unit multiplier based on the operand.

In this embodiment, firstly, the number of called unit multiplications needs to be determined according to the precision of the floating-point number to be operated. Then use the obtained target segment as an operand of a unit multiplier. It can be understood that a unit multiplier needs two operands to perform multiplication, one operand is used as a multiplier, and the other operand is used as a multiplicand . The product generated by the unit multiplier based on the operands is then obtained. In multiplication, if the multiplier is a number with two or more digits, when multiplying, each digit of the multiplier must be used to multiply the multiplicand, and the product obtained each time is called the product, or called incomplete. product.

The step S200 specifically includes the following steps:

Step 210, determining the number of called unit multipliers according to the precision of the floating-point number to be operated;

Step 220, using a target segment as an operand of a unit multiplier;

Step 230: Input the operand into the unit multiplier to generate several row products.

In this embodiment, it is first necessary to determine the number of called unit multipliers. In an implementation manner, when the unit multiplier is a 14-bit multiplier, the determining the number of unit multipliers to call according to the precision and logarithm of the floating-point number to be operated includes: when the to-be-operated floating-point number is When the floating-point number is a half-precision floating-point number, n calls n-unit multipliers for the floating-point number to be operated; when the floating-point number to be operated is a single-precision floating-point number, n calls 4n-unit multipliers for the floating-point number to be operated; When the floating-point number to be operated is a double-precision floating-point number, n calls 16n unit multipliers for the floating-point number to be operated; n is an integer greater than 0.

For example, assuming that the unit multiplier is a 14-bit basic unit multiplier, when you need to calculate the multiplication and accumulation results of 16 pairs of half-precision floating-point numbers at the same time, you need to call 16 14-bit basic unit multipliers for the following reasons. The embodiment is to divide the significant figures based on the number of bits of the unit multiplier, and the significant figures of the half-precision floating-point numbers can be directly used as a target segment. A pair of half-precision floating-point numbers needs to call a 14-bit basic unit multiplier, and a total of 16 14-bit basic unit multipliers need to be called. Similarly, when the multiplication and accumulation operation results of 4 pairs of single-precision floating-point numbers need to be calculated at the same time, 16 14-bit basic unit multipliers also need to be called. Because the significant digits of single-precision floating-point numbers need to be divided before they can be input into the unit multiplier, and the result of the division is to generate 2 target segments, then there are 2*2=4 types between the 4 target segments corresponding to 1 pair of single-precision floating-point numbers In the multiplication and combination mode, 4 unit multipliers are required, and 4*4=16 unit multipliers are required for the multiply-accumulate operation of 4 pairs of single-precision floating-point numbers. Similarly, when the multiplication and accumulation results of a pair of double-precision floating-point numbers need to be calculated at the same time, 16 14-bit basic unit multipliers also need to be called for the following reasons, because the significant digits of double-precision floating-point numbers are divided to generate 4 target segments, then There are 4*4=16 multiplication combinations between the 8 target segments corresponding to a pair of double-precision floating-point numbers, so a total of 16 14-bit basic unit multipliers are required.

In addition, since it is possible to generate target segments with unequal number of bits after the significant digits are divided, in an implementation manner, before using a target segment as an operand of a unit multiplier, it further includes: when the to-be-to-be-multiplier is used When the number of bits of the target segment to which the floating-point number should be operated is not equal, a complementing operation is performed on the target segment with the smallest number of bits, and the complementing operation may be implemented in the form of zero-filling. For example, when the unit multiplier is a 14-bit basic unit multiplier, the significant figure corresponding to the double-precision floating-point number is 53 bits, and the four target ends of 14:13:13:13 generated after division need to The 13-bit target segment is zero-padded.

A target segment is then used as one operand of a unit multiplier, after which several row products generated by the unit multiplier are taken. Specifically, after the operand is input to the unit multiplier, the unit multiplier encodes the operand through an unsigned bit booth and generates several row products (as shown in FIG. 3 ). .

After the product is obtained, in order to obtain the result of the multiply-accumulate operation of floating-point numbers, as shown in FIG. 1 , the method further includes the following steps:

Step S300: Perform a shift-add operation on the product, and use an operation result generated based on the shift-add operation as a result of the multiply-accumulate operation of the floating-point number to be operated.

In this embodiment, after the product output by the unit multiplier is obtained, in order to obtain an accurate multiplication result, it is necessary to perform a shift-add operation on the obtained product, and then use the result of the shift-add operation as the above-mentioned operation result. The result of the multiply-accumulate operation of the floating-point number to be operated on.

In an implementation manner, the step S300 specifically includes the following steps:

Step S310, inputting the product into a preset addition tree;

Step S320, calculating the displacement of the product, and performing a shift operation on the product according to the displacement through the addition tree;

Step S330 , performing a summation operation on the data obtained after the shift operation to obtain a result of the multiply-accumulate operation of the floating-point number to be operated.

In this embodiment, an addition tree is preset for the scheme of generating the target segment and the usage of the unit multiplier, so as to realize the lossless processing of the data. Specifically, after the product is obtained, the product is input into the addition tree, then the displacement of the product is calculated in the addition tree, and then the product is shifted according to the displacement. . Specifically, the displacement calculated in the addition tree includes at least one of an internal displacement and an external displacement, that is, it may include only the internal displacement, only the external displacement, or both the internal displacement The final value of the displacement amount needs to be determined according to the precision of the floating point number to be operated and the logarithm of the calculation. The calculation method of the internal displacement amount is to use the sum of the high and low bits of the segment numbers divided based on the floating-point number to be operated as the internal shift amount of the product corresponding to the segment numbers. The calculation method of the external displacement is as follows: adding the exponent parts of the floating-point numbers to be operated to obtain an exponent sum, taking the maximum value of all exponent sums obtained as a reference value, and then adding the reference value to the exponent sum. A difference is obtained to obtain an exponent difference, and finally the exponent difference is used as the external shift amount of the product corresponding to the floating-point number to be operated.

In short, when calculating multiple pairs of floating-point numbers at the same time, the number in the exponent part of the floating-point number itself needs to be used as the external displacement. After the significant digits are divided, since different unit multipliers are called for operation, although the number of bits of the output product of each unit multiplier is the same, the sum of the high and low bits of the divided segment numbers needs to be used as the internal displacement The correct multiplication-accumulation result of floating-point numbers can be generated after accumulating the corresponding high and low bits and then accumulating.

For example, to calculate the multiplication and accumulation results of 16 pairs of half-precision floating-point numbers at the same time, 16 14-bit basic unit multipliers need to be called. Since the significant digits of half-precision floating-point numbers are not divided, it is necessary to calculate the multiplication of multiple pairs of floating-point numbers at the same time. The result of multiply-accumulate operation, so in this case, the displacement of the product is only the external displacement. First, query the sum of 16 exponents of 16 pairs of half-precision floating-point numbers, and use the largest sum of the 16 exponent sums as the reference value. Subtract 16 different exponent sums from the above reference values to obtain the external displacement.

When calculating the multiplication-accumulation results of 4 pairs of single-precision floating-point numbers at the same time, since the significant digits of the single-precision floating-point numbers are input into the unit multiplier after division, and the multiplication-accumulation results of multiple pairs of floating-point numbers need to be calculated at the same time, Therefore, the displacement of the product in this case includes both the internal displacement and the external displacement. First, query the sum of 4 exponents of 4 pairs of single-precision floating-point numbers, take the largest sum of the 4 exponent sums as the reference value, and then subtract 4 different sums of exponents from the reference value to obtain the external displacement . In addition, it is also necessary to use the high and low bits of the segment number divided based on the floating-point number to be operated as the internal shift amount of the product corresponding to the segment number. For example, the segment number of a ₀ ×b ₀ and bit 0+0=0, then The internal displacement is 0; the segment number of a ₁ ×b ₀ and bit 1+0=1, then the internal displacement is 1×14=14 bits to the left; the segment number of a ₃ ×b ₁ and bit 3+1= 4, then the internal displacement is 4×14=56 bits to the left.

When calculating the result of multiply-accumulate operation of one pair of double-precision floating-point numbers, since the significant figures of double-precision floating-point numbers are input into the unit multiplier after division, but only need to calculate the result of multiply-accumulate operation of one pair of floating-point numbers, so In this case, the displacement of the product only includes the internal displacement. For example, a ₁ ×b ₀ results in a displacement of 1 × 14bit, and a ₁ ×b ₁ and a ₂ ×b ₀ The resulting displacement is 2 × 14bit ( As shown in Figure 4).

After calculating the displacement of the product, perform a shift operation on the product according to the displacement, and then perform a sum operation on the data obtained after the shift operation, and then the multiplication of the floating-point number to be operated can be obtained. The result of the accumulation operation.

Based on the above embodiment, the present invention also provides a reconfigurable floating-point multiply-add operation unit suitable for multi-precision calculation. As shown in FIG. 5 , the operation unit includes:

A division module 01 is used to obtain the significant figures of the floating-point numbers to be operated, and generate several target segments based on the significant figures; the several include one;

Unit multiplier 02, for determining the number of unit multipliers to be called according to the precision of the floating-point number to be operated, taking a target segment as an operand of a unit multiplier, and obtaining the unit multiplier based on the operand the resulting product;

The addition tree 03 is configured to perform a shift-add operation on the product, and use the operation result generated based on the shift-add operation as the result of the multiply-accumulate operation of the floating-point number to be operated.

In an implementation manner, in order to enable the operation unit to realize the multiply-accumulate operation of half-precision floating-point numbers, single-precision floating-point numbers and double-precision floating-point numbers, the operation unit includes 16n unit multipliers, and n is a non-negative number . For example, as shown in FIG. 6 , when the operation unit includes 16 14-bit basic unit multipliers, each unit multiplier can realize 1 set of half-precision floating-point multiplication operations, so 16 pairs of half-precision can be realized at the same time Multiplication and accumulation of floating-point numbers. Every 4 unit multipliers can realize 1 set of single-precision floating-point multiplication operations, so it can also realize the multiply-accumulate operation of 4 pairs of single-precision floating-point numbers at the same time. The 16 unit multipliers can realize a set of double-precision floating-point multiplication operations, so it can also realize a multiply-accumulate operation of a pair of double-precision floating-point numbers. FIG. 6 is a reference diagram of a minimum operation unit provided by the present invention that can realize the multiply-accumulate operation of three floating-point numbers of different precisions. Therefore, the embodiments of the present invention can at least complete the multiply-accumulate operations of multiple pairs of half-precision floating-point numbers, the multiply-accumulate operations of multiple pairs of single-precision floating-point numbers, or the multiply-accumulate operations of one pair of double-precision floating-point numbers within one clock cycle without limiting hardware resources. Multiply and accumulate operations. Compared with the fixed FP32 and FP64 multiply-add units, the arithmetic unit provided by the present invention can increase the maximum throughput rate by 4 times and 16 times respectively.

To sum up, the present invention discloses a reconfigurable floating-point multiply-add operation unit and method suitable for multi-precision calculation. By adopting a unified method to divide the mantissas of floating-point numbers of different precisions, a plurality of bit segments are obtained. , and call different numbers of the same type of unit multipliers to complete the multiplication operation of multiple bit segments in one cycle and output the corresponding product, and then perform the shift and addition operation on the product to obtain the multiplication and accumulation of floating-point numbers. Operation result. The invention adopts a unified mantissa division scheme to avoid the problem of bit redundancy, adopts a unified unit multiplier to improve the hardware utilization rate, and can also realize the multiply-accumulate operation of half-precision floating-point numbers, the multiply-accumulate operation of single-precision floating-point numbers, and the double-accumulation operation of double-precision floating-point numbers. Multiply-accumulate operation of precision floating-point numbers. It solves the problems of bit redundancy and low hardware utilization in the operation method supporting multi-precision floating-point multiplication in the prior art.

It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above descriptions, and all these improvements and transformations should belong to the protection scope of the appended claims of the present invention.

Claims

A reconfigurable floating-point multiply-add operation method suitable for multi-precision computing, characterized in that the method comprises:

Obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several include one;

Determine the number of called unit multipliers according to the precision of the floating-point number to be operated, take a target segment as an operand of a unit multiplier, and obtain a product generated by the unit multiplier based on the operand;

A shift-add operation is performed on the product, and an operation result generated based on the shift-add operation is used as the result of the multiply-accumulate operation of the floating-point number to be operated.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to claim 1, wherein the obtaining the significant digits of the floating-point number to be operated, generates several target segments based on the significant digits ; the several include one including:

Add a 1-bit integer to the mantissa part of the floating-point number to be operated;

Taking the number on the significant digits of the floating-point number obtained after the addition is completed as the significant number of the floating-point number to be operated;

When the number of bits of the significant figure is greater than the number of bits of the unit multiplier, the significant number is divided according to the number of bits of the unit multiplier, and after division, several target segments are generated; including one.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to claim 1, wherein the number of called unit multipliers is determined according to the precision of the floating-point number to be operated, Taking a target segment as an operand of a unit multiplier, obtaining the product generated by the unit multiplier based on the operand includes:

Determine the number of called unit multipliers according to the precision of the floating-point number to be operated;

take a target segment as an operand of a unit multiplier;

A number of row products are generated after the operands are input to the unit multiplier.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to claim 3, wherein when the unit multiplier is a 14-bit multiplier, the floating-point multiplier according to the to-be-operated multiplier Point precision and logarithms determine the number of cell multipliers called by:

When the floating-point number to be operated is a half-precision floating-point number, n calls n unit multipliers for the floating-point number to be operated;

When the floating-point number to be operated is a single-precision floating-point number, n calls 4n unit multipliers for the floating-point number to be operated;

When the floating-point number to be operated is a double-precision floating-point number, n calls 16n unit multipliers for the floating-point number to be operated;

n is an integer greater than 0.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to claim 3, wherein the generating of several row products after the operand is input to the unit multiplier comprises:

The operand is input into the unit multiplier, and the operand is encoded by the unsigned bit Booth to generate several row products.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to claim 3, wherein when the floating-point number to be operated is a double-precision floating-point number, the target segment is used as the An operand of a unit multiplier also includes:

When the number of bits of the target segment corresponding to the floating-point number to be operated is not equal, a complement operation is performed on the target segment with the smallest number of bits.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computation according to claim 1, wherein the shift-add operation is performed on the product, and the shift-add operation is performed based on the shift-add operation. The operation result generated by the addition operation, as the result of the multiply-accumulate operation of the floating-point number to be operated, includes:

inputting the product into a preset addition tree;

Calculate the displacement amount of the product, and perform a shift operation on the product according to the displacement amount through the addition tree;

After the data obtained after the shift operation is summed, the result of the multiply-accumulate operation of the floating-point number to be operated is obtained.
The reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to claim 7, wherein the displacement includes at least one of an internal displacement and an external displacement;

The calculation method of the internal displacement amount is: taking the sum of the high and low bits of the segment numbers divided based on the floating-point number to be operated as the internal shift amount of the product corresponding to the segment number;

The calculation method of the external displacement is as follows: adding the exponent parts of the floating-point numbers to be operated to obtain an exponent sum, and taking the maximum value of all the exponent sums obtained as a reference value; The difference obtains the exponent difference, and the exponent difference is used as the external shift amount of the product corresponding to the floating-point number to be operated.
A reconfigurable floating-point multiply-add operation unit suitable for multi-precision computing, characterized in that the operation unit includes:

A division module, used to obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several include one;

a unit multiplier, used for determining the number of unit multipliers to be called according to the precision of the floating-point number to be operated, taking a target segment as an operand of a unit multiplier, and obtaining the unit multiplier generated based on the operand the product of ;

An addition tree, configured to perform a shift-add operation on the product, and use an operation result generated based on the shift-add operation as a result of the multiply-accumulate operation of the floating-point number to be operated.
A reconfigurable floating-point multiply-add operation unit suitable for multi-precision calculation according to claim 9, characterized in that, the operation unit includes 16n unit multipliers, and n is a non-negative number.