CN107168678B - Multiply-add computing device and floating-point multiply-add computing method - Google Patents
Multiply-add computing device and floating-point multiply-add computing method Download PDFInfo
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Abstract
The embodiment of the invention provides a multiply-add computing device and a floating-point multiply-add computing method. The multiplication and addition computing device comprises at least two floating point part multipliers and a multi-input adder, wherein each floating point part multiplier consists of a sign bit exclusive OR circuit, a mantissa multiplier and an exponent adder, each floating point part multiplier receives the normalized floating point number, performs multiplication computation to output a non-normalized floating point number, and the adder receives the non-normalized floating point number, accumulates the input non-normalized floating point number and outputs the normalized floating point number. The floating point part of the multiplier only comprises a sign bit exclusive OR circuit, the mantissa multiplier and the exponent adder do not comprise a normalization module, the non-normalization floating point number is output after the normalization floating point number is received and subjected to multiplication operation, the adder performs addition operation and outputs the normalization floating point number, the multiplication and addition computing device is optimized in terms of hardware circuits, the operation efficiency of the multiplication and addition computing device is improved, and the area and the power consumption of the hardware circuits are reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of computer hardware structures and circuit designs, in particular to a multiply-add computing device and a floating-point multiply-add computing method.
Background
In recent years, various machine learning algorithms such as deep convolutional neural networks are widely used in multiple fields, and as the technology is updated, the machine learning algorithms become more computationally intensive and storage intensive, and accordingly, the required computational resources and storage resources are increasing. To solve this problem, the development of dedicated hardware has become one of the accepted solutions in academia and industry. The academia and industry have proposed many different architectures of hardware acceleration platforms. However, there is no method for optimizing and designing a hardware circuit to improve the operation efficiency, so it is an urgent technical problem in the art to provide a method for optimizing and improving the operation efficiency of a multiply-add computing device.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a multiply-add calculation method and apparatus.
In one aspect, an embodiment of the present invention provides a multiply-add calculation apparatus, including at least two floating point partial multipliers and a multi-input adder, where the floating point partial multiplier is composed of a sign bit exclusive or circuit, a mantissa multiplier, and an exponent adder, the floating point partial multiplier receives a normalized floating point number and performs multiplication to output a non-normalized floating point number, the adder receives the non-normalized floating point number and accumulates the input non-normalized floating point number to output a normalized floating point number, the non-normalized floating point number is composed of a sign bit, a non-normalized mantissa, and an exponent portion, and the normalized floating point number is composed of a sign bit, a normalized mantissa, and an exponent portion.
In another aspect, an embodiment of the present invention provides a floating-point multiply-add calculation method, including:
receiving at least four normalized floating point number inputs;
performing multiplication operation on the normalized floating point number to obtain a non-normalized floating point number;
and performing addition operation on the non-normalized floating point number to obtain a normalized floating point number.
The multiply-add computing device and the floating-point multiply-add computing method provided by the embodiment of the invention have the advantages that at least two floating-point part multipliers and a multi-input adder are arranged, the floating-point part multipliers only comprise sign bit exclusive-OR circuits, the mantissa multipliers and the exponent adder do not comprise normalization modules, non-normalized floating-point numbers are output after the normalized floating-point numbers are received and subjected to multiplication operation, the adder performs addition operation on the non-normalized floating-point numbers and outputs the normalized floating-point numbers, the multiply-add computing device is optimized in terms of hardware circuits, the operating efficiency of the multiply-add computing device is improved, and the area and the power consumption of the hardware.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a multiply-add computing device according to an embodiment of the present invention;
FIG. 2 is a block diagram of a floating-point partial multiplier in a multiply-add computing device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a sixteen-input multiply-add computing device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an eight-input adder in a sixteen-input multiply-add computing device according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating a floating-point multiply-add calculation method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a multiply-add computing device according to an embodiment of the present invention, fig. 2 is a schematic structural diagram of a floating-point partial multiplier in the multiply-add computing device according to an embodiment of the present invention, as shown in fig. 1 and fig. 2, the multiply-add computing apparatus provided by the embodiment of the present invention includes at least two floating-point partial multipliers 1 and a multi-input adder 2, the floating-point partial multiplier is composed of a sign bit exclusive-or circuit 11, a mantissa multiplier 12 and an exponent adder 13, the floating-point part multiplier 1 receives the normalized floating-point number and performs multiplication to obtain a non-normalized floating-point number, the adder 2 accumulates the non-normalized floating point number and outputs a normalized floating point number, the non-normalized floating point number is composed of a sign bit, a non-normalized mantissa and an exponent portion, and the normalized floating point number is composed of a sign bit, a normalized mantissa and an exponent portion.
The operation of the convolutional neural network is composed of a large number of continuous multiplication and addition, and the operation method in the prior art is to use a plurality of independent floating-point multipliers and a multi-input adder to perform the operation: the normalized floating point number is output by each multiplication, and then the normalized floating point number output by the multiplication is used as the input of the multi-input adder, the multi-input adder is also an addition tree formed by a plurality of adders, and each addition outputs one normalized floating point number as the input of the next addition. The normalized floating point number referred to herein refers to a floating point number that conforms to the IEEE754 standard. The multiply-add computing device provided by the embodiment of the invention is composed of a plurality of floating-point partial multipliers 1 and a multi-input adder 2, wherein the floating-point partial multiplier is a multiplier which is composed of a sign bit exclusive-OR circuit 11, a mantissa multiplier 12 and an exponent adder 13 and does not comprise a normalization module. When performing multiply-add operation, one floating-point partial multiplier receives two normalized floating-point number inputs, the sign bit of the two floating-point numbers is subjected to exclusive-or operation by the sign bit exclusive-or circuit 11 to obtain a new sign bit, the mantissa bits of the two floating-point numbers are subjected to multiplication operation by the mantissa multiplier 12 to obtain a new mantissa bit, and the exponent of the exponent bits of the two floating-point numbers is subjected to addition operation by the exponent adder 13 to obtain a new exponent bit. Since the mantissa multiplier 12 performs multiplication on the mantissa bits of two floating point numbers, the obtained new mantissa bits cannot guarantee that the normalization requirement is still met, so that the obtained result is a non-normalized mantissa, and the new sign bit, the non-normalized mantissa and the new exponent bits form a non-normalized floating point number. The non-normalized floating point number obtained through the operation of the floating point partial multiplier-adder is directly used as the input of the multi-input adder, and the normalized floating point number meeting the normalization requirement is obtained after the addition operation.
The multiply-add computing device provided by the embodiment is optimally designed from the aspect of circuit structure, at least two floating point part multipliers 1 and one multi-input adder 2 are arranged, each floating point part multiplier 1 only comprises a sign bit exclusive-or circuit 11, a mantissa multiplier 12 and an exponent adder 13 and does not comprise a normalization module, a non-normalization floating point number is output after the normalization floating point number is received and multiplied, the non-normalization floating point number is added by the adder and the normalization floating point number is output, the multiply-add computing device is optimized from the aspect of hardware circuit, the operating efficiency of the multiply-add computing device is improved, and the area and the power consumption of the hardware circuit are reduced.
On the basis of the above embodiment, further, the adder includes: the device comprises an exponent comparator, a mantissa shifter, a rounding module and a normalization module, wherein the exponent comparator, the mantissa shifter, the rounding module and the normalization module are used for accumulating input non-normalized floating point numbers and outputting normalized floating point numbers.
Specifically, the non-normalized floating point number output by the floating point part multiplier is used as the input of the multi-input adder, wherein the exponent part of the input non-normalized floating point number is firstly aligned by the exponent comparator according to the comparison result through the mantissa shifter, then accumulated by the fixed point adder, and the accumulated result is subjected to normalization processing through the normalization module after passing through the rounding module, so that the normalized floating point number can be output.
The multiply-add computing device provided by the embodiment of the invention utilizes the floating point part multiplier to multiply the input normalized floating point number, inputs the obtained non-normalized floating point number into the multi-input adder, then accumulates the input non-normalized floating point number and outputs the normalized floating point number through the exponent comparator, the mantissa shifter, the rounding module and the normalization module in the multi-input adder, and reduces the hardware cost by optimizing the floating point number multiplication at the circuit level, thereby improving the operation efficiency, reducing the extra normalization cost and reducing the power consumption.
On the basis of the above embodiment, further, the rounding mechanism of the rounding module in the adder includes: truncated rounding, rounded up, rounded down or rounded nearest.
Specifically, truncation rounding, rounding-up, rounding-down and rounding-up are four different data processing methods for rounding data. For convenience of explanation, the decimal numbers 0.4, 0.5, 0.6, 1.5, 2.4 and 2.5 are used to describe the results of rounding for the four rounding modes respectively.
Table 1 example of results of data processing with different rounding modes
Table 1 shows examples of results of data processing performed by different rounding manners, and as shown in table 1, a round-off manner is to completely omit data after a decimal point from numbers before the decimal point, and the round-off manner is simple in circuit implementation, can effectively reduce the difficulty of circuit design, improve the calculation efficiency, and reduce the power consumption of the circuit, but is low in calculation accuracy and suitable for a calculation scenario with low accuracy requirement. The three ways of rounding up, rounding down and rounding up to the nearest are four-round six-in, wherein the difference lies in the processing of five, the rounding up is to carry out carry calculation on five-way larger numbers, 0.5 is changed into 1 through rounding up, 1.5 is changed into 2 through rounding up, and the like, and the description is omitted here; the rounding-down is to carry out truncation calculation on five-way smaller numbers, wherein 0.5 is changed into 0 through rounding-down, 1.5 is changed into 1 through rounding-down, and the like, and the description is omitted; the nearest rounding is further changed to the even rounding, namely five-way nearest even numbers are rounded, for example, 0.5 is between 0 and 1, wherein 0 is an even number, so that 0.5 is changed to 0 through the nearest rounding, 1.5 is between 1 and 2, wherein 2 is an even number, so that 1.5 is changed to 2 through the nearest rounding, similarly 2.5 is changed to 2 through the nearest rounding, 3.5 is changed to 4 through the nearest rounding, and the like, and therefore, the description is omitted here. Due to the difference of the five processing modes, the data processed by the rounding-up mode, the rounding-down mode and the nearest rounding mode has respective characteristics in terms of errors: rounding up carries the five-way larger number, so the data as a whole is shifted up; rounding down rounds off the five smaller numbers so the data as a whole is biased downward; in the data to be rounded recently, the odd-numbered digits in the integer part are rounded up and the even-numbered digits in the integer part are rounded down, so that the data deviation caused by the rounding method is reduced on the whole, and the precision of the data is improved.
The multiply-add computing device provided by the embodiment comprises a plurality of rounding mechanisms, so that the difficulty of circuit design can be reduced on the basis of meeting the requirements of different operations, and the operation efficiency and accuracy are improved.
Based on the above embodiment, further, the exponent comparator finds the largest exponent value in the input data, and the mantissa shifter performs a shifting operation according to the largest exponent value to align mantissa bits.
Specifically, the input normalized floating point number is multiplied by a floating point part multiplier, and then the output non-normalized floating point number is used as the input of the multi-input adder, wherein the exponent part of the input non-normalized floating point number firstly obtains a maximum exponent value through an exponent comparator, then the maximum exponent value is subtracted from each input exponent to obtain an offset, the decimal point of the mantissa value is shifted to the left according to the offset, the position of the decimal point on the circuit is fixed, and therefore each input mantissa part is shifted to the right through a mantissa shifter according to the offset, and the requirement of mantissa alignment is met. And accumulating the result by the fixed-point adder, rounding the accumulated result by a rounding module, and normalizing the result by a normalization module to output a normalized floating-point number.
The exponent comparator is used for obtaining the maximum exponent value in each input, and then mantissa alignment is carried out according to the difference between the maximum exponent value and each exponent value, so that the exponent part of the result is determined to be the maximum exponent value, corresponding mantissa values can be obtained by adding after the mantissas are aligned, a fixed-point adder can be directly used during mantissa addition, and the operation efficiency is further improved.
On the basis of the above embodiment, further, the adder further includes a ripple register, and the results of the mantissa shifter and the exponent comparator are stored to increase the pipeline of the adder.
The operation of the convolutional neural network is composed of a large number of successive multiplication and addition, and therefore, the operation efficiency of the multiplication and addition calculation device is also affected by the operation frequency. In the multiply-add computing device provided by the embodiment of the invention, the pulse register is added in the multi-input adder to store the results of the mantissa shifter and the exponent comparator, a plurality of normalization floating point numbers input each time are changed into non-normalization floating point numbers to be input into the multi-input adder after being multiplied by the floating point partial multiplier, the comparison result is stored in the pulse register after passing through the exponent comparator in the multi-input adder, after passing through the mantissa shifter, the shifted mantissa is stored in the corresponding pulse register, thus, these data are stored in the pulse register, the multiply-add calculating device can receive the next input to start a new round of operation, and the data in the pulse register continues to carry out the following operation, enters the rounding module for rounding operation, and then enters the normalization module for normalization operation to output the normalized floating point number.
The result of the mantissa shifter and the result of the exponent comparator are stored by adding the pulse register in the adder, so that the operation frequency can be effectively improved, and the overall operation efficiency is improved.
In addition to the above embodiments, the normalization module performs normalization processing on the calculation result at the end of the adder operation.
The multiplication and addition computing device provided by the embodiment of the invention removes normalization modules of all intermediate links and only reserves a normalization module at the tail end of the adder, so that the multiplication and addition operation in the whole operation process is fixed-point operation, the complexity of the calculation is greatly reduced, the operation efficiency is improved, and the normalization module is added at the tail end of the adder to ensure that the output is the normalization floating point number which meets the standard.
Fig. 3 is a schematic diagram of a sixteen-input multiply-add computing apparatus according to an embodiment of the present invention, and fig. 4 is a schematic diagram of an eight-input adder in the sixteen-input multiply-add computing apparatus according to an embodiment of the present invention, as shown in fig. 3 and fig. 4, the multiply-add computing apparatus includes eight floating-point partial multipliers 301 and an eight-input adder 302.
The floating-point partial multiplier is composed of a mantissa multiplier and an exponent adder, and includes an exclusive or circuit of sign bits. The output of the floating-point partial multiplier is made up of non-normalized mantissas, exponents and sign bits and is input to a multiple-input adder. The eight-input adder includes: an exponent comparator 401, a mantissa shifter 402, a pulse register 403, a rounding module 404, a normalization module 405, and the like. In the implementation process, the eight-input adder can select the rounding mode of internal implementation according to the work requirement.
In operation, the output of the upper stage floating-point partial multiplier is used as input to the eight-input adder. The 8 indexes are firstly compared with the index comparator to generate the value of the maximum index, and then the maximum index is subtracted from each input index to obtain different offset. Then, the mantissa part is shifted to the right according to the offset, and the requirement of mantissa alignment is completed. And calculating the sum of the aligned mantissas by a mantissa summing circuit. And finally obtaining a normalized final result through a normalization module.
The multiply-add computing device provided by the embodiment of the invention is provided with eight floating point part multiply-add devices and an eight-input adder, sixteen normalized floating point numbers can be input to carry out multiply-add operation and then output normalized floating point numbers meeting the standard, two sections of stream are realized by adding the pulse register 403, the operation frequency is improved, the whole circuit area is further reduced, the power consumption is reduced, and the operation efficiency is improved.
Fig. 5 is a schematic flowchart of a floating-point multiply-add calculation method according to an embodiment of the present invention, and as shown in fig. 5, the method includes:
and step 30, performing addition operation on the non-normalized floating point number to obtain a normalized floating point number.
Specifically, firstly, inputting a normalized floating point number, then performing multiplication on the received normalized floating point number, but directly performing addition operation by using the obtained non-normalized floating point number without performing normalization processing during the multiplication operation, and performing normalization processing after the addition operation is completed to obtain the normalized floating point number meeting the standard. Because the normalization processing is only carried out at the end in the operation process, the step of carrying out the normalization processing on the multiplication operation is saved, and the calculation efficiency is improved.
On the basis of the foregoing embodiment, further, the step of obtaining the non-normalized floating point number specifically includes:
the sign bit of the non-normalized floating point number is obtained by the sign bit of the normalized floating point number through a sign XOR circuit;
obtaining a non-normalized mantissa bit of the non-normalized floating point number by passing the mantissa bit of the normalized floating point number through a mantissa multiplier;
obtaining the exponent number of the non-normalized floating point number by the exponent number of the normalized floating point number through an exponent adder;
and outputting the non-normalized floating point number consisting of the sign bit, the non-normalized mantissa bit and the exponent bit.
The floating-point number is composed of a sign bit, a mantissa bit and an exponent bit, and the multiplication of the floating-point number is as follows: carrying out XOR operation on the sign bits to obtain positive and negative signs when the sign bits are the same; multiplying the mantissa bits; the exponent bits are then added. Therefore, after receiving the input normalized floating point number, carrying out XOR operation on the sign bit of the floating point number by using a coincidence XOR circuit to obtain a new sign; multiplying the mantissa bits of the input normalized floating point number by a mantissa multiplier to obtain a new mantissa; an exponent adder is used to add the exponent bits of the normalized floating point number to obtain a new exponent. After the mantissa bits are multiplied, the resulting mantissa bits may have not met the normalization requirement and are therefore referred to as non-normalized mantissas. The floating point number composed of the new sign, mantissa, and exponent is referred to as a non-normalized floating point number. And taking the obtained non-normalized floating point number as the input of the multi-input adder, and obtaining the normalized floating point number meeting the standard after addition operation.
According to the method provided by the embodiment of the invention, the normalization step in the multiplication operation of the normalized floating point number is simplified, and the normalized floating point number is output after the addition operation is carried out, so that the efficiency of the multiplication and addition calculation of the floating point is improved.
On the basis of the foregoing embodiment, further, the step of performing addition operation on the non-normalized floating point number to obtain a normalized floating point number specifically includes:
receiving all of the non-normalized floating point numbers;
comparing the indexes of the non-normalized floating point numbers to obtain the maximum index;
respectively subtracting the maximum exponent and the exponent of each non-normalized floating point number to obtain the offset of each non-normalized floating point number;
aligning mantissas of each non-normalized floating point number according to the offset;
carrying out signed summation on each non-normalized mantissa after alignment to obtain a sum;
and the sum and the exponent bits are processed by a rounding module and a normalization module to obtain a normalized floating point number and output the normalized floating point number.
The received normalized floating point number is changed into a non-normalized floating point number after multiplication operation and continues to be subjected to addition operation, and when the addition operation is carried out: firstly, receiving all non-normalized floating point numbers; comparing the exponent bits of the non-normalized floating point numbers to obtain the maximum exponent number; then, carrying out subtraction on the maximum exponent and each exponent, wherein the difference value obtained by the subtraction is the offset of the mantissa part of each non-normalized floating point number; shifting and aligning the mantissa part of each non-normalized floating point number according to the offset; then carrying out signed addition operation on each aligned non-normalized mantissa to obtain a sum; the obtained sum may not meet the normalization requirement, so the result also needs to be subjected to the rounding module and the normalization module to meet the normalization requirement, and a normalized floating point number is obtained and output.
The method provided by the embodiment of the invention has the advantages that by simplifying the normalization step in the multiplication operation of the normalized floating point number, the mantissa digits are shifted and aligned by comparing the exponent digits to calculate the offset in the addition operation, then signed addition operation is carried out on the aligned mantissa digits, and the normalized floating point number meeting the regulation is obtained by passing the obtained sum and the exponent digits through the rounding module and the normalization module, so that the efficiency of the multiplication and addition calculation of the floating point is improved.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. A multiply-add computing device comprises at least two floating point part multipliers and a multi-input adder, and is characterized in that the floating point part multipliers consist of sign bit exclusive-or circuits, mantissa multipliers and exponent adders, the floating point part multipliers receive normalized floating point numbers and carry out multiplication to obtain non-normalized floating point numbers, the adders accumulate the non-normalized floating point numbers and output the normalized floating point numbers, the non-normalized floating point numbers consist of sign bits, non-normalized mantissa and exponent parts, and the normalized floating point numbers consist of sign bits, normalized mantissa and exponent parts; wherein the adder includes: the device comprises an exponent comparator, a mantissa shifter, a rounding module and a normalization module, wherein the exponent comparator, the mantissa shifter, the rounding module and the normalization module are used for accumulating input non-normalized floating point numbers and outputting normalized floating point numbers.
2. The apparatus of claim 1, wherein the rounding mechanism of the rounding module in the adder comprises: truncated rounding, rounded up, rounded down or rounded nearest.
3. The apparatus of claim 1 wherein the exponent comparator identifies a largest exponent value of the input data, and the mantissa shifter shifts the mantissa bits according to the largest exponent value.
4. The apparatus of claim 1, wherein the adder further comprises a ripple register to store the results of the mantissa shifter and the exponent comparator to increase the pipeline of the adder.
5. The apparatus according to any one of claims 1 to 4, wherein the normalization module normalizes the calculation result at an end of the operation of the adder.
6. The apparatus of claim 5 wherein said multiply-add computing means comprises eight floating-point partial multipliers and an eight-input adder.
7. A floating-point multiply-add calculation method implemented by the multiply-add calculation apparatus according to any one of claims 1 to 6, comprising:
receiving at least four normalized floating point number inputs;
performing multiplication operation on the normalized floating point number to obtain a non-normalized floating point number;
performing addition operation on the non-normalized floating point number to obtain a normalized floating point number;
the step of performing addition operation on the non-normalized floating point number to obtain a normalized floating point number specifically includes:
receiving all of the non-normalized floating point numbers;
comparing the indexes of the non-normalized floating point numbers to obtain the maximum index;
respectively subtracting the maximum exponent and the exponent of each non-normalized floating point number to obtain the offset of each non-normalized floating point number;
aligning mantissas of each non-normalized floating point number according to the offset;
carrying out signed summation on each non-normalized mantissa after alignment to obtain a sum;
and obtaining a normalized floating point number by the sum and the exponent number through a normalization module and outputting the normalized floating point number.
8. The method of claim 7, wherein the step of multiplying the normalized floating point number to obtain the non-normalized floating point number is specifically:
the sign bit of the non-normalized floating point number is obtained by the sign bit of the normalized floating point number through a sign XOR circuit;
obtaining a non-normalized mantissa bit of the non-normalized floating point number by passing the mantissa bit of the normalized floating point number through a mantissa multiplier;
obtaining the exponent number of the non-normalized floating point number by the exponent number of the normalized floating point number through an exponent adder;
and outputting the non-normalized floating point number consisting of the sign bit, the non-normalized mantissa bit and the exponent bit.
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