KR100929423B1 - Floating-Point Complex Arithmetic Unit - Google Patents

Abstract

The present invention relates to a floating-point compound arithmetic unit. When a floating-point A * C + B arithmetic operation is performed by a single instruction, a multiplier having the longest arithmetic operation time among the three arithmetic operation pipelines is executed in two cycles The Booth algorithm is used to reduce the size of the chip and to improve the operation speed, so that it can be incorporated into a small-sized, high-performance computing device in a portable device having a built-in graphic function.

Floating Point, Booth Algorithm, Partial Product, Chip Area, Uncoded

Description

Complex operation unit for floating point with multiply-add unit

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified representation of a complex arithmetic unit for a typical floating point A * C + B operation.

2 is a block diagram illustrating a multiplier of a floating-point complex operation apparatus according to the present invention.

4 is a diagram illustrating a method of expanding and removing a sign bit in a floating-point compound operation apparatus according to the present invention.

5 is a flowchart illustrating a multiplication process of a floating-point complex operation apparatus according to the present invention.

   Description of the Related Art [0002]

10: multiplication unit 20:

30: Normalization unit

110, 12: multiplier 120, 14: aligner

112: partial product generation means 114: additive tree means

116: Carry hold addition means

More particularly, the present invention relates to a floating-point multiplication and accumulation apparatus, and more particularly, to a floating-point multiply and accumulator, To a complex floating-point arithmetic unit for reducing the size of a chip and improving the operation speed by using Booth's algorithm so that an operation can be performed in two cycles during processing.

Floating point units are typically used for graphics accelerators, digital signal processors, and computers requiring high performance.

In recent years, with the development of semiconductor technology, as the degree of integration of a chip has increased, a floating-point arithmetic unit can be embedded in a chip together with a central processing unit, so that a floating-point arithmetic unit has become an important element of a main arithmetic unit . Since floating-point arithmetic units are built in the central processing unit, only basic arithmetic units such as addition / subtraction and multiplication are built in. Therefore, the floating-point multiplier greatly affects the overall floating-point operation.

Meanwhile, in the floating-point multiply operation, the processing of the mantissa part is performed in the order of (1) multiplication, addition of carry and sum generated in the multiplication, normalization, and rounding And second, it consists of four steps of multiplication, addition, rounding, and normalization.

In the IEEE-754 standard for binary representation of floating-point numbers for performing the above-mentioned process, there are a 32-bit single precision format and a 64-bit double precision format. The single-precision format has a sign bit of 1 bit, an exponent of 8 bits, and a mantissa of 23 bits. The double-precision format has a 1-bit sign bit, an 11-bit exponent portion, and a 52-bit mantissa portion. Here, the normalized operand (A) according to the IEEE standard can be expressed as follows.

Where S: sign, M: mantissa, and E: exponent, respectively.

Where s is the sign bit for the mantissa, M is the mantissa of the absolute value type, and E is the exponent of the bias type. The normalized form of the mantissa is a state in which the most significant bit (MSB) is 1, and in the floating-point representation, this MSB is omitted and is called a hidden bit.

A multiply-add unit (MAC) that performs normal floating-point multiply and accumulate is to combine the three values A, B, and C by adding or subtracting one value B from the product of the other values A and C. An arithmetic circuit having a multiplier and an adder can perform such a MAC operation in individual steps, multiply the values A and C using a multiplier, round the result, and then use the adder to multiply the result of the multiplication The value B is added or the value C is subtracted from the result of the multiplication.

Optionally, the fused MAC device may perform multiplication and accumulation in parallel, and may be implemented in the IEEE Journal of Solid-State Circuits, by omitting the rounding of the product to improve the processing performance (latency and accuracy) vol. 25, No. 5, October 1990, Hokenek et al., "Second-Generation RISC Floating Point with Multiply-Add Fused", can be used in parallel with the multiplication of the values A and C so that the value B accumulates with the product A * A floating-point MAC device that performs bit alignment on a value B is disclosed.

The result A * C + B is accumulated without rounding or truncating the intermediate product A * C, which can introduce errors. Incidentally, the leading zeros predicts the shift required to normalize the result A * C + B according to the floating-point representation while the value B is accumulated with the product A * C such that the result A * C + B is normalized immediately after accumulation . Thus, fused MAC devices are faster and more accurate than multipliers and accumulators that are used sequentially overall.

Figure 1 is a simplified representation of a computing device for a typical floating point A * C + B operation.

A multiplier 10 for determining the product Ma * Mc of the values A and C and for aligning the product Ma * Mc and the mantissa Mb of the value B to accumulate as shown here, and a multiplier 10 for multiplying the mantissa Mb and the product Ma * An accumulation unit 20 for accumulating Mc, accumulative accumulation in the accumulation unit 20, performing a leading zero or leading 1 / zero prediction, normalizing or rounding the result, or detecting overflow and underflow exceptions And a normalization unit 30 for performing a normalization process.

The multiplier 10 multiplies the multiplier Ma to determine the product Ma * Mb of the values A and B, and the mantissa Mc of the value C to accumulate with the product Ma * Mb, And an aligner 14 for classifying and simplifying the respective MACs according to the magnitude of the value B for the product A * C with the exponent difference (Ea + Ec) -Eb pointed to by Aa.

In the case where the floating-point A * C + B operation is performed by a separate multiplier and an accumulator, there is a problem that a calculation speed and a large design area are required because more than two instructions are required. the number of unsigned multipliers is increased and the operation speed is delayed by using a three-stage multiplier.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a multiprocessor which has a longest operation time among the three- Point complex calculation device for reducing the scale of the chip and improving the operation speed by using the booth algorithm so that the calculation can be performed in two cycles in the no-boil lubrication process.

A multiplier for determining a product of a first value and a second value of a floating point and a multiplier for determining a product and a sorter for sorting a mantissa for accumulation of a third value; And a normalizer for normalizing the result of accumulation, wherein the multiplier of the multiplier multiplies the multiplication result of the first multiplication operation in the first cycle in which the first multiplication operation is started A partial product generation means for generating a partial product by a booth algorithm by dividing the number of 2n bits of the multiplication factor of 2n bits by a first value and a second value to be multiplied, a partial product generation means for adding the partial product generated by the partial product generation means, And a first carry and a first carry output from the adder tree means in the first cycle are fed back to the adder tree means to generate the first carry and the first carry, And carry carry addition means for finally adding and outputting the second sum and the second carry.

In the above, when dividing the 2n bits of the product by the partial product generation means, a value " 0 " is inserted into the upper 2 bits of the lower n bits in the first cycle to divide it into n + 2 bits, n bits, and performs processing.

In addition, the partial product generation means applies sign bit congruence when processing partial products.

The carry hold addition means is characterized in that a 3: 2 array technique is applied.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention is not limited to the scope of the present invention, but is merely an example, and the same reference numerals and names are used for the same parts as in the conventional configuration.

2 is a block diagram showing a multiplier of a floating-point arithmetic unit according to the present invention.

The present invention relates to a single-precision unsigned floating-point arithmetic unit for determining a product Ma * Mc of values A and C as shown in FIG. 1 and a multiplier Mb for aligning the mantissa Mb of the value B to accumulate the product Ma * An accumulator 20 for accumulating the product Mb and a product Ma * Mc of the value B, a leading zero or leading 1 / zero prediction for normalizing the result accumulated in the accumulator 20, And performs normalization or rounding of the floating-point A * C + B and accumulation and accumulation of floating point A * C + B through the same process as that of the normalization unit 30 for detecting overflow and underflow exception.

2, the multiplier 110 multiplies the product Mb of the value B to accumulate with the product Ma * Mc And an aligner 120 for classifying and simplifying each MAC according to the magnitude of the value B for the product A * C by the difference in exponent (Ea + Ec) -Eb indicated by the exponents of the values A, B and C.

The multiplier 110 divides the multiplication factor of 2n bits in the first and second values for the multiplication operation in the first cycle to generate the partial product by the Booth algorithm, Means 114 for adding a partial product generated by the partial product generating means 112 to generate a first sum and a first carry; And carry carry addition means 116 for feeding back the first sum and the first carry to the additive tree means 114 to finally add the second sum and the second carry generated in the second cycle and output.

When dividing the multiplication number by the partial product generation means 112, the multiplication operation is performed in two cycles by dividing the number of 2n bits by n bits in order to reduce the chip area. At this time, as shown in FIG. 3, in the first cycle, n + 2 bits are formed by including the lower n bits of the multiplication number and the upper 2 bits of the value " 0 & 2 + 1 by generating a partial product of n / 2 + 1 by correcting the erroneous calculation result generated by applying the Booth algorithm to the partial product, and shifting the upper n bits to the lower n bits in the second cycle, and then generating the partial products.

In order to reduce the burden on the sign bit expansion when processing the partial products having the sign, the sign bit is expanded by applying a sign bit-wise method so as to expand the sign bit as shown in (A) Bit extensions are removed.

The operation according to the present invention will be described with reference to a flowchart showing a multiplication process of the floating-point arithmetic unit of FIG.

In the first cycle, the aligner 120 receives the exponents of the values A, B, and C, performs Ea + Ec between the exponents of the values A and B, and determines the amount of displacement to match the exponent and the digit of the value B, Moves the mantissa of the value B to the number of digits of the result of the product Ma * Mc of the values A and C.

On the other hand, in the multiplier 110, in the first cycle, in order to generate the partial product of the values A and C, the partial product generating means 112 includes two bits of the lower n bits and the upper " 0 " Bit error correction is performed by applying a Booth algorithm for processing sign numbers when forming an unsigned number bit, thereby generating a partial product of n / 2 + 1, and the mantissa tree means 114 generates a first sum And a first carry.

Then, in the second cycle, the upper n bits are shifted to the lower n bits and then 7 partial products are generated to feed back the first sum and the first carry to the mantissa tree means 114 and the value generated in the sorter 120 And output to the mantissa tree means 114 to generate a second sum and a second carry finally added by the carry holding means 116. [

The second sum and the aligned values of the second carry and aligner 120 output from the carry holding means 116 in the third cycle are then output to the accumulator 20.

As described above, the accumulation unit 20 accumulates the product Ma * Mc with the mantissa Mb of the value B and outputs a leading zero or leading 1 / zero prediction to normalize the accumulated result in the normalization unit 30 And performs A * C + B multiplication and accumulation of the floating point through the process of normalizing or rounding the result or detecting the overflow and underflow exceptions.

As described above, according to the present invention, when a floating point A * C + B operation is performed using a single instruction, a multiplier having the longest operation time among the three stages of the operation pipeline can be operated in two cycles The booth algorithm is used to reduce the size of the chip and to improve the operation speed. Thus, there is an advantage that it can be embedded as a small-area, high-performance computing device in a portable device having a built-in graphic function.

Claims (4)

A multiplier for determining a product of a first value of a floating point and a second value, a multiplier for determining a product and a sorter for sorting a mantissa for accumulation of a third value, and a multiplier for multiplying a third value, A floating-point compound arithmetic unit composed of an accumulating unit for accumulating the product and a normalizing unit for normalizing the accumulated result, Wherein the multiplier of the multiplier multiplies the multiplication factor of 2n bits by the first value and the second value which are to be multiplied in the first cycle to start the multiplication operation by n bits and generates a partial product by the Booth algorithm, , Addition tree means for adding a partial product generated by the partial product generation means to generate a first sum and a first carry; A carry sum accumulating means for accumulating a first sum and a first carry output from said adder tree means in said first cycle to said adder tree means to finally add and output a second sum and a second carry generated in a second cycle, Wherein the floating-point complex arithmetic operation unit comprises: 2. The method of claim 1, wherein, when separating the 2n bits of the product number in the partial product generation means, a value " 0 " is inserted into the upper two bits of the lower n bits in the first cycle, And shifting the upper n bits to the lower n bits to process the floating-point complex operation unit. The apparatus of claim 1, wherein the partial product generating unit applies sign bit normalization when processing partial products. 2. The complex arithmetic unit of claim 1, wherein the carry hold addition means applies a 3: 2 array technique.

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