JPH0732347B2 - Circuit type digital filter - Google PatentsCircuit type digital filter
- Publication number
- JPH0732347B2 JPH0732347B2 JP60142903A JP14290385A JPH0732347B2 JP H0732347 B2 JPH0732347 B2 JP H0732347B2 JP 60142903 A JP60142903 A JP 60142903A JP 14290385 A JP14290385 A JP 14290385A JP H0732347 B2 JPH0732347 B2 JP H0732347B2
- Prior art keywords
- digital filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
- 238000010586 diagrams Methods 0.000 description 19
- 125000004122 cyclic group Chemical group 0.000 description 11
- 238000005070 sampling Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 241001442055 Vipera berus Species 0.000 description 8
- 230000000295 complement Effects 0.000 description 4
- 230000000051 modifying Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reactions Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000002542 deteriorative Effects 0.000 description 1
- 238000000034 methods Methods 0.000 description 1
Description: FIELD OF THE INVENTION The present invention relates to a recursive digital filter having a feedback path used to process a sampled digital signal.
2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional recursive digital filter. Reference numeral 1 is an input terminal for inputting a digital signal sampled at a sampling period T, and 2 is an output terminal. 3 is a delay circuit for delaying the signal by the sampling period T,
Reference numeral 4 is a multiplication circuit for multiplying the signal obtained from the delay circuit 3 by a multiplier K to obtain a feedback path output. Reference numeral 5 is an addition of the input signal obtained from the input terminal 1 and the output of the multiplication circuit 4 to the output terminal 2 and the delay circuit 3.
Is an adder circuit that leads to.
The operation of the conventional recursive digital filter configured as described above will be described by using the Z-transform formula representing a discrete-time system.
In the Z conversion formula, a delay operator indicating a time delay of m times (m is an integer) sampling period mT is represented by Z − m. Therefore the 7th
The transfer equation H (z) showing the characteristics of the conventional recursive digital filter is as follows.
Generally, in a system having a feedback path in which a signal is fed back from the output side to the input side as shown in FIG. 7, the stability of the system is that the feedback path gain is smaller than 1. Consider this in the conventional example of FIG.
Input signal of input terminal 1 at time tn is un, output terminal 2 is
If the output signal of is vn, the following equation is obtained from FIG.
vn = un + Kvn -1 (2) Now, when there is no input from time t 0 , that is, when n ≧ 0, un =
If 0, the output signal vn (n ≧ 0) is given by the following equation.
vn = Kn · v 0 , n ≧ 0 (3) From this equation (3), the system diverges even if there is no input and K> 1, and even if K = 1, vn = v 0 (Constant)
Then the system does not converge. However, when K <1, if n is sufficiently large, v 0 = 0 and the system stabilizes.
From the above, in the recursive digital filter having the feedback path as in the conventional example of FIG.
If smaller, system stability is guaranteed.
However, in the case of digital signal processing, the number of digits during signal transmission (however, in digital signal processing, one digit is 1 bit) is a problem. If precision is required, the number of digits may be increased, but considering the circuit scale, it is necessary to add a rounding operation to an appropriate number of digits (effective number of digits) to limit the number. The method of this rounding operation includes truncation and rounding. The truncation operation is an operation that truncates a portion smaller than the least significant digit of the significant digit, that is, sets it to zero, and the rounding operation rounds up if there is a bit in the digit one less than the least significant digit of the significant digit. These two operations are rounding down, and the circuit scale required for these two operations is small and is an effective method.
Problems to be Solved by the Invention However, in the above-mentioned configuration, even if the stability is guaranteed, the system may not be stable due to an error due to the rounding operation of the output of the feedback path. Hereinafter, description will be made with reference to the drawings. However, there are several methods for expressing a negative number in digital signal processing. Among them, the method using the two's complement expression is the most general, so the following numbers are expressed in the two's complement. To do.
FIG. 8 is an input / output diagram of a rounding operation by truncation. The number rounded on the horizontal axis x and the number rounded on the vertical axis y are taken. However, regarding the unit of x and y, the minimum identification amount that can be represented by the significant digit of the rounded number y is 1, and the same applies to the following rounding operations.
Now, in the conventional example of FIG. 7, assuming that the output of the multiplication circuit 4 at time tn is wn, the output signal vn −1 from the output terminal 2 is used, and wn = K · vn −1 , 0 <K <1 … (4) Now consider when vn -1 is negative.
For example, if vn −1 = −3, then wn = −3K (5) from Eq. (4). At this time, if 2/3 <K <1 (6), then x in the input / output diagram of FIG. 8 becomes -3 <x <-2 (7). y = -3 (8), and as a result, when there is no input, that is, when un = 0, vn = vn -1 = -3 (9), and because of the rounding operation by truncation in FIG. The output signal vn does not converge to zero, causing a limit cycle. Furthermore, even if vn −1 = −1, 0 <K
It can be seen that vn does not converge to zero in the range of <1.
Next, the rounding operation by rounding off shown in FIG. 9 will be considered in the same manner as the rounding operation by rounding down.
Then, if 5/6 <K <1 (11), then vn = -3 (12), and it does not converge to zero. Also,
If vn −1 = -1, then In the range of, vn = vn -1 and it does not converge. further,
In the case of FIG. 9, the same can be said even if vn −1 , that is, x is positive. For example, Then, if 5/6 ≦ K <1, then vn = vn −1 = 3 (14), which does not converge.
In view of the above points, the present invention requires a large number of bits for signal transmission because it has a feedback path, but a rounding type digital filter in which rounding operation must be performed in consideration of the circuit scale. In the above, there is provided a recursive digital filter which does not cause a limit cycle even in a non-input state due to an error due to the rounding operation.
Means for Solving the Problems The present invention is a cyclic digital filter having a feedback path having a predetermined feedback gain, and the output of the feedback path is limited to a predetermined number of significant digits. If the minute value below the significant digit is less than or equal to the value obtained by multiplying the minimum discriminable amount that can be represented by the significant digit by the feedback gain of the feedback path, the minute value below the significant digit is discarded and the minute value below the significant digit is discarded. The present invention provides a recursive digital filter characterized by including rounding means for rounding up if the minimum value is larger than a value obtained by multiplying the minimum discrimination amount by a feedback gain.
Operation The present invention makes it possible to reduce the quantization error in relation to the feedback gain as well as the limit cycle due to the rounding error does not occur even in the recursive digital filter having the feedback path by the above means.
First Embodiment FIG. 1 is a block diagram of a recursive digital filter according to a first embodiment of the present invention. Reference numeral 6 is an input terminal to which the digital signal sampled at the sampling cycle T is input, and 7 is an output terminal. 8 is a signal sampling period T
Delay circuit for delaying only by 9, 9 is a multiplier K to the output of the delay circuit 8
Multiplying circuit (where 0 <K <1), 10 is a detection circuit that detects whether or not a value less than a significant digit is truncated according to the absolute value of the output of the multiplication circuit 9 and outputs a detection signal, 11 is an input terminal 6 is an adder circuit for adding the signal obtained from 6 and the output of the multiplication circuit 9 with the digits below the significant digit rounded off and the detection signal obtained from the detection circuit 10 to lead to the output terminal 7 and the delay circuit 8.
The detection signal output from the detection circuit 10 is a multiplier K which is the feedback gain of the feedback path with respect to the absolute value of the output of the multiplication circuit 9 and the value below the effective digit is the minimum discrimination amount that can be represented by the effective digit.
If the value is equal to or smaller than the value obtained by multiplying by, the value greater than or equal to the significant digit is rounded down, and if it is larger than the value obtained by multiplying the minimum discrimination amount by the multiplier K, the value is rounded up. The detection signal of the detection circuit 10 is used as a carry from the value below the significant digit with respect to the value limited by the number of significant digits in the output of the feedback circuit output from the multiplication circuit 9 to add circuit 1
Added in 1. The rounding operation as described above is performed by the multiplication circuit 9
Since it is performed by the absolute value of the output, the input / output diagram of the rounding operation is represented as shown in FIG. Here, the unit of the number to be rounded and the number y to be rounded is represented by the minimum discriminative amount that can be represented by the effective digit of the feedback path output whose digit number is limited.
As can be seen from FIG. 2, the rounding operation of this embodiment is performed on the absolute value of the feedback path output. For this reason, it is necessary to distinguish the detection operation depending on whether the feedback path output is positive or negative. This is because, in digital signal processing, the two's complement representation is generally used as the number representation. This will be explained using a simple example. First, consider rounded numbers such as +3.75 and -3.75 that have the same absolute value but different positive and negative polarities. Then, round down the numbers below the decimal point in the absolute value state, and add 2 to +3 and -3. I want to get a number. Now, if +3.75 and −3.75 are represented by a binary number in a two-bit two's complement representation, Becomes In order to round these two numbers to valid numbers of +3 and -3 respectively to obtain binary numbers of (001) 2 and (101) 2 , respectively, the detection signal output from the detection circuit 10 has a rounded number. It must be 0 for +3.75 and 1 for -3.75, but the detection circuit performs the above detection operation.
Can be easily configured using a subtraction circuit or an addition circuit, a gate circuit, a switch circuit, or the like.
Next, the reason why the limit cycle does not occur when the rounding operation as shown in FIG. 2 is performed on the feedback path output by the detection circuit 10 provided as described above will be described.
In the configuration of the embodiment of FIG. 1, the output signal v converges to zero when there is no input, that is, when the input signal u is zero. In other words, the necessary and sufficient condition for the limit cycle not to occur is that 0 <K <1, v = 0, [Kv] = 0 …… (16) v ≠ 0, | [Kv] | < | v | …… (17) Is. It suffices if the above conditions can be executed by the rounding operation shown in FIG. First, when v = 0, Kv = 0, so the second
From the figure, [Kv] = 0 and the condition of Eq. (16) is satisfied. Next, consider the case when v ≠ 0. First, when | v | ≦ 1, | Kv | ≦ K, and therefore [Kv] = 0 from FIG. 2, and therefore the equation (17) is satisfied. Now, look at the case of | v |> 1. From Figure 2, Kv and [K
When the relation of v] is calculated, it becomes the following formula.
| [Kv] | + K-1 <| Kv | ≦ | [Kv] | + K …… (18) From equation (18), | [Kv] | is | [Kv] | <| Kv | -K + 1 …… (19 ). On the right side of the equation (19), from 0 <K <1, | Kv | −K + 1 = K (| v | −1) +1 (20) is obtained. Now, from | v |> 1, the right side of equation (19) becomes K (| v | −1) +1 <| v | −1 + 1 = | v | ... (21). Therefore, it is understood from the equations (19) to (21) that the condition of the equation (17) is satisfied even when | v |> 1.
As described above, in the present embodiment of FIG. 1, if the detection circuit 10 is provided so as to perform the rounding operation as shown in FIG. 2, a cyclic digital signal which does not cause a limit cycle even if the feedback path output is rounded. A filter can be constructed.
Next, a second embodiment of the present invention will be described. The block diagram showing the configuration of the present embodiment is the same as the block diagram of the first embodiment of the present invention, but the rounding operation of the feedback path output (the output of the multiplication circuit 10 in FIG. 1) is shown in FIG. This is represented by an output diagram.
In order to perform the rounding operation shown in FIG. 3, the detection signal which is the output of the detection circuit 10 is an absolute value state in which the value below the effective digit is absolute value with respect to the absolute value of the output of the multiplication circuit 9 regardless of the feedback gain. The truncation in is performed. In this truncation operation, the output of the detection signal 10 differs depending on the positive and negative polarities of the output of the multiplication circuit 9 as in the first embodiment. That is, since the absolute value of the output of the multiplication circuit 9 is rounded down, the detection signal which is the output of the detection circuit 9 is always zero when the output of the multiplication circuit 9 is positive, but when it is negative, the detection signal of the multiplication circuit 9 is output. If the value below the significant digit of is not zero, the detection signal outputs 1 and outputs zero only when it is zero. The detection circuit 10 that operates as described above does not require an adder / subtractor circuit or the like, and can be configured very simply by a gate circuit. FIG. 4 is a circuit diagram showing one circuit configuration example of the detection circuit 9. In the figure, 12 is an AND gate and 13 is an OR gate. Further, S is a sign bit of the output of the multiplication circuit 9, which is 0 when positive and 1 when negative. D 1 , D 2 , ... to Dl are multiplication circuits 9
Of the outputs, the bit value (0 or 1) of each digit in the digit smaller than the significant digit (l digit, where l is a positive integer) with respect to the significant digit that should be restricted as the feedback path output.
Is. C is a detection signal output from the detection circuit 10. This C becomes S = 0 when the output of the multiplication circuit 9 is positive, and therefore C = 0 by the AND gate 12. In addition, the multiplication circuit 9
When the output is negative, S = 1, but when the value below the significant digit of the output of the multiplication circuit 9 is zero, that is, when the bit value of each digit below the significant digit is all 0, the output of the OR gate 13 is 0. After all C
= 0. However, if the output of the multiplication circuit 9 is negative and the value below the significant digit is not zero, S = 1 and the output of the OR gate 13 also becomes 1. Therefore, the output C of the AND gate 12 becomes 1. As described above, in order to perform the rounding operation as shown in FIG. 3, the detection circuit 10 can be composed of a simple gate circuit as shown in FIG.
Next, it will be explained that the cyclic digital filter does not cause a limit cycle even if the rounding operation in this embodiment is performed.
First, the necessary and sufficient conditions for preventing the occurrence of the limit cycle are expressed by the above-mentioned equations (16) and (17). Therefore, it suffices if the conditions shown by these two equations can be executed by the rounding operation of FIG. First, regarding equation (16), when v = 0, Kv = 0
Therefore, from FIG. 3, [Kv] = 0 and the condition of the equation (16) is satisfied. Next, with respect to equation (17), when v ≠ 0, that is, Kv
When the relation between Kv and [Kv] in FIG. 3 when ≠ 0 is obtained, the following equation is obtained.
| [Kv] | ≦ | Kv | <...  Also, since 0 <K <1 here, | [Kv] | ≦ | Kv | = K | v | < | v | …… (23), which also satisfies the condition of Eq. (17).
As described above, in this embodiment, if the detection circuit 10 is provided so as to perform the rounding operation as shown in FIG. 3, the cyclic digital filter that does not cause the limit cycle even if the feedback path output is rounded. Can be configured
In addition, the detection circuit 10 can be constituted by only a simple gate circuit as compared with the above-described first embodiment of the present invention, which is still effective.
FIG. 5 is a block diagram of a recursive digital filter which is a third embodiment of the present invention. In the figure, the input terminal 6
The output terminal 7 is the same as that of the embodiment shown in FIG. Further, in the delay circuit 14 which delays the signal for one sampling period T, the minimum discriminable amount that can be represented by the output is equal to the minimum discriminable amount that can be represented by an effective digit of the feedback path output of this embodiment. Next, the multiplication circuit 15 multiplies the output of the delay circuit 14 by the multiplier K '(0 <K'<1), and the detection circuit 16 outputs the multiplication circuit.
15 Whether or not the value below the significant digit of the feedback path output is truncated is detected by the absolute value of the output and the detection signal is output. The subtraction circuit 17 subtracts the output of the multiplication circuit 15 from the output of the delay circuit 14 and further adds the output of the detection circuit 16 as a carry amount to obtain a feedback path output. The adder circuit 18 adds the input signal from the input terminal 6 and the feedback path output from the subtractor circuit 17 and guides it to the output terminal 7 and the delay circuit 14. The operation of this embodiment will be described below.
First, the transfer equation H ' ( z ) showing the characteristics of this embodiment is shown in the following equation.
Equation (24) is compared with Equation (1) above compared to H ( z ) in Equation (1).
K of H (z) is only different from that is a (24) H '(z) in 1-K'. Therefore, in FIG.
Rounds the absolute value of the subtraction circuit 17 output,
If the detection signal is guided to the adder circuit 18, the above-mentioned first
It can be seen that this is exactly the same as that of the second embodiment.
In this embodiment, the detection circuit 16 receives the output of the multiplication circuit 15 and guides the detection signal to the subtraction circuit 17. Therefore, since the effective digit of the output of the delay circuit 14 and the effective digit of the signal guided to the adder circuit 18 as the feedback path output are equal, all the values less than the effective digit of the feedback path output are obtained from the output of the multiplier circuit 15, so that the subtraction circuit It is not necessary to calculate 17 for all the digits of the output of the multiplier circuit 15, and only the significant digits of the feedback path output may be calculated. However,
Since the output of the multiplication circuit 15 is guided to the minus side input of the subtraction circuit 17, the positive and negative polarities of the feedback path output which is the output of the subtraction circuit 17 and the positive and negative polarities of the signal to the detection circuit 16 have opposite polarities. Therefore, the operation of the detection circuit 16 may be the same as the operation of the detection circuit 10 in the first and second embodiments, considering that the polarities of the input signals are reversed. However, it should be noted here that the signal rounded by the output of the detection circuit 16 is the output of the feedback path having the feedback gain 1-K 'and is not the output of the multiplication circuit 14 multiplied by the multiplier K'. is there.
Like the detection circuit 16 described above, it is not always necessary to configure the output of the feedback path immediately before adding it to the input signal. As a result, the detection circuit shown in FIGS. 2 and 3 used in the first and second embodiments described above is obtained. If the rounding operation in the absolute value state shown is performed on the feedback path output, a cyclic digital filter in which no limit cycle occurs can be constructed, and the number of digits to be calculated as in the subtraction circuit 17 of the present embodiment. It can be seen that a smaller number can be formed and a more effective one can be configured in terms of circuit scale. It should be noted that even if the output of the detection circuit 16 is led to the addition circuit 18 instead of the subtraction circuit 17, the same effect as that of this embodiment can be easily inferred.
In the above first, second, and third embodiments, the delay time for delaying the signals of the delay circuit 8 (FIG. 1) and the delay circuit 14 (FIG. 5) is set to one sampling period T. This is due to the characteristics of the recursive digital filter, mT (m = 1,2, ...)
Needless to say, it is also obvious that the multiplication circuit 9 and the multiplication circuit 15 are equivalent even if they are simply bit-shifted.
Next, FIG. 6 is a block diagram of an emphasis device used in a VTR or the like, to which the cyclic digital filter of the present invention is applied. A video signal digitized by the sampling period T is input to the input terminal 19 as an input signal. The difference circuit 20 takes out a change amount of the video signal during the m times (m = 1, 2, ...) Sampling period mT and leads it to the cyclic digital filter 21 of the present invention. The output of the cyclic digital filter 21 is multiplied by the multiplier A by the multiplication circuit 22, and then added to the input signal from the input terminal 19 by the adder circuit 23 and sent to the output terminal 24 to become an output signal. Here, the recursive digital filter 21 has the same configuration as that of the first or second embodiment of the present invention shown in FIG. 1, but the time for delaying the signal of the delay circuit 8 is mT here.
Further, the transfer equation E ( z ) of the emphasis device configured as described above is as follows.
The present emphasis device will be described below.
First, the video signal input to the input terminal 19 is the difference circuit 20.
By this, the change per unit time is extracted. This difference circuit
20 itself has the characteristics of a high-pass filter (HPF) and does not pass the DC component of the video signal. In other words, if a DC signal is introduced to the difference circuit 20 as an input signal, there is no change per unit time, so zero is output. A signal such as the output of the difference circuit 20 which is composed only of high frequency components is added to the video signal which is the input signal by the adder circuit 23 through the recursive filter 21 and the multiplication circuit 22, and is output as an emphasis signal. This emphasis signal is used in a VTR or the like to emphasize the high frequency band of the video signal and relatively reduce noise in order to improve the S / N in the high frequency component when recording the video signal. In this emphasis device, it is one of the most important things to avoid that the DC level of the input video signal and the DC level of the output emphasis signal are different. This is because when recording a video signal, there is a frequency modulation (FM modulation) device after the emphasis device, and this frequency modulation is performed by the DC level of the signal. Therefore, if the DC signal level changes, it may cause deterioration of image quality. In the above sense, the cyclic digital filter 21 does not cause a limit cycle when a zero signal is obtained as its input signal (when there is no input), and the video signal input to the input terminal 19 and the output terminal 24 Matching the DC signal level with the emphasis signal from is very effective and has practical value.
The above-mentioned effects of the emphasis device can be said to be exactly the same as in the de-emphasis device used when reproducing the video signal. Further, not only the non-linear emphasis device and the non-linear de-emphasis device which are the signal processing circuits of the VTR have the same value, but the ROM configured as a non-linear element in the meaning of the digital signal processing of the two devices, The capacity can be reduced in consideration of the number of significant digits of the signal.
Next, as another application example, an HPF composed of a differential circuit for extracting a variation of a signal per unit time of m times the sampling period mT and a cyclic digital filter of the present invention having the output of the differential circuit as an input. Give. This HPF transfer equation G (
z ) is However, consider the case where the multiplier K (0 <K <1) is very close to 1 (K1). At this time, the HPF of G ( z ) does not allow the direct current component to pass through at all, but since it is K1, it has the HPF characteristic of allowing the relatively low frequency component signal to pass through. This HPF characteristic is used to a reproduced video signal in which a low-pass converted color signal such as a VTR and a frequency-modulated luminance signal are mixed, and a great effect is obtained. Because if the reproduced video signal contains a DC component,
The DC signal is also included in the chrominance signal separated from the luminance signal by the low pass filter (LPF), and the frequency conversion signal component is output when the frequency of this is converted to a high frequency. Is necessary.
As described above, in the HPF configuration in which the differential circuit is provided in the preceding stage of the recursive digital filter of the present invention, as in the second term on the right side of the equation (25) and G ( z ) in the equation (26), the value of K is If it is close to 1, there is an advantage that the effective digit of the input signal, the effective digit of the output signal and the effective digit of the signal to be fed back can be made substantially equal. HP above
In F, in order to output without deteriorating the accuracy of the input signal, it suffices to increase the dynamic range of the output signal by at least one digit (1 bit) with respect to the dynamic range of the input signal. Because the maximum gain of HPF is 2 / H obtained when Z - m = -1 in Eq. (26) G ( z ) , for example.
This is because the maximum gain 2 / HK becomes 1 <2 / HK <2 because K is in the range of 0 <K <1. Therefore, it goes without saying that the feedback signal when such an output signal is fed back to the input side can also have the same dynamic range as the output signal, but if a limit cycle such as that of a conventional recursive digital filter occurs, the effect is limited. Since it becomes large, the number of digits in the signal in the return path must be increased to reduce the effect. In particular, for example, if the multiplier K'in the above-mentioned third embodiment (equation (24) H ' ( z ) ) is small, the error width of the DC level caused by the limit cycle becomes large, so that the number of signal digits in the feedback path is increased. I had to make it bigger. However, if a cyclic digital filter that does not cause any limit cycle is used as in the present invention, the number of signal digits in the feedback path can be made equal to the number of effective digits of the output signal, and the effect is very large. In particular, in a device including a non-linear element such as the non-linear emphasis device or non-linear de-emphasis device described above, the feedback gain is determined by the ROM configuration for the feedback signal, but the number of digits of the feedback signal and the number of digits of the feedback path output at that time are determined. It is very practical that the value of can be small because the ROM capacity can be reduced. Furthermore, if the delay time of the feedback path is large, such as a recursible comb filter (when m is large in Eq. (26) G ( z )) , the number of digits of the feedback path signal can be small. Requires many delay elements for 1 bit of signal (1 digit of signal),
The effect of reducing the circuit scale becomes enormous.
EFFECTS OF THE INVENTION As described above, according to the present invention, in a recursive digital filter having a signal having only a high frequency component as an input, no limit cycle occurs at all, so that the practical effect is large. Especially when used in the HPF which constitutes the emphasis / de-emphasis device and the non-linear emphasis / non-linear de-emphasis device in the video signal processing such as VTR, not only does it not change the DC level of the signal, but also the digit of the signal in the return path. Since the number can be configured with a size equivalent to the number of significant digits of the input signal and the output signal, it is possible to reduce the circuit scale of the feedback path and further reduce the quantization error in relation to the feedback gain. Becomes
FIG. 1 is a block diagram of a recursive digital filter according to the first and second embodiments of the present invention, FIG. 2 is an input / output diagram of a rounding operation according to the first embodiment of the present invention, and FIG. Input / output diagram of the rounding operation in the embodiment of FIG.
FIG. 5 is a circuit diagram showing an embodiment of the detection circuit in the embodiment of the invention, FIG. 5 is a block diagram of a recursive digital filter of the third embodiment of the present invention, and FIG. 6 uses the recursive digital filter of the present invention. Block diagram of Emphasis device, No. 7
FIG. 8 is a block diagram of a conventional recursive digital filter, and FIGS. 8 and 9 are input / output diagrams of the rounding operation in the conventional example of FIG. 8,14 ... delay circuit, 9,15 ... multiplication circuit, 10, 17 ... detection circuit, 11 ... addition circuit, 16 ... subtraction circuit.
Priority Applications (1)
|Application Number||Priority Date||Filing Date||Title|
|JP60142903A JPH0732347B2 (en)||1985-06-28||1985-06-28||Circuit type digital filter|
Applications Claiming Priority (1)
|Application Number||Priority Date||Filing Date||Title|
|JP60142903A JPH0732347B2 (en)||1985-06-28||1985-06-28||Circuit type digital filter|
|Publication Number||Publication Date|
|JPS623517A JPS623517A (en)||1987-01-09|
|JPH0732347B2 true JPH0732347B2 (en)||1995-04-10|
Family Applications (1)
|Application Number||Title||Priority Date||Filing Date|
|JP60142903A Expired - Lifetime JPH0732347B2 (en)||1985-06-28||1985-06-28||Circuit type digital filter|
Country Status (1)
|JP (1)||JPH0732347B2 (en)|
Families Citing this family (4)
|Publication number||Priority date||Publication date||Assignee||Title|
|JP2609630B2 (en) *||1987-09-26||1997-05-14||株式会社東芝||Divider and division method|
|JPH10233652A (en) *||1997-02-20||1998-09-02||Mitsubishi Electric Corp||Recursive digital filter|
|JP5006423B2 (en) *||2010-03-26||2012-08-22||株式会社ナナオ||Cyclic noise removal apparatus or method|
|JP5687010B2 (en) *||2010-08-26||2015-03-18||日本無線株式会社||Rounding method and program|
Family Cites Families (3)
|Publication number||Priority date||Publication date||Assignee||Title|
|US3997770A (en) *||1973-07-09||1976-12-14||U.S. Philips Corporation||Recursive digital filter|
|JPS56111896A (en) *||1980-02-08||1981-09-03||Hitachi Ltd||Voice synthetizer|
|JPS56158525A (en) *||1980-05-12||1981-12-07||Nec Corp||Circulation type digital filter|
- 1985-06-28 JP JP60142903A patent/JPH0732347B2/en not_active Expired - Lifetime
Also Published As
|Publication number||Publication date|
|CA1228156A (en)||Apparatus for symmetrically truncating two's complement binary signals|
|EP0092400B1 (en)||Digital synchronization technique|
|FI90607B (en)||Digital scaling circuit to compensate for the cut-off deviation|
|US4872129A (en)||Digital decimation filter|
|US4442454A (en)||Image processing method using a block overlap transformation procedure|
|JP2508616B2 (en)||Sampling rate converter|
|US4652907A (en)||Apparatus for adaptively controlling a video signal recursive filter|
|EP0196193B1 (en)||A video signal recursive filter with luma/chroma separation|
|AT389966B (en)||Digital filter|
|US4953114A (en)||Image signal processing apparatus|
|US4313173A (en)||Linear interpolator|
|JP2910855B2 (en)||FSK discriminator|
|EP0310032A2 (en)||Motion detection circuit|
|CA1204170A (en)||Apparatus for generating scaled weighting coefficients for sampled data filters|
|CA1191960A (en)||Digital matrixing system|
|US5208594A (en)||Signal processor that uses a delta-sigma modulation|
|DE3625612C2 (en)||Circuit device for digital signal overflow correction|
|US4016410A (en)||Signal processor with digital filter and integrating network|
|JP3863294B2 (en)||Noise reduction signal processing circuit and video display device|
|US4193118A (en)||Low pass digital averaging filter|
|EP0141969B1 (en)||Method and circuit arrangement for improving picture quality by movement-controlled dpcm coding|
|KR100462447B1 (en)||Apparatus symmetrically reducing "n" least siginficant bits of an m-bit digital signal|
|JPH0642619B2 (en)||Interpolative time-discrete filter device|
|EP0146963A2 (en)||Iir digital filter|
|JPH0720265B2 (en)||Video signal processing circuit|