JPS63139492A - Acc circuit - Google Patents

Acc circuit

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Publication number
JPS63139492A
JPS63139492A JP28840686A JP28840686A JPS63139492A JP S63139492 A JPS63139492 A JP S63139492A JP 28840686 A JP28840686 A JP 28840686A JP 28840686 A JP28840686 A JP 28840686A JP S63139492 A JPS63139492 A JP S63139492A
Authority
JP
Japan
Prior art keywords
circuit
value
input terminal
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28840686A
Other languages
Japanese (ja)
Inventor
Hideyuki Terane
寺根 秀幸
Kenji Murakami
謙二 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP28840686A priority Critical patent/JPS63139492A/en
Publication of JPS63139492A publication Critical patent/JPS63139492A/en
Pending legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To stabilize an operation with simple circuit constitution by adding the amplitude value of a burst signal for one horizontal period, dividing a prescribed reference value by this added value, calculating the average value of the quotient for every one vertical period to have a multiplexer in a multiplication circuit. CONSTITUTION:A burst amplitude value calculating circuit 2 calculates the amplitude value of the burst signal and this calculated value is applied to one input terminal of an addition circuit 9 and a value outputted from this addition circuit 9 is applied to the other input terminal of the circuit 9. A value outputted from an addition circuit 12 is applied to a shifter 13, shifted by one bit and outputted. This operation is repeated for every one vertical period, thereby, the average value for every one vertical period of a quotient is calculated. The average value outputted from the shifter 13 is applied to the multiplication circuit 7, the multiplication circuit 7 multiplies this average value by a chrome signal from an input terminal 1 as themultiplier, an output signal of a prescribed level is taken out to an output terminal 8 and in such a way, an ACC operation is executed.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は、映像信号をディジタル化して処理を行なう
ようにしfこ、カラープレビジョン受信機に使用される
ACC回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ACC circuit for digitizing and processing a video signal and used in a color preview receiver.

[従来の技術] 第2図は従来のACC回路を示すブロック図である。[Conventional technology] FIG. 2 is a block diagram showing a conventional ACC circuit.

初めにこのACC回路の構成について説明する。First, the configuration of this ACC circuit will be explained.

図において、入力端子1は乗算回路7の一方の入力端子
に接続されるとともに、バースト振幅値計算回路2.f
fi幅最大値取込回路3.誤差信号発生回路4.アキュ
ムレータ6を介して乗算回路7の他方の入力端子に接続
される。5は所定看照値が入力される入力端子である。
In the figure, an input terminal 1 is connected to one input terminal of a multiplication circuit 7, and a burst amplitude value calculation circuit 2. f
fi width maximum value acquisition circuit 3. Error signal generation circuit 4. It is connected to the other input terminal of the multiplication circuit 7 via the accumulator 6 . 5 is an input terminal to which a predetermined reference value is input.

乗算回路7は出力端子8に接続される。Multiplier circuit 7 is connected to output terminal 8 .

次にこのACC回路の動作について説明する。Next, the operation of this ACC circuit will be explained.

入力端子1に8ピツトでディジタル化されたバースト信
号を含むクロマ信号が入力され、このクロマ信号は乗算
回路7の一方の入力端子およびバースト振幅値計算回路
2に与えられる。バースト振幅値計算回路2はバースト
信号の振幅値を計算し、この計W値は振幅最大値取込回
路3に与えられる。
A chroma signal including a burst signal digitized with 8 pits is input to an input terminal 1, and this chroma signal is applied to one input terminal of a multiplier circuit 7 and a burst amplitude value calculation circuit 2. The burst amplitude value calculation circuit 2 calculates the amplitude value of the burst signal, and this total W value is given to the maximum amplitude value acquisition circuit 3.

振幅最大値取込回路3は゛1水水平開ごとのバースト信
号の振幅値の最大値を取込み、この取込まれた値は誤差
信号発生回路4に与えられる。誤差信号発生回路4は入
力端子5から入力される参照値と上記取込まれた値との
差を計算して誤差信号を出力する。この誤差信号はアキ
ュムレータ6に与えられ、アキュムレータ6はこの誤差
信号を蓄積する。乗算回路7はアキュムレータ6からの
誤差信号によりその乗数をロジックひ決定し、この乗数
を入力端子1からのクロマ信号に乗鼻することで出力信
号のレベルが上記参照値に等しくされる。
The maximum amplitude value acquisition circuit 3 acquires the maximum amplitude value of the burst signal for each horizontal opening, and this acquired value is given to the error signal generation circuit 4. The error signal generation circuit 4 calculates the difference between the reference value inputted from the input terminal 5 and the above-mentioned input value, and outputs an error signal. This error signal is given to the accumulator 6, and the accumulator 6 accumulates this error signal. The multiplier circuit 7 logically determines its multiplier based on the error signal from the accumulator 6, and multiplies this multiplier by the chroma signal from the input terminal 1, thereby making the level of the output signal equal to the reference value.

[発明が解決しようとする問題点] 従来のACC回路は以上のように構成されているので、
回路構成が?!!雑となり、またバースト信号の振幅の
最大値を取込むため、バースト信号のレベルがパルスノ
イズなどで大幅に変化したときなどに画像が乱されるこ
とが多くなるという問題点があった・ この発明は上記のような問題点を解消するためになされ
たもので、回路構成が簡単で、かつ安定な動作が得られ
るACC回路を得ることを目的とする。
[Problems to be solved by the invention] Since the conventional ACC circuit is configured as described above,
What is the circuit configuration? ! ! Furthermore, since the maximum value of the amplitude of the burst signal is captured, the image is often disturbed when the level of the burst signal changes significantly due to pulse noise, etc. This was made to solve the above-mentioned problems, and the purpose is to obtain an ACC circuit with a simple circuit configuration and stable operation.

[問題点を解決するための手段] この発明に係るACC回路は、入力端子にディジタル化
きれたバースト信号を含むクロマ信号を入力し、振幅値
計算手段により入力端子からのりOマ信号のバースト信
号の振幅値を計算し、加算手段により振幅値計算手段出
力を1水平期間ごとに加算し、除算手段により1水平期
間ごとの加算手段出力で所定参照値を除算し、平均値算
出手段により除算手段出力の1垂直期間ごとの平均値を
算出し、乗算手段により平均値算出手段出力を入力端子
からのクロマ信号に乗算するものである。
[Means for Solving the Problems] The ACC circuit according to the present invention inputs a chroma signal including a fully digitized burst signal to an input terminal, and calculates a burst signal of an O chroma signal from the input terminal using an amplitude value calculation means. , the adding means adds the output of the amplitude value calculating means for each horizontal period, the dividing means divides the predetermined reference value by the adding means output for each horizontal period, and the average value calculating means divides the predetermined reference value by the output of the adding means for each horizontal period. The average value of the output for each vertical period is calculated, and the output of the average value calculation means is multiplied by the chroma signal from the input terminal by the multiplication means.

[作用] この発明においては、バースト信号の振幅値を1水平期
間ごとに加算し、この加算した値で所定参照値を除算し
、この商の1垂直期間ごとの平均値を算出して乗算回路
の乗数としているので、従来の誤差信号から乗算回路の
乗数をロジックで決定する場合に比べて回路構成が簡単
になり、また、成るバースト信号のレベルがパルスノイ
ズなどで大幅に変化したときでも、従来のバースト信号
の最大振幅値をもとにして乗算回路の乗数を決定する場
合に比べてACC回路の動作は安定する。
[Operation] In the present invention, the amplitude values of the burst signals are added for each horizontal period, a predetermined reference value is divided by this added value, and the average value of this quotient for each vertical period is calculated. Since the multiplier is set as a multiplier of The operation of the ACC circuit is more stable than the conventional case where the multiplier of the multiplier circuit is determined based on the maximum amplitude value of the burst signal.

〔実施例] 以下、この発明の実施例を図について説明する。〔Example] Embodiments of the present invention will be described below with reference to the drawings.

なお、この実施例の説明において、従来の技術の説明と
重複する部分については適宜その説明を省略する。
In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

第1図はこの発明の実施例であるACC回路のブロック
図である。
FIG. 1 is a block diagram of an ACC circuit according to an embodiment of the present invention.

この実施例の構成が第2図のACC回路の構成と異なる
点は以下の点である。すなわち、バースト振幅値計算回
路2は加算回路9の一方の入力端子に接続され、9の出
力端子はその他方の入力端子に接続される。加算回路9
の出力端子は除算回路10を介して加算回路12の一方
の入力端子に接続され、加算回路12はシフター13を
介して乗算回路7の他方の入力端子に接続される。また
シフター13の出力端子は加算回路12の他方の入力端
子に接続される。11は所定参照値が入力される入力端
子である。
The configuration of this embodiment differs from the configuration of the ACC circuit shown in FIG. 2 in the following points. That is, the burst amplitude value calculation circuit 2 is connected to one input terminal of the adder circuit 9, and the output terminal of 9 is connected to the other input terminal. Addition circuit 9
The output terminal of is connected to one input terminal of an adder circuit 12 via a divider circuit 10, and the adder circuit 12 is connected to the other input terminal of a multiplier circuit 7 via a shifter 13. Further, the output terminal of the shifter 13 is connected to the other input terminal of the adder circuit 12. 11 is an input terminal to which a predetermined reference value is input.

次にこのACC回路の動作について説明する。Next, the operation of this ACC circuit will be explained.

入力端子1に8ビツトでディジタル化されたバースト信
号を含むクロマ信号が入力され、このクロマ信号は乗算
回路7の一方の入力端子に与えられるとともにバースト
振幅値計算回路2に与えられる。バースト振幅値計算回
路2はバースト信号の振幅値を計算し、この計算値は加
算回路9の一方の入力端子に与えられ、9の他方の入力
端子にはこの加算回路9から出力された値が与えられる
A chroma signal containing an 8-bit digitized burst signal is input to an input terminal 1, and this chroma signal is applied to one input terminal of a multiplier circuit 7 and also to a burst amplitude value calculation circuit 2. The burst amplitude value calculation circuit 2 calculates the amplitude value of the burst signal, and this calculated value is given to one input terminal of the adder circuit 9, and the value output from the adder circuit 9 is given to the other input terminal of the adder circuit 9. Given.

これによって、加算回路9はバースト信号の振幅値を1
水平期間ごとに加算し、この加算された値は除算回路1
oに与えられる。除算回路10は入力端子11から入力
される所定参照値をこの加算された値で除算し、この商
が加算回路12の一方の入力端子に与えられる。加算回
路12の他方の入力端子には最初のみ一方の入力端子に
与えられる値と同じ値が入力され、それ以降はシフター
13から出力される値が入力される。加算回路12から
出力された値はシフター13に与えられ、LSB側に1
ビツトシフトした後出力される。この操作を1垂直期間
ごとに繰返すことによって、上記商の1垂直期間ごとの
平均値が計算される。シフター13から出力されたこの
平均値は乗算回路7に与えられ、乗算回路7はこの平均
値をその乗数として入力端子1からのクロマ信号に乗算
して、出力端子8に所定レベルの出力信号が取出され、
このようにしてACC動作が行なわれる。
As a result, the adder circuit 9 increases the amplitude value of the burst signal by 1.
It is added for each horizontal period, and this added value is sent to divider circuit 1.
given to o. The division circuit 10 divides the predetermined reference value input from the input terminal 11 by this added value, and the quotient is given to one input terminal of the addition circuit 12. The same value as the value given to one input terminal is input to the other input terminal of the adder circuit 12 only at the beginning, and thereafter the value output from the shifter 13 is input. The value output from the adder circuit 12 is given to the shifter 13, and 1 is added to the LSB side.
Output after bit shifting. By repeating this operation for each vertical period, the average value of the above quotient for each vertical period is calculated. This average value output from the shifter 13 is given to the multiplication circuit 7, which multiplies the chroma signal from the input terminal 1 by using this average value as a multiplier, so that an output signal of a predetermined level is output to the output terminal 8. taken out,
The ACC operation is performed in this manner.

以上のように、この実施例においては、バースト信号の
振幅値を1水平期間ごとに加算し、この加算した値で所
定参照値を除算し、この商の1垂直期間ごとの平均値を
算出してこれを乗算回路の乗数としているので、従来の
誤差信号から乗算回路の乗数をロジックで決定する場合
に比べて回路構成が簡単になり、また、成るバースト信
号のレベルがパルスノイズなどで大幅に変化したときで
も、従来のバースト信号の最大振幅値をもとにして乗算
回路の乗数を決定する場合に比べてACC回路の動作は
安定する。
As described above, in this embodiment, the amplitude values of the burst signals are added for each horizontal period, a predetermined reference value is divided by this added value, and the average value of this quotient for each vertical period is calculated. This is used as the multiplier of the multiplier circuit, which simplifies the circuit configuration compared to the conventional method in which the multiplier of the multiplier circuit is determined from the error signal using logic. Also, the level of the resulting burst signal is significantly reduced by pulse noise, etc. Even when the amplitude changes, the operation of the ACC circuit is more stable than in the conventional case where the multiplier of the multiplier circuit is determined based on the maximum amplitude value of the burst signal.

[発明の効果] 以上のようにこの発明によれば、振幅値計算手段により
クロマ信号のバースト信号の振幅値を計算し、加算手段
により振幅値計算手段出力を1水平期間ごとに加算し、
除算手段により1水平期間ごとの加算手段出力で所定参
照値を除算し、平均値算出手段により除算手段出力の1
垂直期間ごとの平均値を算出し、乗算手段により平均値
算出手段出力をりOマ信号に乗算するようにしたので、
回路構成が簡単で、かつ安定な動作が得られるACC回
路を得ることができる。
[Effects of the Invention] As described above, according to the present invention, the amplitude value calculation means calculates the amplitude value of the burst signal of the chroma signal, and the addition means adds the outputs of the amplitude value calculation means every horizontal period,
The division means divides the predetermined reference value by the output of the addition means for each horizontal period, and the average value calculation means divides the output of the division means by 1.
The average value for each vertical period is calculated, and the output of the average value calculation means is multiplied by the O signal using the multiplication means.
An ACC circuit with a simple circuit configuration and stable operation can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例であるACC回路のブロック
図である。 第2図は従来のACC回路を示すブロック図である。 図において、1.5.11は入力端子、2はバースト擾
幅値計算回路、3は振幅最大値取込回路、4は誤差信号
発生回路、6はアキュムレータ、7は乗算回路、8は出
力端子、9,12は加算回路、1oは除算回路、13は
シフターである。 なお、各図中同一符号は同一または相当部分を示す。
FIG. 1 is a block diagram of an ACC circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing a conventional ACC circuit. In the figure, 1, 5, 11 are input terminals, 2 is a burst amplitude value calculation circuit, 3 is a maximum amplitude value acquisition circuit, 4 is an error signal generation circuit, 6 is an accumulator, 7 is a multiplication circuit, and 8 is an output terminal , 9 and 12 are adder circuits, 1o is a division circuit, and 13 is a shifter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 ディジタル化されたバースト信号を含むクロマ信号が入
力される入力端子と、 前記入力端子からの前記クロマ信号の前記バースト信号
の振幅値を計算する振幅値計算手段と、前記振幅値計算
手段出力を1水平期間ごとに加算する加算手段と、 前記1水平期間ごとの前記加算手段出力で所定参照値を
除算する除算手段と、 前記除算手段出力の1垂直期間ごとの平均値を算出する
平均値算出手段と、 前記平均値算出手段出力を前記入力端子からの前記クロ
マ信号に乗算する乗算手段とを備えたACC回路。
[Scope of Claims] An input terminal into which a chroma signal including a digitized burst signal is input; amplitude value calculation means for calculating the amplitude value of the burst signal of the chroma signal from the input terminal; addition means for adding the output of the value calculation means every horizontal period; division means for dividing a predetermined reference value by the output of the addition means for every horizontal period; and an average value of the output of the division means for every vertical period. An ACC circuit comprising: an average value calculation means for calculating; and a multiplication means for multiplying the output of the average value calculation means by the chroma signal from the input terminal.
JP28840686A 1986-12-02 1986-12-02 Acc circuit Pending JPS63139492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28840686A JPS63139492A (en) 1986-12-02 1986-12-02 Acc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28840686A JPS63139492A (en) 1986-12-02 1986-12-02 Acc circuit

Publications (1)

Publication Number Publication Date
JPS63139492A true JPS63139492A (en) 1988-06-11

Family

ID=17729796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28840686A Pending JPS63139492A (en) 1986-12-02 1986-12-02 Acc circuit

Country Status (1)

Country Link
JP (1) JPS63139492A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02233086A (en) * 1989-03-07 1990-09-14 Sony Corp Color television receiver
JPH03195162A (en) * 1989-12-22 1991-08-26 Fujitsu Ltd Redial system for exchange of additional number dial-in call incoming
US5661530A (en) * 1993-03-17 1997-08-26 Sanyo Electric Co., Ltd. Television circuit utilizing color burst signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02233086A (en) * 1989-03-07 1990-09-14 Sony Corp Color television receiver
JPH03195162A (en) * 1989-12-22 1991-08-26 Fujitsu Ltd Redial system for exchange of additional number dial-in call incoming
US5661530A (en) * 1993-03-17 1997-08-26 Sanyo Electric Co., Ltd. Television circuit utilizing color burst signal

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