JPS57203330A - Decimal-to-binary converting circuit - Google Patents
Decimal-to-binary converting circuitInfo
- Publication number
- JPS57203330A JPS57203330A JP8899381A JP8899381A JPS57203330A JP S57203330 A JPS57203330 A JP S57203330A JP 8899381 A JP8899381 A JP 8899381A JP 8899381 A JP8899381 A JP 8899381A JP S57203330 A JPS57203330 A JP S57203330A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- binary
- decimal
- fed
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two
- H03M7/08—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two the radix being ten, i.e. pure decimal code
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To decrease the converting time of numerical value for a decimal- binary converting circuit, by using hardware circuits including a storage circuit, a binary adder circuit, a digit designating circuit, a latch circuit, etc. and eliminating a converting process using a software. CONSTITUTION:A decimal-binary converting circuit includes the 1st latch circuit 1 which stores an N-digit decimal number, a digit designating circuit which designates each digit, and a multiplexer circut 3 having a data input D and a control input C that deliver each digit value given from the circuits 2 and 1. The output of the circuit 1 is fed to the data input of the circuit 3, and the output of the circuit 2 is fed to the input C of the circuit 3. Furthermore, a decimal number is converted into a binary number and stored in a storage circut 4, and the outputs of the circuits 2 and 3 are fed to the circuit 4. The output converted into a binary number given from the circuit 4 is fed to the input A of one side of a binary adder circut 5. The output of the circut 5 is temporarily latched at the 2nd latch circuit 6. The output of the circuit 6 is fed to the input B of the other side of the circuit 5. Thus the time can be decreased for the decimal- binary converting process without using any software.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8899381A JPS57203330A (en) | 1981-06-10 | 1981-06-10 | Decimal-to-binary converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8899381A JPS57203330A (en) | 1981-06-10 | 1981-06-10 | Decimal-to-binary converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57203330A true JPS57203330A (en) | 1982-12-13 |
Family
ID=13958331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8899381A Pending JPS57203330A (en) | 1981-06-10 | 1981-06-10 | Decimal-to-binary converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57203330A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59177646A (en) * | 1983-03-29 | 1984-10-08 | Nec Corp | Decimal-binary converting system |
-
1981
- 1981-06-10 JP JP8899381A patent/JPS57203330A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59177646A (en) * | 1983-03-29 | 1984-10-08 | Nec Corp | Decimal-binary converting system |
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