GB921330A - Improvements relating to code converters - Google Patents

Abstract

921,330. Binary to binary-coded-decimal converters. ELECTRIC & MUSICAL INDUSTRIES Ltd. May 4, 1959 [May 2, 1958], No. 13996/58. Class 106 (1). In a system for converting a pure binary number into a binary-coded-decimal number the pure binary number is shifted, most significant bit first, from a register 2 into an accumulating register 1 which is notionally divided into decimal stages R0, R10, R100, &c., each comprising six bits, and after each shift the binary " filler " number 110110 ( = 2<SP>6</SP> - 10 = 54) is added to each decimal stage R0, R10 . . ., &c., and is immediately subtracted from all those decimal stages that do not send a carry to their adjacent stages. The effect of this is that when any decimal stage contains bits which represent, in the binary scale, ten or more, then ten is subtracted from that stage and one is added to the next decimal stage. The circuit described is controlled by a unit 3 and each cycle of operation comprises the following steps. First the registers 1 and 2 are shifted one position, register 2 to the right and register 1 to the left. Then a pulse or a line 15 and on an " add " line 8 causes " filler " digit generators 16, 17 . . . 21 to add a filler digit to each decimal stage. This is followed by a further pulse on line 15 together with a pulse on a " subtract " lead 8 but this time the pulse on lead 15 is inhibited from reaching the filler digit generator of any stage from which a carry has occurred so tnat the filler digit is only subtracted from those stages not producing a carry. This cycle is repeated. The register 2 contains 36 bits so that a decimal register with 12 stages is required. Register 1, however, only contains 6 stages and thus after only 18 or 19 cycles bits may overflow from the left-hand end of register 1. These bits are entered into register 2 which is gradually being emptied. Thus after 36 cycles the lowest 6 decimal denominations will be correctly registered in register 1 but the higher denominations, which will be in register 2 will not have been properly converted. This situation is remedied by transferring the contents of register 1 to a further register (not shown) and then shifting the contents of register 2 into register 1 during a further 36 cycles. The shift register 2 and the accumulator register 1 could be as described in Specifications 893,355 and 893,353 respectively, both these Specifications being referred to.