JPS574630A - Series data synchronizing system - Google Patents

Series data synchronizing system

Info

Publication number
JPS574630A
JPS574630A JP7832880A JP7832880A JPS574630A JP S574630 A JPS574630 A JP S574630A JP 7832880 A JP7832880 A JP 7832880A JP 7832880 A JP7832880 A JP 7832880A JP S574630 A JPS574630 A JP S574630A
Authority
JP
Japan
Prior art keywords
series data
clock
bit
data
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7832880A
Other languages
Japanese (ja)
Inventor
Takashi Nara
Yoshiaki Matsuura
Kenzo Aoki
Yoshitaka Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7832880A priority Critical patent/JPS574630A/en
Publication of JPS574630A publication Critical patent/JPS574630A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/45—Transmitting circuits; Receiving circuits using electronic distributors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To eliminate a correction of phase based on a delay of transmission, by converting a series data into a parallel data with every plural bits and based on the clock synchronizing with each bit of the series data and the clock synchronizing with every plural bits of the series data. CONSTITUTION:The series data sent via a transmission line 56 are stored successively in a shift register 60 in accordance with the basic clock supplied via a transmission line 54. Then these stored data are transferred in parallel to D-type flip-flop 62, 64, 66 and 68 by the 4-bit synchronizing clock supplied via a transmssion line 58 with every storage of the 4-bit series data. On the other hand, the series data given from a terminal device 42 receives a series-parallel conversion with every plural bits and by the clock synchronizing with each bit of the series data and the clock synchronizing with plural bits. This received data that received a parallel conversion is sampled by the clock at the side of a master device 40.
JP7832880A 1980-06-12 1980-06-12 Series data synchronizing system Pending JPS574630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7832880A JPS574630A (en) 1980-06-12 1980-06-12 Series data synchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7832880A JPS574630A (en) 1980-06-12 1980-06-12 Series data synchronizing system

Publications (1)

Publication Number Publication Date
JPS574630A true JPS574630A (en) 1982-01-11

Family

ID=13658894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7832880A Pending JPS574630A (en) 1980-06-12 1980-06-12 Series data synchronizing system

Country Status (1)

Country Link
JP (1) JPS574630A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671255B2 (en) * 1988-04-01 1994-09-07 ディジタル イクイプメント コーポレーション Stabilized data transfer method
KR100452705B1 (en) * 1997-10-25 2005-01-27 엘지전자 주식회사 Apparatus for Fetching Data in Serial Data Communication and Method Thereof
US10873441B2 (en) * 2019-03-29 2020-12-22 Teledyne E2V Semiconductors Sas Method for synchronizing digital data sent in series

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244107A (en) * 1975-10-03 1977-04-06 Hitachi Ltd High-speed circular/serial data transmission system
JPS52144909A (en) * 1976-05-28 1977-12-02 Hitachi Ltd Transmission by clock folding

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244107A (en) * 1975-10-03 1977-04-06 Hitachi Ltd High-speed circular/serial data transmission system
JPS52144909A (en) * 1976-05-28 1977-12-02 Hitachi Ltd Transmission by clock folding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671255B2 (en) * 1988-04-01 1994-09-07 ディジタル イクイプメント コーポレーション Stabilized data transfer method
KR100452705B1 (en) * 1997-10-25 2005-01-27 엘지전자 주식회사 Apparatus for Fetching Data in Serial Data Communication and Method Thereof
US10873441B2 (en) * 2019-03-29 2020-12-22 Teledyne E2V Semiconductors Sas Method for synchronizing digital data sent in series

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